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    bool retval = false;

    u32_t bus, last_bus;

    PCITAG tag;

    if( (last_bus = PciApi(1))==-1)

    for(bus=0;bus<=last_bus;bus++)

        u32_t devfn;

        for(devfn=0;devfn<256;devfn++)

            hc_t *hc;

            u32_t id;

            u16_t devclass;

            u8_t  interface;

            int i;

            interface = PciRead8(bus,devfn, 0x09);

            if( devclass != 0x0C03)

                continue;

            if( interface != 0)

            pcicmd = PciRead16(bus,devfn, PCI_COMMAND);

                continue;

            hc = (hc_t*)kmalloc(sizeof(hc_t), 0);

            hc->pciId  = PciRead32(bus,devfn, 0);

            for (i = 0; i < 6; i++)

                u32_t base;

                bool validSize;

                base = PciRead32(bus,devfn, PCI_MAP_REG_START + (i << 2));

                {

                    if (base & PCI_MAP_IO) {

                        hc->ioBase[i] = (addr_t)PCIGETIO(base);

                        hc->memType[i]   = base & PCI_MAP_IO_ATTR_MASK;

                    } else {

                        hc->memBase[i] = (u32_t)PCIGETMEMORY(base);

                        hc->memType[i] = base & PCI_MAP_MEMORY_ATTR_MASK;

                    }

                }

            };

            list_add_tail(&hc->list, &hc_list);

            retval = true;

        };

    };

    return retval;

};

/* these helpers provide future and backwards compatibility

#define pci_resource_start(dev, bar)    ((dev)->resource[(bar)].start)

#define pci_resource_end(dev, bar)  ((dev)->resource[(bar)].end)

#define pci_resource_flags(dev, bar)    ((dev)->resource[(bar)].flags)

#define pci_resource_len(dev,bar) \

    ((pci_resource_start((dev), (bar)) == 0 &&  \

      pci_resource_end((dev), (bar)) ==     \

      pci_resource_start((dev), (bar))) ? 0 :   \

                            \

     (pci_resource_end((dev), (bar)) -      \

      pci_resource_start((dev), (bar)) + 1))

static int __devinit mmio_resource_enabled(struct pci_dev *pdev, int idx)

    return pci_resource_start(pdev, idx) && mmio_enabled(pdev);

}

static void __devinit quirk_usb_disable_ehci(struct pci_dev *pdev)

    int wait_time, delta;

    void __iomem *base, *op_reg_base;

    u32 hcc_params, val;

    u8  offset, cap_length;

    int count = 256/4;

    int tried_handoff = 0;

    if (!mmio_resource_enabled(pdev, 0))

    base = pci_ioremap_bar(pdev, 0);

        return;

    cap_length = readb(base);

    /* EHCI 0.96 and later may have "extended capabilities"

     * booting from USB disk or using a usb keyboard

     */

    hcc_params = readl(base + EHCI_HCC_PARAMS);

    offset = (hcc_params >> 8) & 0xff;

    while (offset && --count) {

        u32     cap;

        int     msec;

        pci_read_config_dword(pdev, offset, &cap);

        case 1:         /* BIOS/SMM/... handoff support */

            if ((cap & EHCI_USBLEGSUP_BIOS)) {

                dev_dbg(&pdev->dev, "EHCI: BIOS handoff\n");

#if 0

 * but that seems dubious in general (the BIOS left it off intentionally)

 * and is known to prevent some systems from booting.  so we won't do this

 * unless maybe we can determine when we're on a system that needs SMI forced.

 */

                /* BIOS workaround (?): be sure the

                 * pre-Linux code receives the SMI

                 */

                pci_read_config_dword(pdev,

                        offset + EHCI_USBLEGCTLSTS,

                        &val);

                pci_write_config_dword(pdev,

                        offset + EHCI_USBLEGCTLSTS,

                        val | EHCI_USBLEGCTLSTS_SOOE);

#endif

                /* some systems get upset if this semaphore is

                 * handoff..

                 */

                pci_write_config_byte(pdev, offset + 3, 1);

            }

            /* if boot firmware now owns EHCI, spin till

             */

            msec = 1000;

            while ((cap & EHCI_USBLEGSUP_BIOS) && (msec > 0)) {

                tried_handoff = 1;

                msleep(10);

                msec -= 10;

                pci_read_config_dword(pdev, offset, &cap);

            }

            if (cap & EHCI_USBLEGSUP_BIOS) {

                 * it down, and hope nothing goes too wrong

                 */

                dev_warn(&pdev->dev, "EHCI: BIOS handoff failed"

                        " (BIOS bug?) %08x\n", cap);

                pci_write_config_byte(pdev, offset + 2, 0);

            }

            /* just in case, always disable EHCI SMIs */

                    offset + EHCI_USBLEGCTLSTS,

                    0);

            /* If the BIOS ever owned the controller then we

             */

            if (tried_handoff)

                writel(0, op_reg_base + EHCI_CONFIGFLAG);

            break;

        case 0:         /* illegal reserved capability */

            cap = 0;

            /* FALLTHROUGH */

        default:

            dev_warn(&pdev->dev, "EHCI: unrecognized capability "

                    "%02x\n", cap & 0xff);

            break;

        }

        offset = (cap >> 8) & 0xff;

    }

    if (!count)

        dev_printk(KERN_DEBUG, &pdev->dev, "EHCI: capability loop?\n");

    /*

     */

    val = readl(op_reg_base + EHCI_USBSTS);

    if ((val & EHCI_USBSTS_HALTED) == 0) {

        val = readl(op_reg_base + EHCI_USBCMD);

        val &= ~EHCI_USBCMD_RUN;

        writel(val, op_reg_base + EHCI_USBCMD);

        wait_time = 2000;

        do {

            writel(0x3f, op_reg_base + EHCI_USBSTS);

            udelay(delta);

            wait_time -= delta;

            val = readl(op_reg_base + EHCI_USBSTS);

            if ((val == ~(u32)0) || (val & EHCI_USBSTS_HALTED)) {

                break;

            }

        } while (wait_time > 0);

    }

    writel(0, op_reg_base + EHCI_USBINTR);

    writel(0x3f, op_reg_base + EHCI_USBSTS);

    iounmap(base);

    return;

#endif

>