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Rev | Author | Line No. | Line |
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9079 | turbocat | 1 | #include |
2 | #include |
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3 | |||
4 | LIST_HEAD(devices); |
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5 | |||
6 | /* PCI control bits. Shares IORESOURCE_BITS with above PCI ROM. */ |
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7 | #define IORESOURCE_PCI_FIXED (1<<4) /* Do not move resource */ |
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8 | |||
9 | #define LEGACY_IO_RESOURCE (IORESOURCE_IO | IORESOURCE_PCI_FIXED) |
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10 | |||
11 | #define IORESOURCE_ROM_COPY (1<<2) /* ROM is alloc'd copy, resource field overlaid */ |
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12 | #define IORESOURCE_ROM_BIOS_COPY (1<<3) /* ROM is BIOS copy, resource field overlaid */ |
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13 | |||
14 | |||
15 | static inline unsigned int pci_calc_resource_flags(unsigned int flags) |
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16 | { |
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17 | if (flags & PCI_BASE_ADDRESS_SPACE_IO) |
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18 | return IORESOURCE_IO; |
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19 | |||
20 | if (flags & PCI_BASE_ADDRESS_MEM_PREFETCH) |
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21 | return IORESOURCE_MEM | IORESOURCE_PREFETCH; |
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22 | |||
23 | return IORESOURCE_MEM; |
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24 | } |
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25 | |||
26 | static u32 pci_size(u32 base, u32 maxbase, u32 mask) |
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27 | { |
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28 | u32 size = mask & maxbase; /* Find the significant bits */ |
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29 | |||
30 | if (!size) |
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31 | return 0; |
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32 | |||
33 | /* Get the lowest of them to find the decode size, and |
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34 | from that the extent. */ |
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35 | size = (size & ~(size-1)) - 1; |
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36 | |||
37 | /* base == maxbase can be valid only if the BAR has |
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38 | already been programmed with all 1s. */ |
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39 | if (base == maxbase && ((base | size) & mask) != mask) |
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40 | return 0; |
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41 | |||
42 | return size; |
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43 | } |
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44 | |||
45 | static u64 pci_size64(u64 base, u64 maxbase, u64 mask) |
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46 | { |
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47 | u64 size = mask & maxbase; /* Find the significant bits */ |
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48 | |||
49 | if (!size) |
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50 | return 0; |
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51 | |||
52 | /* Get the lowest of them to find the decode size, and |
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53 | from that the extent. */ |
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54 | size = (size & ~(size-1)) - 1; |
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55 | |||
56 | /* base == maxbase can be valid only if the BAR has |
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57 | already been programmed with all 1s. */ |
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58 | if (base == maxbase && ((base | size) & mask) != mask) |
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59 | return 0; |
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60 | |||
61 | return size; |
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62 | } |
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63 | |||
64 | static inline int is_64bit_memory(u32 mask) |
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65 | { |
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66 | if ((mask & (PCI_BASE_ADDRESS_SPACE|PCI_BASE_ADDRESS_MEM_TYPE_MASK)) == |
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67 | (PCI_BASE_ADDRESS_SPACE_MEMORY|PCI_BASE_ADDRESS_MEM_TYPE_64)) |
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68 | return 1; |
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69 | return 0; |
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70 | } |
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71 | |||
72 | static void pci_read_bases(struct pci_dev *dev, unsigned int howmany, int rom) |
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73 | { |
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74 | u32 pos, reg, next; |
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75 | u32 l, sz; |
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76 | struct resource *res; |
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77 | |||
78 | for(pos=0; pos < howmany; pos = next) |
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79 | { |
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80 | u64 l64; |
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81 | u64 sz64; |
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82 | u32 raw_sz; |
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83 | |||
84 | next = pos + 1; |
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85 | |||
86 | res = &dev->resource[pos]; |
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87 | |||
88 | reg = PCI_BASE_ADDRESS_0 + (pos << 2); |
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89 | l = PciRead32(dev->busnr, dev->devfn, reg); |
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90 | PciWrite32(dev->busnr, dev->devfn, reg, ~0); |
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91 | sz = PciRead32(dev->busnr, dev->devfn, reg); |
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92 | PciWrite32(dev->busnr, dev->devfn, reg, l); |
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93 | |||
94 | if (!sz || sz == 0xffffffff) |
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95 | continue; |
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96 | |||
97 | if (l == 0xffffffff) |
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98 | l = 0; |
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99 | |||
100 | raw_sz = sz; |
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101 | if ((l & PCI_BASE_ADDRESS_SPACE) == |
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102 | PCI_BASE_ADDRESS_SPACE_MEMORY) |
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103 | { |
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104 | sz = pci_size(l, sz, (u32)PCI_BASE_ADDRESS_MEM_MASK); |
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105 | /* |
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106 | * For 64bit prefetchable memory sz could be 0, if the |
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107 | * real size is bigger than 4G, so we need to check |
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108 | * szhi for that. |
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109 | */ |
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110 | if (!is_64bit_memory(l) && !sz) |
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111 | continue; |
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112 | res->start = l & PCI_BASE_ADDRESS_MEM_MASK; |
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113 | res->flags |= l & ~PCI_BASE_ADDRESS_MEM_MASK; |
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114 | } |
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115 | else { |
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116 | sz = pci_size(l, sz, PCI_BASE_ADDRESS_IO_MASK & 0xffff); |
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117 | if (!sz) |
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118 | continue; |
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119 | res->start = l & PCI_BASE_ADDRESS_IO_MASK; |
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120 | res->flags |= l & ~PCI_BASE_ADDRESS_IO_MASK; |
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121 | } |
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122 | res->end = res->start + (unsigned long) sz; |
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123 | res->flags |= pci_calc_resource_flags(l); |
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124 | if (is_64bit_memory(l)) |
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125 | { |
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126 | u32 szhi, lhi; |
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127 | |||
128 | lhi = PciRead32(dev->busnr, dev->devfn, reg+4); |
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129 | PciWrite32(dev->busnr, dev->devfn, reg+4, ~0); |
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130 | szhi = PciRead32(dev->busnr, dev->devfn, reg+4); |
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131 | PciWrite32(dev->busnr, dev->devfn, reg+4, lhi); |
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132 | sz64 = ((u64)szhi << 32) | raw_sz; |
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133 | l64 = ((u64)lhi << 32) | l; |
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134 | sz64 = pci_size64(l64, sz64, PCI_BASE_ADDRESS_MEM_MASK); |
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135 | next++; |
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136 | |||
137 | #if BITS_PER_LONG == 64 |
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138 | if (!sz64) { |
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139 | res->start = 0; |
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140 | res->end = 0; |
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141 | res->flags = 0; |
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142 | continue; |
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143 | } |
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144 | res->start = l64 & PCI_BASE_ADDRESS_MEM_MASK; |
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145 | res->end = res->start + sz64; |
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146 | #else |
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147 | if (sz64 > 0x100000000ULL) { |
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148 | printk(KERN_ERR "PCI: Unable to handle 64-bit " |
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149 | "BAR for device %s\n", pci_name(dev)); |
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150 | res->start = 0; |
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151 | res->flags = 0; |
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152 | } |
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153 | else if (lhi) |
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154 | { |
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155 | /* 64-bit wide address, treat as disabled */ |
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156 | PciWrite32(dev->busnr, dev->devfn, reg, |
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157 | l & ~(u32)PCI_BASE_ADDRESS_MEM_MASK); |
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158 | PciWrite32(dev->busnr, dev->devfn, reg+4, 0); |
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159 | res->start = 0; |
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160 | res->end = sz; |
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161 | } |
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162 | #endif |
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163 | } |
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164 | } |
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165 | |||
166 | if ( rom ) |
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167 | { |
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168 | dev->rom_base_reg = rom; |
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169 | res = &dev->resource[PCI_ROM_RESOURCE]; |
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170 | |||
171 | l = PciRead32(dev->busnr, dev->devfn, rom); |
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172 | PciWrite32(dev->busnr, dev->devfn, rom, ~PCI_ROM_ADDRESS_ENABLE); |
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173 | sz = PciRead32(dev->busnr, dev->devfn, rom); |
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174 | PciWrite32(dev->busnr, dev->devfn, rom, l); |
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175 | |||
176 | if (l == 0xffffffff) |
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177 | l = 0; |
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178 | |||
179 | if (sz && sz != 0xffffffff) |
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180 | { |
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181 | sz = pci_size(l, sz, (u32)PCI_ROM_ADDRESS_MASK); |
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182 | |||
183 | if (sz) |
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184 | { |
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185 | res->flags = (l & IORESOURCE_ROM_ENABLE) | |
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186 | IORESOURCE_MEM | IORESOURCE_PREFETCH | |
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187 | IORESOURCE_READONLY | IORESOURCE_CACHEABLE; |
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188 | res->start = l & PCI_ROM_ADDRESS_MASK; |
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189 | res->end = res->start + (unsigned long) sz; |
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190 | } |
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191 | } |
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192 | } |
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193 | } |
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194 | |||
195 | static void pci_read_irq(struct pci_dev *dev) |
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196 | { |
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197 | u8 irq; |
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198 | |||
199 | irq = PciRead8(dev->busnr, dev->devfn, PCI_INTERRUPT_PIN); |
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200 | dev->pin = irq; |
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201 | if (irq) |
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202 | irq = PciRead8(dev->busnr, dev->devfn, PCI_INTERRUPT_LINE); |
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203 | dev->irq = irq; |
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204 | }; |
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205 | |||
206 | |||
207 | int pci_setup_device(struct pci_dev *dev) |
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208 | { |
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209 | u32 class; |
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210 | |||
211 | class = PciRead32(dev->busnr, dev->devfn, PCI_CLASS_REVISION); |
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212 | dev->revision = class & 0xff; |
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213 | class >>= 8; /* upper 3 bytes */ |
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214 | dev->class = class; |
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215 | |||
216 | /* "Unknown power state" */ |
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217 | // dev->current_state = PCI_UNKNOWN; |
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218 | |||
219 | /* Early fixups, before probing the BARs */ |
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220 | // pci_fixup_device(pci_fixup_early, dev); |
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221 | class = dev->class >> 8; |
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222 | |||
223 | switch (dev->hdr_type) |
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224 | { |
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225 | case PCI_HEADER_TYPE_NORMAL: /* standard header */ |
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226 | if (class == PCI_CLASS_BRIDGE_PCI) |
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227 | goto bad; |
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228 | pci_read_irq(dev); |
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229 | pci_read_bases(dev, 6, PCI_ROM_ADDRESS); |
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230 | dev->subsystem_vendor = PciRead16(dev->busnr, dev->devfn,PCI_SUBSYSTEM_VENDOR_ID); |
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231 | dev->subsystem_device = PciRead16(dev->busnr, dev->devfn, PCI_SUBSYSTEM_ID); |
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232 | |||
233 | /* |
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234 | * Do the ugly legacy mode stuff here rather than broken chip |
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235 | * quirk code. Legacy mode ATA controllers have fixed |
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236 | * addresses. These are not always echoed in BAR0-3, and |
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237 | * BAR0-3 in a few cases contain junk! |
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238 | */ |
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239 | if (class == PCI_CLASS_STORAGE_IDE) |
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240 | { |
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241 | u8 progif; |
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242 | |||
243 | progif = PciRead8(dev->busnr, dev->devfn,PCI_CLASS_PROG); |
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244 | if ((progif & 1) == 0) |
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245 | { |
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246 | dev->resource[0].start = 0x1F0; |
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247 | dev->resource[0].end = 0x1F7; |
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248 | dev->resource[0].flags = LEGACY_IO_RESOURCE; |
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249 | dev->resource[1].start = 0x3F6; |
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250 | dev->resource[1].end = 0x3F6; |
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251 | dev->resource[1].flags = LEGACY_IO_RESOURCE; |
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252 | } |
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253 | if ((progif & 4) == 0) |
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254 | { |
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255 | dev->resource[2].start = 0x170; |
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256 | dev->resource[2].end = 0x177; |
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257 | dev->resource[2].flags = LEGACY_IO_RESOURCE; |
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258 | dev->resource[3].start = 0x376; |
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259 | dev->resource[3].end = 0x376; |
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260 | dev->resource[3].flags = LEGACY_IO_RESOURCE; |
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261 | }; |
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262 | } |
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263 | break; |
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264 | |||
265 | case PCI_HEADER_TYPE_BRIDGE: /* bridge header */ |
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266 | if (class != PCI_CLASS_BRIDGE_PCI) |
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267 | goto bad; |
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268 | /* The PCI-to-PCI bridge spec requires that subtractive |
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269 | decoding (i.e. transparent) bridge must have programming |
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270 | interface code of 0x01. */ |
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271 | pci_read_irq(dev); |
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272 | dev->transparent = ((dev->class & 0xff) == 1); |
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273 | pci_read_bases(dev, 2, PCI_ROM_ADDRESS1); |
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274 | break; |
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275 | |||
276 | case PCI_HEADER_TYPE_CARDBUS: /* CardBus bridge header */ |
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277 | if (class != PCI_CLASS_BRIDGE_CARDBUS) |
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278 | goto bad; |
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279 | pci_read_irq(dev); |
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280 | pci_read_bases(dev, 1, 0); |
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281 | dev->subsystem_vendor = PciRead16(dev->busnr, |
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282 | dev->devfn, |
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283 | PCI_CB_SUBSYSTEM_VENDOR_ID); |
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284 | |||
285 | dev->subsystem_device = PciRead16(dev->busnr, |
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286 | dev->devfn, |
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287 | PCI_CB_SUBSYSTEM_ID); |
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288 | break; |
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289 | |||
290 | default: /* unknown header */ |
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291 | printk(KERN_ERR "PCI: device %s has unknown header type %02x, ignoring.\n", |
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292 | pci_name(dev), dev->hdr_type); |
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293 | return -1; |
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294 | |||
295 | bad: |
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296 | printk(KERN_ERR "PCI: %s: class %x doesn't match header type %02x. Ignoring class.\n", |
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297 | pci_name(dev), class, dev->hdr_type); |
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298 | dev->class = PCI_CLASS_NOT_DEFINED; |
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299 | } |
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300 | |||
301 | /* We found a fine healthy device, go go go... */ |
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302 | |||
303 | return 0; |
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304 | }; |
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305 | |||
306 | static pci_dev_t* pci_scan_device(u32 busnr, int devfn) |
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307 | { |
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308 | pci_dev_t *dev; |
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309 | |||
310 | u32 id; |
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311 | u8 hdr; |
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312 | |||
313 | int timeout = 10; |
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314 | |||
315 | id = PciRead32(busnr, devfn, PCI_VENDOR_ID); |
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316 | /* some broken boards return 0 or ~0 if a slot is empty: */ |
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317 | if (id == 0xffffffff || id == 0x00000000 || |
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318 | id == 0x0000ffff || id == 0xffff0000) |
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319 | return NULL; |
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320 | |||
321 | while (id == 0xffff0001) |
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322 | { |
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323 | |||
324 | delay(timeout/10); |
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325 | timeout *= 2; |
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326 | |||
327 | id = PciRead32(busnr, devfn, PCI_VENDOR_ID); |
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328 | |||
329 | /* Card hasn't responded in 60 seconds? Must be stuck. */ |
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330 | if (timeout > 60 * 100) |
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331 | { |
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332 | printk(KERN_WARNING "Device %04x:%02x:%02x.%d not " |
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333 | "responding\n", busnr,PCI_SLOT(devfn),PCI_FUNC(devfn)); |
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334 | return NULL; |
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335 | } |
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336 | }; |
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337 | |||
338 | /* if( pci_scan_filter(id, busnr, devfn) == 0) |
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339 | return NULL;*/ |
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340 | |||
341 | hdr = PciRead8(busnr, devfn, PCI_HEADER_TYPE); |
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342 | |||
9827 | turbocat | 343 | dev = (pci_dev_t*)KernelZeroAlloc(sizeof(pci_dev_t)); |
9079 | turbocat | 344 | if(unlikely(dev == NULL)) |
345 | return NULL; |
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346 | |||
347 | INIT_LIST_HEAD(&dev->link); |
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348 | |||
349 | dev->pci_dev.busnr = busnr; |
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350 | dev->pci_dev.devfn = devfn; |
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351 | dev->pci_dev.hdr_type = hdr & 0x7f; |
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352 | dev->pci_dev.multifunction = !!(hdr & 0x80); |
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353 | dev->pci_dev.vendor = id & 0xffff; |
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354 | dev->pci_dev.device = (id >> 16) & 0xffff; |
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355 | |||
356 | pci_setup_device(&dev->pci_dev); |
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357 | |||
358 | return dev; |
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359 | |||
360 | }; |
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361 | |||
362 | |||
363 | |||
364 | int _pci_scan_slot(u32 bus, int devfn) |
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365 | { |
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366 | int func, nr = 0; |
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367 | |||
368 | for (func = 0; func < 8; func++, devfn++) |
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369 | { |
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370 | pci_dev_t *dev; |
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371 | |||
372 | dev = pci_scan_device(bus, devfn); |
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373 | if( dev ) |
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374 | { |
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375 | list_add(&dev->link, &devices); |
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376 | nr++; |
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377 | |||
378 | /* |
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379 | * If this is a single function device, |
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380 | * don't scan past the first function. |
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381 | */ |
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382 | if (!dev->pci_dev.multifunction) |
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383 | { |
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384 | if (func > 0) { |
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385 | dev->pci_dev.multifunction = 1; |
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386 | } |
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387 | else { |
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388 | break; |
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389 | } |
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390 | } |
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391 | } |
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392 | else { |
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393 | if (func == 0) |
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394 | break; |
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395 | } |
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396 | }; |
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397 | |||
398 | return nr; |
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399 | }; |
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400 | |||
401 | #define PCI_FIND_CAP_TTL 48 |
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402 | |||
403 | static int __pci_find_next_cap_ttl(unsigned int bus, unsigned int devfn, |
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404 | u8 pos, int cap, int *ttl) |
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405 | { |
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406 | u8 id; |
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407 | |||
408 | while ((*ttl)--) { |
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409 | pos = PciRead8(bus, devfn, pos); |
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410 | if (pos < 0x40) |
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411 | break; |
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412 | pos &= ~3; |
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413 | id = PciRead8(bus, devfn, pos + PCI_CAP_LIST_ID); |
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414 | if (id == 0xff) |
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415 | break; |
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416 | if (id == cap) |
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417 | return pos; |
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418 | pos += PCI_CAP_LIST_NEXT; |
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419 | } |
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420 | return 0; |
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421 | } |
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422 | |||
423 | static int __pci_find_next_cap(unsigned int bus, unsigned int devfn, |
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424 | u8 pos, int cap) |
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425 | { |
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426 | int ttl = PCI_FIND_CAP_TTL; |
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427 | |||
428 | return __pci_find_next_cap_ttl(bus, devfn, pos, cap, &ttl); |
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429 | } |
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430 | |||
431 | static int __pci_bus_find_cap_start(unsigned int bus, |
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432 | unsigned int devfn, u8 hdr_type) |
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433 | { |
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434 | u16 status; |
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435 | |||
436 | status = PciRead16(bus, devfn, PCI_STATUS); |
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437 | if (!(status & PCI_STATUS_CAP_LIST)) |
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438 | return 0; |
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439 | |||
440 | switch (hdr_type) { |
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441 | case PCI_HEADER_TYPE_NORMAL: |
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442 | case PCI_HEADER_TYPE_BRIDGE: |
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443 | return PCI_CAPABILITY_LIST; |
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444 | case PCI_HEADER_TYPE_CARDBUS: |
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445 | return PCI_CB_CAPABILITY_LIST; |
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446 | default: |
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447 | return 0; |
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448 | } |
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449 | |||
450 | return 0; |
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451 | } |
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452 | |||
453 | |||
454 | int pci_find_capability(struct pci_dev *dev, int cap) |
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455 | { |
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456 | int pos; |
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457 | |||
458 | pos = __pci_bus_find_cap_start(dev->busnr, dev->devfn, dev->hdr_type); |
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459 | if (pos) |
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460 | pos = __pci_find_next_cap(dev->busnr, dev->devfn, pos, cap); |
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461 | |||
462 | return pos; |
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463 | } |
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464 | |||
465 | |||
9827 | turbocat | 466 | int enum_pci_devices(void) |
9079 | turbocat | 467 | { |
468 | pci_dev_t *dev; |
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469 | u32 last_bus; |
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470 | u32 bus = 0 , devfn = 0; |
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471 | |||
472 | last_bus = PciApi(1); |
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473 | |||
474 | if( unlikely(last_bus == -1)) |
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475 | return -1; |
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476 | |||
477 | for(;bus <= last_bus; bus++) |
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478 | { |
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479 | for (devfn = 0; devfn < 0x100; devfn += 8){ |
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480 | _pci_scan_slot(bus, devfn); |
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481 | } |
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482 | } |
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483 | dev = (pci_dev_t*)devices.next; |
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484 | |||
485 | while(&dev->link != &devices) |
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486 | { |
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487 | /*printk("PCI device %x:%x bus:%x devfn:%x\n", |
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488 | dev->pci_dev.vendor, |
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489 | dev->pci_dev.device, |
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490 | dev->pci_dev.busnr, |
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491 | dev->pci_dev.devfn);*/ |
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492 | dev = (pci_dev_t*)dev->link.next; |
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493 | } |
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494 | return 0; |
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495 | } |
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496 | |||
9827 | turbocat | 497 | void free_pci_devices(void) |
498 | { |
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499 | pci_dev_t *dev = (pci_dev_t*)devices.next; |
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500 | while(&dev->link != &devices) { |
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501 | pci_dev_t *temp = dev; |
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502 | dev = (pci_dev_t*)dev->link.next; |
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503 | KernelFree(temp); |
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504 | } |
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505 | } |
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506 | |||
9079 | turbocat | 507 | const struct pci_device_id* find_pci_device(pci_dev_t* pdev, const struct pci_device_id *idlist) |
508 | { |
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509 | pci_dev_t *dev; |
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510 | const struct pci_device_id *ent; |
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511 | |||
512 | for(dev = (pci_dev_t*)devices.next; |
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513 | &dev->link != &devices; |
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514 | dev = (pci_dev_t*)dev->link.next) |
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515 | { |
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516 | if( dev->pci_dev.vendor != idlist->vendor ) |
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517 | continue; |
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518 | |||
519 | for(ent = idlist; ent->vendor != 0; ent++) |
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520 | { |
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521 | if(unlikely(ent->device == dev->pci_dev.device)) |
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522 | { |
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523 | pdev->pci_dev = dev->pci_dev; |
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524 | return ent; |
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525 | } |
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526 | }; |
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527 | } |
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528 | |||
529 | return NULL; |
||
530 | }; |
||
531 | |||
532 | struct pci_dev * |
||
533 | pci_get_device(unsigned int vendor, unsigned int device, struct pci_dev *from) |
||
534 | { |
||
535 | pci_dev_t *dev; |
||
536 | |||
537 | dev = (pci_dev_t*)devices.next; |
||
538 | |||
539 | if(from != NULL) |
||
540 | { |
||
541 | for(; &dev->link != &devices; |
||
542 | dev = (pci_dev_t*)dev->link.next) |
||
543 | { |
||
544 | if( &dev->pci_dev == from) |
||
545 | { |
||
546 | dev = (pci_dev_t*)dev->link.next; |
||
547 | break; |
||
548 | }; |
||
549 | } |
||
550 | }; |
||
551 | |||
552 | for(; &dev->link != &devices; |
||
553 | dev = (pci_dev_t*)dev->link.next) |
||
554 | { |
||
555 | if((dev->pci_dev.vendor != vendor) && (vendor != PCI_ANY_ID)) |
||
556 | continue; |
||
557 | |||
558 | if((dev->pci_dev.device == device || device == PCI_ANY_ID)) |
||
559 | { |
||
560 | return &dev->pci_dev; |
||
561 | } |
||
562 | } |
||
563 | return NULL; |
||
564 | }; |
||
565 | |||
566 | |||
567 | struct pci_dev * _pci_get_bus_and_slot(unsigned int bus, unsigned int devfn) |
||
568 | { |
||
569 | pci_dev_t *dev; |
||
570 | |||
571 | for(dev = (pci_dev_t*)devices.next; |
||
572 | &dev->link != &devices; |
||
573 | dev = (pci_dev_t*)dev->link.next) |
||
574 | { |
||
575 | if ( dev->pci_dev.busnr == bus && dev->pci_dev.devfn == devfn) |
||
576 | return &dev->pci_dev; |
||
577 | } |
||
578 | return NULL; |
||
579 | } |
||
580 | |||
581 | struct pci_dev *pci_get_class(unsigned int class, struct pci_dev *from) |
||
582 | { |
||
583 | pci_dev_t *dev; |
||
584 | |||
585 | dev = (pci_dev_t*)devices.next; |
||
586 | |||
587 | if(from != NULL) |
||
588 | { |
||
589 | for(; &dev->link != &devices; |
||
590 | dev = (pci_dev_t*)dev->link.next) |
||
591 | { |
||
592 | if( &dev->pci_dev == from) |
||
593 | { |
||
594 | dev = (pci_dev_t*)dev->link.next; |
||
595 | break; |
||
596 | }; |
||
597 | } |
||
598 | }; |
||
599 | |||
600 | for(; &dev->link != &devices; |
||
601 | dev = (pci_dev_t*)dev->link.next) |
||
602 | { |
||
603 | if( dev->pci_dev.class == class) |
||
604 | { |
||
605 | return &dev->pci_dev; |
||
606 | } |
||
607 | } |
||
608 | |||
609 | return NULL; |
||
610 | } |
||
611 | |||
9827 | turbocat | 612 | |
9079 | turbocat | 613 | int pci_bus_read_config_byte (struct pci_bus *bus, u32 devfn, int pos, u8 *value) |
614 | { |
||
615 | // raw_spin_lock_irqsave(&pci_lock, flags); |
||
616 | *value = PciRead8(bus->number, devfn, pos); |
||
617 | // raw_spin_unlock_irqrestore(&pci_lock, flags); |
||
618 | return 0; |
||
619 | } |
||
620 | |||
621 | int pci_bus_read_config_word (struct pci_bus *bus, u32 devfn, int pos, u16 *value) |
||
622 | { |
||
623 | if ( pos & 1) |
||
624 | return PCIBIOS_BAD_REGISTER_NUMBER; |
||
625 | // raw_spin_lock_irqsave(&pci_lock, flags); |
||
626 | *value = PciRead16(bus->number, devfn, pos); |
||
627 | // raw_spin_unlock_irqrestore(&pci_lock, flags); |
||
628 | return 0; |
||
629 | } |
||
630 | |||
631 | |||
632 | int pci_bus_read_config_dword (struct pci_bus *bus, u32 devfn, int pos, u32 *value) |
||
633 | { |
||
634 | if ( pos & 3) |
||
635 | return PCIBIOS_BAD_REGISTER_NUMBER; |
||
636 | *value = PciRead32(bus->number, devfn, pos); |
||
637 | return 0; |
||
638 | } |
||
639 | |||
640 | int pci_bus_write_config_dword(struct pci_bus *bus, unsigned int devfn, int where, u32 val) |
||
641 | { |
||
642 | if ( where & 3) |
||
643 | return PCIBIOS_BAD_REGISTER_NUMBER; |
||
644 | PciWrite32(bus->number, devfn,where, val); |
||
645 | return 0; |
||
646 | }>=>>>><>><>><>>3)><3)>2)><2)>4)><4)> |