WebSVN – Kolibri OS – Blame – /drivers/sensors/pci.c

Rev	Author	Line No.	Line
9079	turbocat	1	#include
		2
		3	#include
		4	#include
		5	#include
		6	#include
		7	#include
		8	#include
		9	#include
		10
		11	extern int pci_scan_filter(u32 id, u32 busnr, u32 devfn);
		12
		13	LIST_HEAD(devices);
		14
		15	/* PCI control bits. Shares IORESOURCE_BITS with above PCI ROM. */
		16	#define IORESOURCE_PCI_FIXED (1<<4) /* Do not move resource */
		17
		18	#define LEGACY_IO_RESOURCE (IORESOURCE_IO \| IORESOURCE_PCI_FIXED)
		19
		20	#define IORESOURCE_ROM_COPY (1<<2) /* ROM is alloc'd copy, resource field overlaid */
		21	#define IORESOURCE_ROM_BIOS_COPY (1<<3) /* ROM is BIOS copy, resource field overlaid */
		22
		23	/*
		24	* Translate the low bits of the PCI base
		25	* to the resource type
		26	*/
		27	/*
		28	//int pci_scan_filter(u32 id, u32 busnr, u32 devfn)
		29	{
		30	u16 vendor, device;
		31	u32 class;
		32	int ret = 0;
		33
		34	vendor = id & 0xffff;
		35	device = (id >> 16) & 0xffff;
		36
		37	if(vendor == 0x15AD )
		38	{
		39	class = PciRead32(busnr, devfn, PCI_CLASS_REVISION);
		40	class >>= 16;
		41
		42	if( class == PCI_CLASS_DISPLAY_VGA )
		43	ret = 1;
		44	}
		45	return ret;
		46	};*/
		47
		48
		49	static inline unsigned int pci_calc_resource_flags(unsigned int flags)
		50	{
		51	if (flags & PCI_BASE_ADDRESS_SPACE_IO)
		52	return IORESOURCE_IO;
		53
		54	if (flags & PCI_BASE_ADDRESS_MEM_PREFETCH)
		55	return IORESOURCE_MEM \| IORESOURCE_PREFETCH;
		56
		57	return IORESOURCE_MEM;
		58	}
		59
		60	static u32 pci_size(u32 base, u32 maxbase, u32 mask)
		61	{
		62	u32 size = mask & maxbase; /* Find the significant bits */
		63
		64	if (!size)
		65	return 0;
		66
		67	/* Get the lowest of them to find the decode size, and
		68	from that the extent. */
		69	size = (size & ~(size-1)) - 1;
		70
		71	/* base == maxbase can be valid only if the BAR has
		72	already been programmed with all 1s. */
		73	if (base == maxbase && ((base \| size) & mask) != mask)
		74	return 0;
		75
		76	return size;
		77	}
		78
		79	static u64 pci_size64(u64 base, u64 maxbase, u64 mask)
		80	{
		81	u64 size = mask & maxbase; /* Find the significant bits */
		82
		83	if (!size)
		84	return 0;
		85
		86	/* Get the lowest of them to find the decode size, and
		87	from that the extent. */
		88	size = (size & ~(size-1)) - 1;
		89
		90	/* base == maxbase can be valid only if the BAR has
		91	already been programmed with all 1s. */
		92	if (base == maxbase && ((base \| size) & mask) != mask)
		93	return 0;
		94
		95	return size;
		96	}
		97
		98	static inline int is_64bit_memory(u32 mask)
		99	{
		100	if ((mask & (PCI_BASE_ADDRESS_SPACE\|PCI_BASE_ADDRESS_MEM_TYPE_MASK)) ==
		101	(PCI_BASE_ADDRESS_SPACE_MEMORY\|PCI_BASE_ADDRESS_MEM_TYPE_64))
		102	return 1;
		103	return 0;
		104	}
		105
		106	static void pci_read_bases(struct pci_dev *dev, unsigned int howmany, int rom)
		107	{
		108	u32 pos, reg, next;
		109	u32 l, sz;
		110	struct resource *res;
		111
		112	for(pos=0; pos < howmany; pos = next)
		113	{
		114	u64 l64;
		115	u64 sz64;
		116	u32 raw_sz;
		117
		118	next = pos + 1;
		119
		120	res = &dev->resource[pos];
		121
		122	reg = PCI_BASE_ADDRESS_0 + (pos << 2);
		123	l = PciRead32(dev->busnr, dev->devfn, reg);
		124	PciWrite32(dev->busnr, dev->devfn, reg, ~0);
		125	sz = PciRead32(dev->busnr, dev->devfn, reg);
		126	PciWrite32(dev->busnr, dev->devfn, reg, l);
		127
		128	if (!sz \|\| sz == 0xffffffff)
		129	continue;
		130
		131	if (l == 0xffffffff)
		132	l = 0;
		133
		134	raw_sz = sz;
		135	if ((l & PCI_BASE_ADDRESS_SPACE) ==
		136	PCI_BASE_ADDRESS_SPACE_MEMORY)
		137	{
		138	sz = pci_size(l, sz, (u32)PCI_BASE_ADDRESS_MEM_MASK);
		139	/*
		140	* For 64bit prefetchable memory sz could be 0, if the
		141	* real size is bigger than 4G, so we need to check
		142	* szhi for that.
		143	*/
		144	if (!is_64bit_memory(l) && !sz)
		145	continue;
		146	res->start = l & PCI_BASE_ADDRESS_MEM_MASK;
		147	res->flags \|= l & ~PCI_BASE_ADDRESS_MEM_MASK;
		148	}
		149	else {
		150	sz = pci_size(l, sz, PCI_BASE_ADDRESS_IO_MASK & 0xffff);
		151	if (!sz)
		152	continue;
		153	res->start = l & PCI_BASE_ADDRESS_IO_MASK;
		154	res->flags \|= l & ~PCI_BASE_ADDRESS_IO_MASK;
		155	}
		156	res->end = res->start + (unsigned long) sz;
		157	res->flags \|= pci_calc_resource_flags(l);
		158	if (is_64bit_memory(l))
		159	{
		160	u32 szhi, lhi;
		161
		162	lhi = PciRead32(dev->busnr, dev->devfn, reg+4);
		163	PciWrite32(dev->busnr, dev->devfn, reg+4, ~0);
		164	szhi = PciRead32(dev->busnr, dev->devfn, reg+4);
		165	PciWrite32(dev->busnr, dev->devfn, reg+4, lhi);
		166	sz64 = ((u64)szhi << 32) \| raw_sz;
		167	l64 = ((u64)lhi << 32) \| l;
		168	sz64 = pci_size64(l64, sz64, PCI_BASE_ADDRESS_MEM_MASK);
		169	next++;
		170
		171	#if BITS_PER_LONG == 64
		172	if (!sz64) {
		173	res->start = 0;
		174	res->end = 0;
		175	res->flags = 0;
		176	continue;
		177	}
		178	res->start = l64 & PCI_BASE_ADDRESS_MEM_MASK;
		179	res->end = res->start + sz64;
		180	#else
		181	if (sz64 > 0x100000000ULL) {
		182	printk(KERN_ERR "PCI: Unable to handle 64-bit "
		183	"BAR for device %s\n", pci_name(dev));
		184	res->start = 0;
		185	res->flags = 0;
		186	}
		187	else if (lhi)
		188	{
		189	/* 64-bit wide address, treat as disabled */
		190	PciWrite32(dev->busnr, dev->devfn, reg,
		191	l & ~(u32)PCI_BASE_ADDRESS_MEM_MASK);
		192	PciWrite32(dev->busnr, dev->devfn, reg+4, 0);
		193	res->start = 0;
		194	res->end = sz;
		195	}
		196	#endif
		197	}
		198	}
		199
		200	if ( rom )
		201	{
		202	dev->rom_base_reg = rom;
		203	res = &dev->resource[PCI_ROM_RESOURCE];
		204
		205	l = PciRead32(dev->busnr, dev->devfn, rom);
		206	PciWrite32(dev->busnr, dev->devfn, rom, ~PCI_ROM_ADDRESS_ENABLE);
		207	sz = PciRead32(dev->busnr, dev->devfn, rom);
		208	PciWrite32(dev->busnr, dev->devfn, rom, l);
		209
		210	if (l == 0xffffffff)
		211	l = 0;
		212
		213	if (sz && sz != 0xffffffff)
		214	{
		215	sz = pci_size(l, sz, (u32)PCI_ROM_ADDRESS_MASK);
		216
		217	if (sz)
		218	{
		219	res->flags = (l & IORESOURCE_ROM_ENABLE) \|
		220	IORESOURCE_MEM \| IORESOURCE_PREFETCH \|
		221	IORESOURCE_READONLY \| IORESOURCE_CACHEABLE;
		222	res->start = l & PCI_ROM_ADDRESS_MASK;
		223	res->end = res->start + (unsigned long) sz;
		224	}
		225	}
		226	}
		227	}
		228
		229	static void pci_read_irq(struct pci_dev *dev)
		230	{
		231	u8 irq;
		232
		233	irq = PciRead8(dev->busnr, dev->devfn, PCI_INTERRUPT_PIN);
		234	dev->pin = irq;
		235	if (irq)
		236	irq = PciRead8(dev->busnr, dev->devfn, PCI_INTERRUPT_LINE);
		237	dev->irq = irq;
		238	};
		239
		240
		241	int pci_setup_device(struct pci_dev *dev)
		242	{
		243	u32 class;
		244
		245	class = PciRead32(dev->busnr, dev->devfn, PCI_CLASS_REVISION);
		246	dev->revision = class & 0xff;
		247	class >>= 8; /* upper 3 bytes */
		248	dev->class = class;
		249
		250	/* "Unknown power state" */
		251	// dev->current_state = PCI_UNKNOWN;
		252
		253	/* Early fixups, before probing the BARs */
		254	// pci_fixup_device(pci_fixup_early, dev);
		255	class = dev->class >> 8;
		256
		257	switch (dev->hdr_type)
		258	{
		259	case PCI_HEADER_TYPE_NORMAL: /* standard header */
		260	if (class == PCI_CLASS_BRIDGE_PCI)
		261	goto bad;
		262	pci_read_irq(dev);
		263	pci_read_bases(dev, 6, PCI_ROM_ADDRESS);
		264	dev->subsystem_vendor = PciRead16(dev->busnr, dev->devfn,PCI_SUBSYSTEM_VENDOR_ID);
		265	dev->subsystem_device = PciRead16(dev->busnr, dev->devfn, PCI_SUBSYSTEM_ID);
		266
		267	/*
		268	* Do the ugly legacy mode stuff here rather than broken chip
		269	* quirk code. Legacy mode ATA controllers have fixed
		270	* addresses. These are not always echoed in BAR0-3, and
		271	* BAR0-3 in a few cases contain junk!
		272	*/
		273	if (class == PCI_CLASS_STORAGE_IDE)
		274	{
		275	u8 progif;
		276
		277	progif = PciRead8(dev->busnr, dev->devfn,PCI_CLASS_PROG);
		278	if ((progif & 1) == 0)
		279	{
		280	dev->resource[0].start = 0x1F0;
		281	dev->resource[0].end = 0x1F7;
		282	dev->resource[0].flags = LEGACY_IO_RESOURCE;
		283	dev->resource[1].start = 0x3F6;
		284	dev->resource[1].end = 0x3F6;
		285	dev->resource[1].flags = LEGACY_IO_RESOURCE;
		286	}
		287	if ((progif & 4) == 0)
		288	{
		289	dev->resource[2].start = 0x170;
		290	dev->resource[2].end = 0x177;
		291	dev->resource[2].flags = LEGACY_IO_RESOURCE;
		292	dev->resource[3].start = 0x376;
		293	dev->resource[3].end = 0x376;
		294	dev->resource[3].flags = LEGACY_IO_RESOURCE;
		295	};
		296	}
		297	break;
		298
		299	case PCI_HEADER_TYPE_BRIDGE: /* bridge header */
		300	if (class != PCI_CLASS_BRIDGE_PCI)
		301	goto bad;
		302	/* The PCI-to-PCI bridge spec requires that subtractive
		303	decoding (i.e. transparent) bridge must have programming
		304	interface code of 0x01. */
		305	pci_read_irq(dev);
		306	dev->transparent = ((dev->class & 0xff) == 1);
		307	pci_read_bases(dev, 2, PCI_ROM_ADDRESS1);
		308	break;
		309
		310	case PCI_HEADER_TYPE_CARDBUS: /* CardBus bridge header */
		311	if (class != PCI_CLASS_BRIDGE_CARDBUS)
		312	goto bad;
		313	pci_read_irq(dev);
		314	pci_read_bases(dev, 1, 0);
		315	dev->subsystem_vendor = PciRead16(dev->busnr,
		316	dev->devfn,
		317	PCI_CB_SUBSYSTEM_VENDOR_ID);
		318
		319	dev->subsystem_device = PciRead16(dev->busnr,
		320	dev->devfn,
		321	PCI_CB_SUBSYSTEM_ID);
		322	break;
		323
		324	default: /* unknown header */
		325	printk(KERN_ERR "PCI: device %s has unknown header type %02x, ignoring.\n",
		326	pci_name(dev), dev->hdr_type);
		327	return -1;
		328
		329	bad:
		330	printk(KERN_ERR "PCI: %s: class %x doesn't match header type %02x. Ignoring class.\n",
		331	pci_name(dev), class, dev->hdr_type);
		332	dev->class = PCI_CLASS_NOT_DEFINED;
		333	}
		334
		335	/* We found a fine healthy device, go go go... */
		336
		337	return 0;
		338	};
		339
		340	static pci_dev_t* pci_scan_device(u32 busnr, int devfn)
		341	{
		342	pci_dev_t *dev;
		343
		344	u32 id;
		345	u8 hdr;
		346
		347	int timeout = 10;
		348
		349	id = PciRead32(busnr, devfn, PCI_VENDOR_ID);
		350	/* some broken boards return 0 or ~0 if a slot is empty: */
		351	if (id == 0xffffffff \|\| id == 0x00000000 \|\|
		352	id == 0x0000ffff \|\| id == 0xffff0000)
		353	return NULL;
		354
		355	while (id == 0xffff0001)
		356	{
		357
		358	delay(timeout/10);
		359	timeout *= 2;
		360
		361	id = PciRead32(busnr, devfn, PCI_VENDOR_ID);
		362
		363	/* Card hasn't responded in 60 seconds? Must be stuck. */
		364	if (timeout > 60 * 100)
		365	{
		366	printk(KERN_WARNING "Device %04x:%02x:%02x.%d not "
		367	"responding\n", busnr,PCI_SLOT(devfn),PCI_FUNC(devfn));
		368	return NULL;
		369	}
		370	};
		371
		372	/* if( pci_scan_filter(id, busnr, devfn) == 0)
		373	return NULL;*/
		374
		375	hdr = PciRead8(busnr, devfn, PCI_HEADER_TYPE);
		376
		377	dev = (pci_dev_t*)kzalloc(sizeof(pci_dev_t), 0);
		378	if(unlikely(dev == NULL))
		379	return NULL;
		380
		381	INIT_LIST_HEAD(&dev->link);
		382
		383
		384	dev->pci_dev.busnr = busnr;
		385	dev->pci_dev.devfn = devfn;
		386	dev->pci_dev.hdr_type = hdr & 0x7f;
		387	dev->pci_dev.multifunction = !!(hdr & 0x80);
		388	dev->pci_dev.vendor = id & 0xffff;
		389	dev->pci_dev.device = (id >> 16) & 0xffff;
		390
		391	pci_setup_device(&dev->pci_dev);
		392
		393	return dev;
		394
		395	};
		396
		397
		398
		399	int _pci_scan_slot(u32 bus, int devfn)
		400	{
		401	int func, nr = 0;
		402
		403	for (func = 0; func < 8; func++, devfn++)
		404	{
		405	pci_dev_t *dev;
		406
		407	dev = pci_scan_device(bus, devfn);
		408	if( dev )
		409	{
		410	list_add(&dev->link, &devices);
		411	nr++;
		412
		413	/*
		414	* If this is a single function device,
		415	* don't scan past the first function.
		416	*/
		417	if (!dev->pci_dev.multifunction)
		418	{
		419	if (func > 0) {
		420	dev->pci_dev.multifunction = 1;
		421	}
		422	else {
		423	break;
		424	}
		425	}
		426	}
		427	else {
		428	if (func == 0)
		429	break;
		430	}
		431	};
		432
		433	return nr;
		434	};
		435
		436	#define PCI_FIND_CAP_TTL 48
		437
		438	static int __pci_find_next_cap_ttl(unsigned int bus, unsigned int devfn,
		439	u8 pos, int cap, int *ttl)
		440	{
		441	u8 id;
		442
		443	while ((*ttl)--) {
		444	pos = PciRead8(bus, devfn, pos);
		445	if (pos < 0x40)
		446	break;
		447	pos &= ~3;
		448	id = PciRead8(bus, devfn, pos + PCI_CAP_LIST_ID);
		449	if (id == 0xff)
		450	break;
		451	if (id == cap)
		452	return pos;
		453	pos += PCI_CAP_LIST_NEXT;
		454	}
		455	return 0;
		456	}
		457
		458	static int __pci_find_next_cap(unsigned int bus, unsigned int devfn,
		459	u8 pos, int cap)
		460	{
		461	int ttl = PCI_FIND_CAP_TTL;
		462
		463	return __pci_find_next_cap_ttl(bus, devfn, pos, cap, &ttl);
		464	}
		465
		466	static int __pci_bus_find_cap_start(unsigned int bus,
		467	unsigned int devfn, u8 hdr_type)
		468	{
		469	u16 status;
		470
		471	status = PciRead16(bus, devfn, PCI_STATUS);
		472	if (!(status & PCI_STATUS_CAP_LIST))
		473	return 0;
		474
		475	switch (hdr_type) {
		476	case PCI_HEADER_TYPE_NORMAL:
		477	case PCI_HEADER_TYPE_BRIDGE:
		478	return PCI_CAPABILITY_LIST;
		479	case PCI_HEADER_TYPE_CARDBUS:
		480	return PCI_CB_CAPABILITY_LIST;
		481	default:
		482	return 0;
		483	}
		484
		485	return 0;
		486	}
		487
		488
		489	int pci_find_capability(struct pci_dev *dev, int cap)
		490	{
		491	int pos;
		492
		493	pos = __pci_bus_find_cap_start(dev->busnr, dev->devfn, dev->hdr_type);
		494	if (pos)
		495	pos = __pci_find_next_cap(dev->busnr, dev->devfn, pos, cap);
		496
		497	return pos;
		498	}
		499
		500
		501
		502
		503	int enum_pci_devices()
		504	{
		505	pci_dev_t *dev;
		506	u32 last_bus;
		507	u32 bus = 0 , devfn = 0;
		508
		509	last_bus = PciApi(1);
		510
		511
		512	if( unlikely(last_bus == -1))
		513	return -1;
		514
		515	for(;bus <= last_bus; bus++)
		516	{
		517	for (devfn = 0; devfn < 0x100; devfn += 8){
		518	_pci_scan_slot(bus, devfn);
		519	}
		520	}
		521	dev = (pci_dev_t*)devices.next;
		522
		523	while(&dev->link != &devices)
		524	{
		525	/*printk("PCI device %x:%x bus:%x devfn:%x\n",
		526	dev->pci_dev.vendor,
		527	dev->pci_dev.device,
		528	dev->pci_dev.busnr,
		529	dev->pci_dev.devfn);*/
		530	dev = (pci_dev_t*)dev->link.next;
		531	}
		532	return 0;
		533	}
		534
		535	const struct pci_device_id* find_pci_device(pci_dev_t* pdev, const struct pci_device_id *idlist)
		536	{
		537	pci_dev_t *dev;
		538	const struct pci_device_id *ent;
		539
		540	for(dev = (pci_dev_t*)devices.next;
		541	&dev->link != &devices;
		542	dev = (pci_dev_t*)dev->link.next)
		543	{
		544	if( dev->pci_dev.vendor != idlist->vendor )
		545	continue;
		546
		547	for(ent = idlist; ent->vendor != 0; ent++)
		548	{
		549	if(unlikely(ent->device == dev->pci_dev.device))
		550	{
		551	pdev->pci_dev = dev->pci_dev;
		552	return ent;
		553	}
		554	};
		555	}
		556
		557	return NULL;
		558	};
		559
		560	struct pci_dev *
		561	pci_get_device(unsigned int vendor, unsigned int device, struct pci_dev *from)
		562	{
		563	pci_dev_t *dev;
		564
		565	dev = (pci_dev_t*)devices.next;
		566
		567	if(from != NULL)
		568	{
		569	for(; &dev->link != &devices;
		570	dev = (pci_dev_t*)dev->link.next)
		571	{
		572	if( &dev->pci_dev == from)
		573	{
		574	dev = (pci_dev_t*)dev->link.next;
		575	break;
		576	};
		577	}
		578	};
		579
		580	for(; &dev->link != &devices;
		581	dev = (pci_dev_t*)dev->link.next)
		582	{
		583	if((dev->pci_dev.vendor != vendor) && (vendor != PCI_ANY_ID))
		584	continue;
		585
		586	if((dev->pci_dev.device == device \|\| device == PCI_ANY_ID))
		587	{
		588	return &dev->pci_dev;
		589	}
		590	}
		591	return NULL;
		592	};
		593
		594
		595	struct pci_dev * _pci_get_bus_and_slot(unsigned int bus, unsigned int devfn)
		596	{
		597	pci_dev_t *dev;
		598
		599	for(dev = (pci_dev_t*)devices.next;
		600	&dev->link != &devices;
		601	dev = (pci_dev_t*)dev->link.next)
		602	{
		603	if ( dev->pci_dev.busnr == bus && dev->pci_dev.devfn == devfn)
		604	return &dev->pci_dev;
		605	}
		606	return NULL;
		607	}
		608
		609	struct pci_dev pci_get_class(unsigned int class, struct pci_dev from)
		610	{
		611	pci_dev_t *dev;
		612
		613	dev = (pci_dev_t*)devices.next;
		614
		615	if(from != NULL)
		616	{
		617	for(; &dev->link != &devices;
		618	dev = (pci_dev_t*)dev->link.next)
		619	{
		620	if( &dev->pci_dev == from)
		621	{
		622	dev = (pci_dev_t*)dev->link.next;
		623	break;
		624	};
		625	}
		626	};
		627
		628	for(; &dev->link != &devices;
		629	dev = (pci_dev_t*)dev->link.next)
		630	{
		631	if( dev->pci_dev.class == class)
		632	{
		633	return &dev->pci_dev;
		634	}
		635	}
		636
		637	return NULL;
		638	}
		639
		640	int pci_bus_read_config_byte (struct pci_bus bus, u32 devfn, int pos, u8 value)
		641	{
		642	// raw_spin_lock_irqsave(&pci_lock, flags);
		643	*value = PciRead8(bus->number, devfn, pos);
		644	// raw_spin_unlock_irqrestore(&pci_lock, flags);
		645	return 0;
		646	}
		647
		648	int pci_bus_read_config_word (struct pci_bus bus, u32 devfn, int pos, u16 value)
		649	{
		650	if ( pos & 1)
		651	return PCIBIOS_BAD_REGISTER_NUMBER;
		652	// raw_spin_lock_irqsave(&pci_lock, flags);
		653	*value = PciRead16(bus->number, devfn, pos);
		654	// raw_spin_unlock_irqrestore(&pci_lock, flags);
		655	return 0;
		656	}
		657
		658
		659	int pci_bus_read_config_dword (struct pci_bus bus, u32 devfn, int pos, u32 value)
		660	{
		661	if ( pos & 3)
		662	return PCIBIOS_BAD_REGISTER_NUMBER;
		663
		664	// raw_spin_lock_irqsave(&pci_lock, flags);
		665	*value = PciRead32(bus->number, devfn, pos);
		666	// raw_spin_unlock_irqrestore(&pci_lock, flags);
		667	return 0;
		668	}
		669
		670	int pci_bus_write_config_dword(struct pci_bus *bus, unsigned int devfn, int where, u32 val)
		671	{
		672	if ( where & 3)
		673	return PCIBIOS_BAD_REGISTER_NUMBER;
		674
		675	// raw_spin_lock_irqsave(&pci_lock, flags);
		676	PciWrite32(bus->number, devfn,where, val);
		677	// raw_spin_unlock_irqrestore(&pci_lock, flags);
		678	return 0;
		679	}
		680

Subversion Repositories Kolibri OS

(root)/drivers/sensors/pci.c @ 9827 – Rev 9079