Rev 9100 | Go to most recent revision | Details | Compare with Previous | Last modification | View Log | RSS feed
| Rev | Author | Line No. | Line |
|---|---|---|---|
| 9079 | turbocat | 1 | // SPDX-License-Identifier: GPL-2.0-or-later |
| 2 | /* |
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| 3 | * k10temp.c - AMD Family 10h/11h/12h/14h/15h/16h/17h |
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| 4 | * processor hardware monitoring |
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| 5 | * |
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| 6 | * Copyright (c) 2009 Clemens Ladisch |
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| 7 | * Copyright (c) 2020 Guenter Roeck |
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| 8 | * |
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| 9 | * Implementation notes: |
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| 10 | * - CCD register address information as well as the calculation to |
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| 11 | * convert raw register values is from https://github.com/ocerman/zenpower. |
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| 12 | * The information is not confirmed from chip datasheets, but experiments |
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| 13 | * suggest that it provides reasonable temperature values. |
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| 14 | */ |
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| 15 | |||
| 9100 | turbocat | 16 | /* Ported for Kolibri OS by turbocat (Maxim Logaeav). 2021 */ |
| 17 | /* Thanks: dunkaist, punk_joker, doczom. */ |
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| 18 | |||
| 9079 | turbocat | 19 | #include |
| 20 | #include |
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| 21 | #include |
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| 22 | #include |
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| 23 | #include |
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| 24 | #include |
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| 25 | #include |
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| 26 | #include |
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| 27 | #include |
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| 28 | #include |
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| 29 | |||
| 30 | struct cpuinfo_x86 boot_cpu_data; |
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| 9144 | turbocat | 31 | extern void init_amd_nbs(void); |
| 9079 | turbocat | 32 | |
| 9144 | turbocat | 33 | #define KERNEL_SPACE 0x80000000 |
| 34 | |||
| 9079 | turbocat | 35 | /* CPUID function 0x80000001, ebx */ |
| 36 | #define CPUID_PKGTYPE_MASK GENMASK(31, 28) |
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| 37 | #define CPUID_PKGTYPE_F 0x00000000 |
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| 38 | #define CPUID_PKGTYPE_AM2R2_AM3 0x10000000 |
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| 39 | |||
| 40 | /* DRAM controller (PCI function 2) */ |
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| 41 | #define REG_DCT0_CONFIG_HIGH 0x094 |
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| 42 | #define DDR3_MODE BIT(8) |
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| 43 | |||
| 44 | /* miscellaneous (PCI function 3) */ |
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| 45 | #define REG_HARDWARE_THERMAL_CONTROL 0x64 |
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| 46 | #define HTC_ENABLE BIT(0) |
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| 47 | |||
| 48 | #define REG_REPORTED_TEMPERATURE 0xa4 |
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| 49 | |||
| 50 | #define REG_NORTHBRIDGE_CAPABILITIES 0xe8 |
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| 51 | #define NB_CAP_HTC BIT(10) |
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| 52 | |||
| 53 | /* |
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| 54 | * For F15h M60h and M70h, REG_HARDWARE_THERMAL_CONTROL |
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| 55 | * and REG_REPORTED_TEMPERATURE have been moved to |
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| 56 | * D0F0xBC_xD820_0C64 [Hardware Temperature Control] |
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| 57 | * D0F0xBC_xD820_0CA4 [Reported Temperature Control] |
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| 58 | */ |
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| 59 | #define F15H_M60H_HARDWARE_TEMP_CTRL_OFFSET 0xd8200c64 |
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| 60 | #define F15H_M60H_REPORTED_TEMP_CTRL_OFFSET 0xd8200ca4 |
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| 61 | |||
| 62 | /* Common for Zen CPU families (Family 17h and 18h) */ |
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| 63 | #define ZEN_REPORTED_TEMP_CTRL_OFFSET 0x00059800 |
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| 64 | |||
| 65 | #define ZEN_CCD_TEMP(x) (0x00059954 + ((x) * 4)) |
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| 66 | #define ZEN_CCD_TEMP_VALID BIT(11) |
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| 67 | #define ZEN_CCD_TEMP_MASK GENMASK(10, 0) |
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| 68 | |||
| 69 | #define ZEN_CUR_TEMP_SHIFT 21 |
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| 70 | #define ZEN_CUR_TEMP_RANGE_SEL_MASK BIT(19) |
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| 71 | |||
| 72 | #define ZEN_SVI_BASE 0x0005A000 |
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| 73 | |||
| 74 | /* F17h thermal registers through SMN */ |
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| 75 | #define F17H_M01H_SVI_TEL_PLANE0 (ZEN_SVI_BASE + 0xc) |
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| 76 | #define F17H_M01H_SVI_TEL_PLANE1 (ZEN_SVI_BASE + 0x10) |
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| 77 | #define F17H_M31H_SVI_TEL_PLANE0 (ZEN_SVI_BASE + 0x14) |
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| 78 | #define F17H_M31H_SVI_TEL_PLANE1 (ZEN_SVI_BASE + 0x10) |
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| 79 | |||
| 80 | #define F17H_M01H_CFACTOR_ICORE 1000000 /* 1A / LSB */ |
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| 81 | #define F17H_M01H_CFACTOR_ISOC 250000 /* 0.25A / LSB */ |
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| 82 | #define F17H_M31H_CFACTOR_ICORE 1000000 /* 1A / LSB */ |
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| 83 | #define F17H_M31H_CFACTOR_ISOC 310000 /* 0.31A / LSB */ |
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| 84 | |||
| 85 | /* F19h thermal registers through SMN */ |
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| 86 | #define F19H_M01_SVI_TEL_PLANE0 (ZEN_SVI_BASE + 0x14) |
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| 87 | #define F19H_M01_SVI_TEL_PLANE1 (ZEN_SVI_BASE + 0x10) |
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| 88 | |||
| 89 | #define F19H_M01H_CFACTOR_ICORE 1000000 /* 1A / LSB */ |
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| 90 | #define F19H_M01H_CFACTOR_ISOC 310000 /* 0.31A / LSB */ |
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| 91 | |||
| 92 | /* Provide lock for writing to NB_SMU_IND_ADDR */ |
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| 93 | DEFINE_MUTEX(nb_smu_ind_mutex); |
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| 94 | DEFINE_MUTEX(smn_mutex); |
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| 95 | |||
| 96 | struct k10temp_data { |
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| 97 | struct pci_dev *pdev; |
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| 98 | void (*read_htcreg)(struct pci_dev *pdev, u32 *regval); |
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| 99 | void (*read_tempreg)(struct pci_dev *pdev, u32 *regval); |
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| 100 | int temp_offset; |
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| 101 | u32 temp_adjust_mask; |
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| 102 | u32 show_temp; |
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| 103 | bool is_zen; |
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| 104 | }; |
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| 105 | |||
| 106 | #define TCTL_BIT 0 |
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| 107 | #define TDIE_BIT 1 |
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| 108 | #define TCCD_BIT(x) ((x) + 2) |
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| 109 | |||
| 110 | #define HAVE_TEMP(d, channel) ((d)->show_temp & BIT(channel)) |
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| 111 | #define HAVE_TDIE(d) HAVE_TEMP(d, TDIE_BIT) |
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| 112 | |||
| 113 | struct tctl_offset { |
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| 114 | u8 model; |
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| 115 | char const *id; |
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| 116 | int offset; |
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| 117 | }; |
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| 118 | |||
| 119 | const struct tctl_offset tctl_offset_table[] = { |
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| 120 | { 0x17, "AMD Ryzen 5 1600X", 20000 }, |
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| 121 | { 0x17, "AMD Ryzen 7 1700X", 20000 }, |
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| 122 | { 0x17, "AMD Ryzen 7 1800X", 20000 }, |
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| 123 | { 0x17, "AMD Ryzen 7 2700X", 10000 }, |
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| 124 | { 0x17, "AMD Ryzen Threadripper 19", 27000 }, /* 19{00,20,50}X */ |
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| 125 | { 0x17, "AMD Ryzen Threadripper 29", 27000 }, /* 29{20,50,70,90}[W]X */ |
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| 126 | }; |
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| 127 | |||
| 128 | void read_htcreg_pci(struct pci_dev *pdev, u32 *regval) |
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| 129 | { |
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| 130 | pci_read_config_dword(pdev, REG_HARDWARE_THERMAL_CONTROL, regval); |
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| 131 | } |
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| 132 | |||
| 133 | void read_tempreg_pci(struct pci_dev *pdev, u32 *regval) |
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| 134 | { |
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| 135 | pci_read_config_dword(pdev, REG_REPORTED_TEMPERATURE, regval); |
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| 136 | } |
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| 137 | |||
| 138 | void amd_nb_index_read(struct pci_dev *pdev, unsigned int devfn, |
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| 139 | unsigned int base, int offset, u32 *val) |
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| 140 | { |
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| 141 | mutex_lock(&nb_smu_ind_mutex); |
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| 142 | pci_bus_write_config_dword(pdev->bus, devfn, |
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| 143 | base, offset); |
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| 144 | pci_bus_read_config_dword(pdev->bus, devfn, |
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| 145 | base + 4, val); |
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| 146 | mutex_unlock(&nb_smu_ind_mutex); |
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| 147 | } |
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| 148 | |||
| 149 | void read_htcreg_nb_f15(struct pci_dev *pdev, u32 *regval) |
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| 150 | { |
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| 151 | amd_nb_index_read(pdev, PCI_DEVFN(0, 0), 0xb8, |
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| 152 | F15H_M60H_HARDWARE_TEMP_CTRL_OFFSET, regval); |
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| 153 | } |
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| 154 | |||
| 155 | void read_tempreg_nb_f15(struct pci_dev *pdev, u32 *regval) |
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| 156 | { |
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| 157 | amd_nb_index_read(pdev, PCI_DEVFN(0, 0), 0xb8, |
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| 158 | F15H_M60H_REPORTED_TEMP_CTRL_OFFSET, regval); |
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| 159 | } |
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| 160 | |||
| 161 | void read_tempreg_nb_zen(struct pci_dev *pdev, u32 *regval) |
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| 162 | { |
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| 163 | amd_smn_read(amd_pci_dev_to_node_id(pdev), |
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| 164 | ZEN_REPORTED_TEMP_CTRL_OFFSET, regval); |
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| 165 | } |
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| 166 | |||
| 167 | long get_raw_temp(struct k10temp_data *data) |
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| 168 | { |
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| 169 | u32 regval; |
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| 170 | long temp; |
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| 171 | data->read_tempreg(data->pdev, ®val); |
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| 172 | temp = (regval >> ZEN_CUR_TEMP_SHIFT) * 125; |
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| 173 | if (regval & data->temp_adjust_mask) |
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| 174 | temp -= 49000; |
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| 175 | return temp; |
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| 176 | } |
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| 9100 | turbocat | 177 | #if 0 |
| 9079 | turbocat | 178 | const char *k10temp_temp_label[] = { |
| 179 | "Tctl", |
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| 180 | "Tdie", |
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| 181 | "Tccd1", |
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| 182 | "Tccd2", |
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| 183 | "Tccd3", |
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| 184 | "Tccd4", |
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| 185 | "Tccd5", |
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| 186 | "Tccd6", |
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| 187 | "Tccd7", |
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| 188 | "Tccd8", |
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| 189 | }; |
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| 190 | |||
| 191 | int k10temp_read_labels(struct device *dev, |
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| 192 | enum hwmon_sensor_types type, |
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| 193 | u32 attr, int channel, const char **str) |
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| 194 | { |
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| 195 | switch (type) { |
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| 196 | case hwmon_temp: |
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| 197 | *str = k10temp_temp_label[channel]; |
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| 198 | break; |
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| 199 | default: |
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| 200 | return -EOPNOTSUPP; |
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| 201 | } |
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| 202 | return 0; |
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| 203 | } |
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| 9100 | turbocat | 204 | #endif |
| 9079 | turbocat | 205 | |
| 206 | int k10temp_read_temp(struct device *dev, u32 attr, int channel, |
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| 207 | long *val) |
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| 208 | { |
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| 209 | struct k10temp_data *data = dev_get_drvdata(dev); |
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| 210 | u32 regval; |
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| 211 | |||
| 212 | switch (attr) { |
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| 213 | case hwmon_temp_input: |
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| 214 | switch (channel) { |
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| 215 | case 0: /* Tctl */ |
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| 216 | *val = get_raw_temp(data); |
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| 217 | if (*val < 0) |
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| 218 | *val = 0; |
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| 219 | break; |
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| 220 | case 1: /* Tdie */ |
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| 221 | *val = get_raw_temp(data) - data->temp_offset; |
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| 222 | if (*val < 0) |
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| 223 | *val = 0; |
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| 224 | break; |
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| 225 | case 2 ... 9: /* Tccd{1-8} */ |
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| 226 | amd_smn_read(amd_pci_dev_to_node_id(data->pdev), |
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| 227 | ZEN_CCD_TEMP(channel - 2), ®val); |
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| 228 | *val = (regval & ZEN_CCD_TEMP_MASK) * 125 - 49000; |
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| 229 | break; |
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| 230 | default: |
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| 231 | return -EOPNOTSUPP; |
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| 232 | } |
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| 233 | break; |
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| 234 | case hwmon_temp_max: |
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| 235 | *val = 70 * 1000; |
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| 236 | break; |
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| 237 | case hwmon_temp_crit: |
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| 238 | data->read_htcreg(data->pdev, ®val); |
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| 239 | *val = ((regval >> 16) & 0x7f) * 500 + 52000; |
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| 240 | break; |
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| 241 | case hwmon_temp_crit_hyst: |
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| 242 | data->read_htcreg(data->pdev, ®val); |
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| 243 | *val = (((regval >> 16) & 0x7f) |
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| 244 | - ((regval >> 24) & 0xf)) * 500 + 52000; |
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| 245 | break; |
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| 246 | default: |
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| 247 | return -EOPNOTSUPP; |
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| 248 | } |
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| 249 | return 0; |
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| 250 | } |
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| 251 | |||
| 252 | int k10temp_read(struct device *dev, enum hwmon_sensor_types type, |
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| 253 | u32 attr, int channel, long *val) |
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| 254 | { |
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| 255 | switch (type) { |
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| 256 | case hwmon_temp: |
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| 257 | return k10temp_read_temp(dev, attr, channel, val); |
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| 258 | default: |
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| 259 | return -EOPNOTSUPP; |
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| 260 | } |
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| 261 | } |
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| 262 | |||
| 263 | umode_t k10temp_is_visible(const void *_data, |
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| 264 | enum hwmon_sensor_types type, |
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| 265 | u32 attr, int channel) |
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| 266 | { |
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| 267 | const struct k10temp_data *data = _data; |
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| 268 | struct pci_dev *pdev = data->pdev; |
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| 269 | u32 reg; |
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| 270 | |||
| 271 | switch (type) { |
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| 272 | case hwmon_temp: |
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| 273 | switch (attr) { |
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| 274 | case hwmon_temp_input: |
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| 275 | if (!HAVE_TEMP(data, channel)){ |
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| 276 | return 0; |
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| 277 | } |
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| 278 | break; |
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| 279 | case hwmon_temp_max: |
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| 280 | if (channel || data->is_zen) |
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| 281 | return 0; |
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| 282 | break; |
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| 283 | case hwmon_temp_crit: |
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| 284 | case hwmon_temp_crit_hyst: |
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| 285 | if (channel || !data->read_htcreg) |
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| 286 | return 0; |
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| 287 | |||
| 288 | pci_read_config_dword(pdev, |
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| 289 | REG_NORTHBRIDGE_CAPABILITIES, |
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| 290 | ®); |
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| 291 | if (!(reg & NB_CAP_HTC)) |
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| 292 | return 0; |
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| 293 | |||
| 294 | data->read_htcreg(data->pdev, ®); |
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| 295 | if (!(reg & HTC_ENABLE)) |
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| 296 | return 0; |
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| 297 | break; |
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| 9100 | turbocat | 298 | // case hwmon_temp_label: |
| 299 | // /* Show temperature labels only on Zen CPUs */ |
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| 300 | // if (!data->is_zen || !HAVE_TEMP(data, channel)) |
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| 301 | // return 0; |
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| 302 | // break; |
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| 9079 | turbocat | 303 | default: |
| 304 | return 0; |
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| 305 | } |
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| 306 | break; |
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| 307 | default: |
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| 308 | return 0; |
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| 309 | } |
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| 310 | return 0444; |
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| 311 | } |
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| 9100 | turbocat | 312 | #if 0 |
| 9079 | turbocat | 313 | bool has_erratum_319(struct pci_dev *pdev) |
| 314 | { |
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| 315 | u32 pkg_type, reg_dram_cfg; |
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| 316 | |||
| 317 | if (boot_cpu_data.x86 != 0x10) |
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| 318 | return false; |
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| 319 | |||
| 320 | /* |
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| 321 | * Erratum 319: The thermal sensor of Socket F/AM2+ processors |
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| 322 | * may be unreliable. |
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| 323 | */ |
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| 324 | pkg_type = cpuid_ebx(0x80000001) & CPUID_PKGTYPE_MASK; |
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| 325 | if (pkg_type == CPUID_PKGTYPE_F) |
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| 326 | return true; |
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| 327 | if (pkg_type != CPUID_PKGTYPE_AM2R2_AM3) |
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| 328 | return false; |
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| 329 | |||
| 330 | /* DDR3 memory implies socket AM3, which is good */ |
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| 331 | pci_bus_read_config_dword(pdev->bus, |
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| 332 | PCI_DEVFN(PCI_SLOT(pdev->devfn), 2), |
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| 333 | REG_DCT0_CONFIG_HIGH, ®_dram_cfg); |
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| 334 | if (reg_dram_cfg & DDR3_MODE) |
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| 335 | return false; |
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| 336 | |||
| 337 | /* |
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| 338 | * Unfortunately it is possible to run a socket AM3 CPU with DDR2 |
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| 339 | * memory. We blacklist all the cores which do exist in socket AM2+ |
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| 340 | * format. It still isn't perfect, as RB-C2 cores exist in both AM2+ |
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| 341 | * and AM3 formats, but that's the best we can do. |
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| 342 | */ |
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| 343 | |||
| 344 | return boot_cpu_data.x86_model < 4; |
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| 345 | } |
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| 9100 | turbocat | 346 | #endif |
| 9079 | turbocat | 347 | |
| 348 | const struct hwmon_channel_info *k10temp_info[] = { |
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| 349 | HWMON_CHANNEL_INFO(temp, |
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| 350 | HWMON_T_INPUT | HWMON_T_MAX | |
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| 351 | HWMON_T_CRIT | HWMON_T_CRIT_HYST | |
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| 352 | HWMON_T_LABEL, |
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| 353 | HWMON_T_INPUT | HWMON_T_LABEL, |
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| 354 | HWMON_T_INPUT | HWMON_T_LABEL, |
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| 355 | HWMON_T_INPUT | HWMON_T_LABEL, |
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| 356 | HWMON_T_INPUT | HWMON_T_LABEL, |
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| 357 | HWMON_T_INPUT | HWMON_T_LABEL, |
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| 358 | HWMON_T_INPUT | HWMON_T_LABEL, |
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| 359 | HWMON_T_INPUT | HWMON_T_LABEL, |
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| 360 | HWMON_T_INPUT | HWMON_T_LABEL, |
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| 361 | HWMON_T_INPUT | HWMON_T_LABEL), |
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| 362 | HWMON_CHANNEL_INFO(in, |
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| 363 | HWMON_I_INPUT | HWMON_I_LABEL, |
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| 364 | HWMON_I_INPUT | HWMON_I_LABEL), |
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| 365 | HWMON_CHANNEL_INFO(curr, |
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| 366 | HWMON_C_INPUT | HWMON_C_LABEL, |
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| 367 | HWMON_C_INPUT | HWMON_C_LABEL), |
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| 368 | NULL |
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| 369 | }; |
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| 370 | /* |
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| 371 | const struct hwmon_ops k10temp_hwmon_ops = { |
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| 372 | .is_visible = k10temp_is_visible, |
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| 373 | .read = k10temp_read, |
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| 374 | .read_string = k10temp_read_labels, |
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| 375 | };*/ |
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| 376 | /* |
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| 377 | const struct hwmon_chip_info k10temp_chip_info = { |
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| 378 | .ops = &k10temp_hwmon_ops, |
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| 379 | .info = k10temp_info, |
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| 380 | };*/ |
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| 381 | |||
| 382 | void k10temp_get_ccd_support(struct pci_dev *pdev, |
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| 383 | struct k10temp_data *data, int limit) |
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| 384 | { |
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| 385 | |||
| 386 | u32 regval; |
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| 387 | int i; |
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| 388 | |||
| 389 | for (i = 0; i < limit; i++) { |
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| 390 | amd_smn_read(amd_pci_dev_to_node_id(pdev), |
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| 391 | ZEN_CCD_TEMP(i), ®val); |
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| 392 | if (regval & ZEN_CCD_TEMP_VALID) |
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| 393 | data->show_temp |= BIT(TCCD_BIT(i)); |
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| 394 | } |
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| 395 | } |
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| 396 | |||
| 397 | int k10temp_probe(struct pci_dev *pdev, const struct pci_device_id *id, struct device *hwmon_dev) |
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| 398 | { |
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| 9100 | turbocat | 399 | // int unreliable = has_erratum_319(pdev); |
| 9079 | turbocat | 400 | struct device *dev = &pdev->dev; |
| 401 | struct k10temp_data *data; |
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| 402 | int i; |
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| 9100 | turbocat | 403 | /* if (unreliable) { |
| 9079 | turbocat | 404 | if (!force) { |
| 405 | dev_err(dev,"unreliable CPU thermal sensor; monitoring disabled\n"); |
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| 406 | return -ENODEV; |
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| 407 | } |
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| 408 | dev_warn(dev, |
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| 409 | "unreliable CPU thermal sensor; check erratum 319\n"); |
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| 410 | } |
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| 9100 | turbocat | 411 | */ |
| 9079 | turbocat | 412 | data = kzalloc(sizeof(struct k10temp_data), GFP_KERNEL); |
| 413 | memset(data, 0x0, sizeof(struct k10temp_data)); |
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| 414 | if (!data) |
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| 415 | return -ENOMEM; |
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| 416 | |||
| 417 | data->pdev = pdev; |
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| 418 | data->show_temp |= BIT(TCTL_BIT); /* Always show Tctl */ |
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| 419 | |||
| 420 | if (boot_cpu_data.x86 == 0x15 && |
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| 421 | ((boot_cpu_data.x86_model & 0xf0) == 0x60 || |
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| 422 | (boot_cpu_data.x86_model & 0xf0) == 0x70)) { |
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| 423 | data->read_htcreg = read_htcreg_nb_f15; |
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| 424 | data->read_tempreg = read_tempreg_nb_f15; |
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| 425 | |||
| 426 | } else if (boot_cpu_data.x86 == 0x17 || boot_cpu_data.x86 == 0x18) { |
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| 427 | data->temp_adjust_mask = ZEN_CUR_TEMP_RANGE_SEL_MASK; |
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| 428 | data->read_tempreg = read_tempreg_nb_zen; |
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| 429 | data->show_temp |= BIT(TDIE_BIT); /* show Tdie */ |
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| 430 | data->is_zen = true; |
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| 431 | |||
| 432 | switch (boot_cpu_data.x86_model) { |
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| 433 | case 0x1: /* Zen */ |
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| 434 | case 0x8: /* Zen+ */ |
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| 435 | case 0x11: /* Zen APU */ |
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| 436 | case 0x18: /* Zen+ APU */ |
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| 437 | k10temp_get_ccd_support(pdev, data, 4); |
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| 438 | break; |
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| 439 | case 0x31: /* Zen2 Threadripper */ |
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| 440 | case 0x71: /* Zen2 */ |
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| 441 | k10temp_get_ccd_support(pdev, data, 8); |
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| 442 | break; |
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| 443 | } |
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| 444 | } else if (boot_cpu_data.x86 == 0x19) { |
||
| 445 | data->temp_adjust_mask = ZEN_CUR_TEMP_RANGE_SEL_MASK; |
||
| 446 | data->read_tempreg = read_tempreg_nb_zen; |
||
| 447 | data->show_temp |= BIT(TDIE_BIT); |
||
| 448 | data->is_zen = true; |
||
| 449 | switch (boot_cpu_data.x86_model) { |
||
| 450 | case 0x0 ... 0x1: /* Zen3 SP3/TR */ |
||
| 451 | case 0x21: /* Zen3 Ryzen Desktop */ |
||
| 452 | k10temp_get_ccd_support(pdev, data, 8); |
||
| 453 | break; |
||
| 454 | } |
||
| 455 | } else { |
||
| 456 | data->read_htcreg = read_htcreg_pci; |
||
| 457 | data->read_tempreg = read_tempreg_pci; |
||
| 458 | } |
||
| 459 | |||
| 460 | for (i = 0; i < ARRAY_SIZE(tctl_offset_table); i++) { |
||
| 461 | const struct tctl_offset *entry = &tctl_offset_table[i]; |
||
| 462 | if (boot_cpu_data.x86 == entry->model && |
||
| 463 | strstr(boot_cpu_data.x86_model_id, entry->id)) { |
||
| 464 | data->temp_offset = entry->offset; |
||
| 465 | break; |
||
| 466 | } |
||
| 467 | } |
||
| 468 | |||
| 469 | hwmon_dev->driver_data=data; |
||
| 470 | return PTR_ERR_OR_ZERO(hwmon_dev); |
||
| 471 | } |
||
| 472 | |||
| 473 | const struct pci_device_id k10temp_id_table[] = { |
||
| 474 | { PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_10H_NB_MISC) }, |
||
| 475 | { PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_11H_NB_MISC) }, |
||
| 476 | { PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_CNB17H_F3) }, |
||
| 477 | { PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_15H_NB_F3) }, |
||
| 478 | { PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_15H_M10H_F3) }, |
||
| 479 | { PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_15H_M30H_NB_F3) }, |
||
| 480 | { PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_15H_M60H_NB_F3) }, |
||
| 481 | { PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_15H_M70H_NB_F3) }, |
||
| 482 | { PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_16H_NB_F3) }, |
||
| 483 | { PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_16H_M30H_NB_F3) }, |
||
| 484 | { PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_17H_DF_F3) }, |
||
| 485 | { PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_17H_M10H_DF_F3) }, |
||
| 486 | { PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_17H_M30H_DF_F3) }, |
||
| 487 | { PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_17H_M60H_DF_F3) }, |
||
| 488 | { PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_17H_M70H_DF_F3) }, |
||
| 489 | { PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_19H_DF_F3) }, |
||
| 490 | { PCI_VDEVICE(HYGON, PCI_DEVICE_ID_AMD_17H_DF_F3) }, |
||
| 491 | {} |
||
| 492 | }; |
||
| 493 | |||
| 9100 | turbocat | 494 | #define K10TEMP_NA (~0) |
| 495 | #define CHANEL_MAX 9 |
||
| 496 | |||
| 497 | #pragma pack(push, 1) |
||
| 498 | struct{ |
||
| 499 | int Tctl; |
||
| 500 | int Tdie; |
||
| 501 | int Tccd1; |
||
| 502 | int Tccd2; |
||
| 503 | int Tccd3; |
||
| 504 | int Tccd4; |
||
| 505 | int Tccd5; |
||
| 506 | int Tccd6; |
||
| 507 | int Tccd7; |
||
| 508 | int Tccd8; |
||
| 509 | |||
| 510 | int Tmax; |
||
| 511 | int Tcrit; |
||
| 512 | int Tcrit_hyst; |
||
| 513 | }k10temp_out; |
||
| 514 | #pragma pack(pop) |
||
| 515 | |||
| 516 | struct device k10temp_device; |
||
| 517 | |||
| 518 | void read_temp_info(struct device *dev, u32 attr, int channel, int *val){ |
||
| 519 | long temp=0; |
||
| 520 | if(k10temp_is_visible(dev->driver_data, hwmon_temp, attr, channel)){ |
||
| 521 | k10temp_read_temp(dev, attr, channel, &temp); |
||
| 522 | *val=temp; |
||
| 523 | }else{ |
||
| 524 | *val=K10TEMP_NA; |
||
| 525 | } |
||
| 9079 | turbocat | 526 | } |
| 527 | |||
| 9100 | turbocat | 528 | void read_all_info(struct device* dev){ |
| 529 | for(int c=0; c<=CHANEL_MAX; c++){ |
||
| 530 | read_temp_info(dev, hwmon_temp_input, c, (int*)&k10temp_out+c); |
||
| 531 | } |
||
| 532 | read_temp_info(dev, hwmon_temp_max, 0, &k10temp_out.Tmax); |
||
| 533 | read_temp_info(dev, hwmon_temp_crit, 0, &k10temp_out.Tcrit); |
||
| 534 | read_temp_info(dev, hwmon_temp_crit_hyst, 0, &k10temp_out.Tcrit_hyst); |
||
| 9079 | turbocat | 535 | } |
| 536 | |||
| 9100 | turbocat | 537 | int __stdcall service_proc(ioctl_t *my_ctl){ |
| 9144 | turbocat | 538 | if(!my_ctl || !my_ctl->output || (int)my_ctl->output>=KERNEL_SPACE-sizeof(k10temp_out)){ |
| 539 | printk("k10temp: Bad address for writing data!\n"); |
||
| 540 | return 0; |
||
| 9079 | turbocat | 541 | } |
| 9144 | turbocat | 542 | |
| 9100 | turbocat | 543 | read_all_info(&k10temp_device); |
| 9144 | turbocat | 544 | |
| 9100 | turbocat | 545 | if(my_ctl->out_size == sizeof(k10temp_out)){ |
| 546 | memcpy(my_ctl->output, &k10temp_out, sizeof(k10temp_out)); |
||
| 547 | return 0; |
||
| 548 | } |
||
| 9144 | turbocat | 549 | printk("k10temp: Invalid buffer length!\n"); |
| 9100 | turbocat | 550 | return 1; |
| 9079 | turbocat | 551 | } |
| 552 | |||
| 553 | uint32_t drvEntry(int action, char *cmdline){ |
||
| 554 | if(action != 1){ |
||
| 555 | return 0; |
||
| 556 | } |
||
| 9100 | turbocat | 557 | pci_dev_t device; |
| 558 | const struct pci_device_id *k10temp_id; |
||
| 9079 | turbocat | 559 | int err; |
| 560 | |||
| 561 | cpu_detect(&boot_cpu_data); |
||
| 562 | |||
| 563 | err = enum_pci_devices(); |
||
| 564 | if(unlikely(err != 0)) { |
||
| 9100 | turbocat | 565 | printk("k10temp: Device enumeration failed!\n"); |
| 9144 | turbocat | 566 | return 0; |
| 9079 | turbocat | 567 | } |
| 568 | |||
| 569 | k10temp_id = find_pci_device(&device, k10temp_id_table); |
||
| 9100 | turbocat | 570 | |
| 571 | if(unlikely(k10temp_id == NULL)){ |
||
| 572 | printk("k10temp: Device not found!\n"); |
||
| 9144 | turbocat | 573 | return 0; |
| 9079 | turbocat | 574 | } |
| 9100 | turbocat | 575 | |
| 9079 | turbocat | 576 | init_amd_nbs(); |
| 9100 | turbocat | 577 | k10temp_probe(&device.pci_dev, k10temp_id, &k10temp_device); |
| 9079 | turbocat | 578 | return RegService("k10temp", service_proc); |
| 579 | } |