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| Rev | Author | Line No. | Line |
|---|---|---|---|
| 9079 | turbocat | 1 | // SPDX-License-Identifier: GPL-2.0-or-later |
| 2 | /* |
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| 3 | * k10temp.c - AMD Family 10h/11h/12h/14h/15h/16h/17h |
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| 4 | * processor hardware monitoring |
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| 5 | * |
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| 6 | * Copyright (c) 2009 Clemens Ladisch |
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| 7 | * Copyright (c) 2020 Guenter Roeck |
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| 8 | * |
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| 9 | * Implementation notes: |
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| 10 | * - CCD register address information as well as the calculation to |
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| 11 | * convert raw register values is from https://github.com/ocerman/zenpower. |
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| 12 | * The information is not confirmed from chip datasheets, but experiments |
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| 13 | * suggest that it provides reasonable temperature values. |
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| 14 | */ |
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| 15 | |||
| 9100 | turbocat | 16 | /* Ported for Kolibri OS by turbocat (Maxim Logaeav). 2021 */ |
| 17 | /* Thanks: dunkaist, punk_joker, doczom. */ |
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| 18 | |||
| 9079 | turbocat | 19 | #include |
| 20 | #include |
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| 21 | #include |
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| 22 | #include |
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| 23 | #include |
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| 24 | #include |
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| 25 | #include |
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| 26 | #include |
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| 27 | #include |
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| 28 | #include |
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| 29 | |||
| 30 | struct cpuinfo_x86 boot_cpu_data; |
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| 31 | bool force; |
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| 32 | |||
| 33 | /* CPUID function 0x80000001, ebx */ |
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| 34 | #define CPUID_PKGTYPE_MASK GENMASK(31, 28) |
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| 35 | #define CPUID_PKGTYPE_F 0x00000000 |
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| 36 | #define CPUID_PKGTYPE_AM2R2_AM3 0x10000000 |
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| 37 | |||
| 38 | /* DRAM controller (PCI function 2) */ |
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| 39 | #define REG_DCT0_CONFIG_HIGH 0x094 |
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| 40 | #define DDR3_MODE BIT(8) |
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| 41 | |||
| 42 | /* miscellaneous (PCI function 3) */ |
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| 43 | #define REG_HARDWARE_THERMAL_CONTROL 0x64 |
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| 44 | #define HTC_ENABLE BIT(0) |
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| 45 | |||
| 46 | #define REG_REPORTED_TEMPERATURE 0xa4 |
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| 47 | |||
| 48 | #define REG_NORTHBRIDGE_CAPABILITIES 0xe8 |
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| 49 | #define NB_CAP_HTC BIT(10) |
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| 50 | |||
| 51 | /* |
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| 52 | * For F15h M60h and M70h, REG_HARDWARE_THERMAL_CONTROL |
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| 53 | * and REG_REPORTED_TEMPERATURE have been moved to |
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| 54 | * D0F0xBC_xD820_0C64 [Hardware Temperature Control] |
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| 55 | * D0F0xBC_xD820_0CA4 [Reported Temperature Control] |
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| 56 | */ |
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| 57 | #define F15H_M60H_HARDWARE_TEMP_CTRL_OFFSET 0xd8200c64 |
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| 58 | #define F15H_M60H_REPORTED_TEMP_CTRL_OFFSET 0xd8200ca4 |
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| 59 | |||
| 60 | /* Common for Zen CPU families (Family 17h and 18h) */ |
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| 61 | #define ZEN_REPORTED_TEMP_CTRL_OFFSET 0x00059800 |
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| 62 | |||
| 63 | #define ZEN_CCD_TEMP(x) (0x00059954 + ((x) * 4)) |
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| 64 | #define ZEN_CCD_TEMP_VALID BIT(11) |
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| 65 | #define ZEN_CCD_TEMP_MASK GENMASK(10, 0) |
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| 66 | |||
| 67 | #define ZEN_CUR_TEMP_SHIFT 21 |
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| 68 | #define ZEN_CUR_TEMP_RANGE_SEL_MASK BIT(19) |
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| 69 | |||
| 70 | #define ZEN_SVI_BASE 0x0005A000 |
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| 71 | |||
| 72 | /* F17h thermal registers through SMN */ |
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| 73 | #define F17H_M01H_SVI_TEL_PLANE0 (ZEN_SVI_BASE + 0xc) |
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| 74 | #define F17H_M01H_SVI_TEL_PLANE1 (ZEN_SVI_BASE + 0x10) |
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| 75 | #define F17H_M31H_SVI_TEL_PLANE0 (ZEN_SVI_BASE + 0x14) |
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| 76 | #define F17H_M31H_SVI_TEL_PLANE1 (ZEN_SVI_BASE + 0x10) |
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| 77 | |||
| 78 | #define F17H_M01H_CFACTOR_ICORE 1000000 /* 1A / LSB */ |
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| 79 | #define F17H_M01H_CFACTOR_ISOC 250000 /* 0.25A / LSB */ |
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| 80 | #define F17H_M31H_CFACTOR_ICORE 1000000 /* 1A / LSB */ |
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| 81 | #define F17H_M31H_CFACTOR_ISOC 310000 /* 0.31A / LSB */ |
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| 82 | |||
| 83 | /* F19h thermal registers through SMN */ |
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| 84 | #define F19H_M01_SVI_TEL_PLANE0 (ZEN_SVI_BASE + 0x14) |
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| 85 | #define F19H_M01_SVI_TEL_PLANE1 (ZEN_SVI_BASE + 0x10) |
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| 86 | |||
| 87 | #define F19H_M01H_CFACTOR_ICORE 1000000 /* 1A / LSB */ |
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| 88 | #define F19H_M01H_CFACTOR_ISOC 310000 /* 0.31A / LSB */ |
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| 89 | |||
| 90 | /* Provide lock for writing to NB_SMU_IND_ADDR */ |
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| 91 | DEFINE_MUTEX(nb_smu_ind_mutex); |
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| 92 | DEFINE_MUTEX(smn_mutex); |
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| 93 | |||
| 94 | struct k10temp_data { |
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| 95 | struct pci_dev *pdev; |
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| 96 | void (*read_htcreg)(struct pci_dev *pdev, u32 *regval); |
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| 97 | void (*read_tempreg)(struct pci_dev *pdev, u32 *regval); |
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| 98 | int temp_offset; |
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| 99 | u32 temp_adjust_mask; |
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| 100 | u32 show_temp; |
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| 101 | bool is_zen; |
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| 102 | }; |
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| 103 | |||
| 104 | #define TCTL_BIT 0 |
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| 105 | #define TDIE_BIT 1 |
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| 106 | #define TCCD_BIT(x) ((x) + 2) |
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| 107 | |||
| 108 | #define HAVE_TEMP(d, channel) ((d)->show_temp & BIT(channel)) |
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| 109 | #define HAVE_TDIE(d) HAVE_TEMP(d, TDIE_BIT) |
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| 110 | |||
| 111 | struct tctl_offset { |
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| 112 | u8 model; |
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| 113 | char const *id; |
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| 114 | int offset; |
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| 115 | }; |
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| 116 | |||
| 117 | const struct tctl_offset tctl_offset_table[] = { |
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| 118 | { 0x17, "AMD Ryzen 5 1600X", 20000 }, |
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| 119 | { 0x17, "AMD Ryzen 7 1700X", 20000 }, |
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| 120 | { 0x17, "AMD Ryzen 7 1800X", 20000 }, |
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| 121 | { 0x17, "AMD Ryzen 7 2700X", 10000 }, |
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| 122 | { 0x17, "AMD Ryzen Threadripper 19", 27000 }, /* 19{00,20,50}X */ |
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| 123 | { 0x17, "AMD Ryzen Threadripper 29", 27000 }, /* 29{20,50,70,90}[W]X */ |
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| 124 | }; |
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| 125 | |||
| 126 | void read_htcreg_pci(struct pci_dev *pdev, u32 *regval) |
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| 127 | { |
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| 128 | pci_read_config_dword(pdev, REG_HARDWARE_THERMAL_CONTROL, regval); |
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| 129 | } |
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| 130 | |||
| 131 | void read_tempreg_pci(struct pci_dev *pdev, u32 *regval) |
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| 132 | { |
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| 133 | pci_read_config_dword(pdev, REG_REPORTED_TEMPERATURE, regval); |
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| 134 | } |
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| 135 | |||
| 136 | void amd_nb_index_read(struct pci_dev *pdev, unsigned int devfn, |
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| 137 | unsigned int base, int offset, u32 *val) |
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| 138 | { |
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| 139 | mutex_lock(&nb_smu_ind_mutex); |
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| 140 | pci_bus_write_config_dword(pdev->bus, devfn, |
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| 141 | base, offset); |
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| 142 | pci_bus_read_config_dword(pdev->bus, devfn, |
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| 143 | base + 4, val); |
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| 144 | mutex_unlock(&nb_smu_ind_mutex); |
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| 145 | } |
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| 146 | |||
| 147 | void read_htcreg_nb_f15(struct pci_dev *pdev, u32 *regval) |
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| 148 | { |
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| 149 | amd_nb_index_read(pdev, PCI_DEVFN(0, 0), 0xb8, |
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| 150 | F15H_M60H_HARDWARE_TEMP_CTRL_OFFSET, regval); |
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| 151 | } |
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| 152 | |||
| 153 | void read_tempreg_nb_f15(struct pci_dev *pdev, u32 *regval) |
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| 154 | { |
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| 155 | amd_nb_index_read(pdev, PCI_DEVFN(0, 0), 0xb8, |
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| 156 | F15H_M60H_REPORTED_TEMP_CTRL_OFFSET, regval); |
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| 157 | } |
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| 158 | |||
| 159 | void read_tempreg_nb_zen(struct pci_dev *pdev, u32 *regval) |
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| 160 | { |
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| 161 | amd_smn_read(amd_pci_dev_to_node_id(pdev), |
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| 162 | ZEN_REPORTED_TEMP_CTRL_OFFSET, regval); |
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| 163 | } |
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| 164 | |||
| 165 | long get_raw_temp(struct k10temp_data *data) |
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| 166 | { |
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| 167 | u32 regval; |
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| 168 | long temp; |
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| 169 | //printk("b30\n"); |
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| 170 | data->read_tempreg(data->pdev, ®val); |
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| 171 | temp = (regval >> ZEN_CUR_TEMP_SHIFT) * 125; |
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| 172 | if (regval & data->temp_adjust_mask) |
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| 173 | temp -= 49000; |
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| 174 | return temp; |
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| 175 | } |
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| 9100 | turbocat | 176 | #if 0 |
| 9079 | turbocat | 177 | const char *k10temp_temp_label[] = { |
| 178 | "Tctl", |
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| 179 | "Tdie", |
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| 180 | "Tccd1", |
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| 181 | "Tccd2", |
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| 182 | "Tccd3", |
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| 183 | "Tccd4", |
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| 184 | "Tccd5", |
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| 185 | "Tccd6", |
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| 186 | "Tccd7", |
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| 187 | "Tccd8", |
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| 188 | }; |
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| 189 | |||
| 190 | int k10temp_read_labels(struct device *dev, |
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| 191 | enum hwmon_sensor_types type, |
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| 192 | u32 attr, int channel, const char **str) |
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| 193 | { |
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| 194 | switch (type) { |
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| 195 | case hwmon_temp: |
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| 196 | *str = k10temp_temp_label[channel]; |
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| 197 | break; |
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| 198 | default: |
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| 199 | return -EOPNOTSUPP; |
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| 200 | } |
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| 201 | return 0; |
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| 202 | } |
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| 9100 | turbocat | 203 | #endif |
| 9079 | turbocat | 204 | |
| 205 | int k10temp_read_temp(struct device *dev, u32 attr, int channel, |
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| 206 | long *val) |
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| 207 | { |
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| 208 | struct k10temp_data *data = dev_get_drvdata(dev); |
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| 209 | u32 regval; |
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| 210 | |||
| 211 | switch (attr) { |
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| 212 | case hwmon_temp_input: |
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| 213 | switch (channel) { |
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| 214 | case 0: /* Tctl */ |
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| 215 | *val = get_raw_temp(data); |
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| 216 | if (*val < 0) |
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| 217 | *val = 0; |
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| 218 | break; |
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| 219 | case 1: /* Tdie */ |
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| 220 | *val = get_raw_temp(data) - data->temp_offset; |
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| 221 | if (*val < 0) |
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| 222 | *val = 0; |
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| 223 | break; |
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| 224 | case 2 ... 9: /* Tccd{1-8} */ |
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| 225 | amd_smn_read(amd_pci_dev_to_node_id(data->pdev), |
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| 226 | ZEN_CCD_TEMP(channel - 2), ®val); |
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| 227 | *val = (regval & ZEN_CCD_TEMP_MASK) * 125 - 49000; |
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| 228 | break; |
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| 229 | default: |
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| 230 | return -EOPNOTSUPP; |
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| 231 | } |
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| 232 | break; |
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| 233 | case hwmon_temp_max: |
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| 234 | *val = 70 * 1000; |
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| 235 | break; |
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| 236 | case hwmon_temp_crit: |
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| 237 | data->read_htcreg(data->pdev, ®val); |
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| 238 | *val = ((regval >> 16) & 0x7f) * 500 + 52000; |
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| 239 | break; |
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| 240 | case hwmon_temp_crit_hyst: |
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| 241 | data->read_htcreg(data->pdev, ®val); |
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| 242 | *val = (((regval >> 16) & 0x7f) |
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| 243 | - ((regval >> 24) & 0xf)) * 500 + 52000; |
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| 244 | break; |
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| 245 | default: |
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| 246 | return -EOPNOTSUPP; |
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| 247 | } |
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| 248 | return 0; |
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| 249 | } |
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| 250 | |||
| 251 | int k10temp_read(struct device *dev, enum hwmon_sensor_types type, |
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| 252 | u32 attr, int channel, long *val) |
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| 253 | { |
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| 254 | switch (type) { |
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| 255 | case hwmon_temp: |
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| 256 | return k10temp_read_temp(dev, attr, channel, val); |
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| 257 | default: |
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| 258 | return -EOPNOTSUPP; |
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| 259 | } |
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| 260 | } |
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| 261 | |||
| 262 | umode_t k10temp_is_visible(const void *_data, |
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| 263 | enum hwmon_sensor_types type, |
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| 264 | u32 attr, int channel) |
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| 265 | { |
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| 266 | const struct k10temp_data *data = _data; |
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| 267 | struct pci_dev *pdev = data->pdev; |
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| 268 | u32 reg; |
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| 269 | |||
| 270 | switch (type) { |
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| 271 | case hwmon_temp: |
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| 272 | switch (attr) { |
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| 273 | case hwmon_temp_input: |
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| 274 | if (!HAVE_TEMP(data, channel)){ |
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| 275 | return 0; |
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| 276 | } |
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| 277 | break; |
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| 278 | case hwmon_temp_max: |
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| 279 | if (channel || data->is_zen) |
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| 280 | return 0; |
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| 281 | break; |
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| 282 | case hwmon_temp_crit: |
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| 283 | case hwmon_temp_crit_hyst: |
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| 284 | if (channel || !data->read_htcreg) |
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| 285 | return 0; |
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| 286 | |||
| 287 | pci_read_config_dword(pdev, |
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| 288 | REG_NORTHBRIDGE_CAPABILITIES, |
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| 289 | ®); |
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| 290 | if (!(reg & NB_CAP_HTC)) |
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| 291 | return 0; |
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| 292 | |||
| 293 | data->read_htcreg(data->pdev, ®); |
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| 294 | if (!(reg & HTC_ENABLE)) |
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| 295 | return 0; |
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| 296 | break; |
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| 9100 | turbocat | 297 | // case hwmon_temp_label: |
| 298 | // /* Show temperature labels only on Zen CPUs */ |
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| 299 | // if (!data->is_zen || !HAVE_TEMP(data, channel)) |
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| 300 | // return 0; |
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| 301 | // break; |
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| 9079 | turbocat | 302 | default: |
| 303 | return 0; |
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| 304 | } |
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| 305 | break; |
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| 306 | default: |
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| 307 | return 0; |
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| 308 | } |
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| 309 | return 0444; |
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| 310 | } |
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| 9100 | turbocat | 311 | #if 0 |
| 9079 | turbocat | 312 | bool has_erratum_319(struct pci_dev *pdev) |
| 313 | { |
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| 314 | u32 pkg_type, reg_dram_cfg; |
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| 315 | |||
| 316 | if (boot_cpu_data.x86 != 0x10) |
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| 317 | return false; |
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| 318 | |||
| 319 | /* |
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| 320 | * Erratum 319: The thermal sensor of Socket F/AM2+ processors |
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| 321 | * may be unreliable. |
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| 322 | */ |
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| 323 | pkg_type = cpuid_ebx(0x80000001) & CPUID_PKGTYPE_MASK; |
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| 324 | if (pkg_type == CPUID_PKGTYPE_F) |
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| 325 | return true; |
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| 326 | if (pkg_type != CPUID_PKGTYPE_AM2R2_AM3) |
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| 327 | return false; |
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| 328 | |||
| 329 | /* DDR3 memory implies socket AM3, which is good */ |
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| 330 | pci_bus_read_config_dword(pdev->bus, |
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| 331 | PCI_DEVFN(PCI_SLOT(pdev->devfn), 2), |
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| 332 | REG_DCT0_CONFIG_HIGH, ®_dram_cfg); |
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| 333 | if (reg_dram_cfg & DDR3_MODE) |
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| 334 | return false; |
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| 335 | |||
| 336 | /* |
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| 337 | * Unfortunately it is possible to run a socket AM3 CPU with DDR2 |
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| 338 | * memory. We blacklist all the cores which do exist in socket AM2+ |
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| 339 | * format. It still isn't perfect, as RB-C2 cores exist in both AM2+ |
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| 340 | * and AM3 formats, but that's the best we can do. |
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| 341 | */ |
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| 342 | |||
| 343 | return boot_cpu_data.x86_model < 4; |
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| 344 | } |
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| 9100 | turbocat | 345 | #endif |
| 9079 | turbocat | 346 | |
| 347 | const struct hwmon_channel_info *k10temp_info[] = { |
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| 348 | HWMON_CHANNEL_INFO(temp, |
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| 349 | HWMON_T_INPUT | HWMON_T_MAX | |
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| 350 | HWMON_T_CRIT | HWMON_T_CRIT_HYST | |
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| 351 | HWMON_T_LABEL, |
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| 352 | HWMON_T_INPUT | HWMON_T_LABEL, |
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| 353 | HWMON_T_INPUT | HWMON_T_LABEL, |
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| 354 | HWMON_T_INPUT | HWMON_T_LABEL, |
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| 355 | HWMON_T_INPUT | HWMON_T_LABEL, |
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| 356 | HWMON_T_INPUT | HWMON_T_LABEL, |
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| 357 | HWMON_T_INPUT | HWMON_T_LABEL, |
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| 358 | HWMON_T_INPUT | HWMON_T_LABEL, |
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| 359 | HWMON_T_INPUT | HWMON_T_LABEL, |
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| 360 | HWMON_T_INPUT | HWMON_T_LABEL), |
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| 361 | HWMON_CHANNEL_INFO(in, |
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| 362 | HWMON_I_INPUT | HWMON_I_LABEL, |
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| 363 | HWMON_I_INPUT | HWMON_I_LABEL), |
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| 364 | HWMON_CHANNEL_INFO(curr, |
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| 365 | HWMON_C_INPUT | HWMON_C_LABEL, |
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| 366 | HWMON_C_INPUT | HWMON_C_LABEL), |
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| 367 | NULL |
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| 368 | }; |
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| 369 | /* |
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| 370 | const struct hwmon_ops k10temp_hwmon_ops = { |
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| 371 | .is_visible = k10temp_is_visible, |
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| 372 | .read = k10temp_read, |
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| 373 | .read_string = k10temp_read_labels, |
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| 374 | };*/ |
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| 375 | /* |
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| 376 | const struct hwmon_chip_info k10temp_chip_info = { |
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| 377 | .ops = &k10temp_hwmon_ops, |
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| 378 | .info = k10temp_info, |
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| 379 | };*/ |
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| 380 | |||
| 381 | void k10temp_get_ccd_support(struct pci_dev *pdev, |
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| 382 | struct k10temp_data *data, int limit) |
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| 383 | { |
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| 384 | |||
| 385 | u32 regval; |
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| 386 | int i; |
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| 387 | |||
| 388 | for (i = 0; i < limit; i++) { |
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| 389 | amd_smn_read(amd_pci_dev_to_node_id(pdev), |
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| 390 | ZEN_CCD_TEMP(i), ®val); |
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| 391 | if (regval & ZEN_CCD_TEMP_VALID) |
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| 392 | data->show_temp |= BIT(TCCD_BIT(i)); |
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| 393 | } |
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| 394 | } |
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| 395 | |||
| 396 | int k10temp_probe(struct pci_dev *pdev, const struct pci_device_id *id, struct device *hwmon_dev) |
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| 397 | { |
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| 9100 | turbocat | 398 | // int unreliable = has_erratum_319(pdev); |
| 9079 | turbocat | 399 | struct device *dev = &pdev->dev; |
| 400 | struct k10temp_data *data; |
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| 401 | int i; |
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| 9100 | turbocat | 402 | /* if (unreliable) { |
| 9079 | turbocat | 403 | if (!force) { |
| 404 | dev_err(dev,"unreliable CPU thermal sensor; monitoring disabled\n"); |
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| 405 | return -ENODEV; |
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| 406 | } |
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| 407 | dev_warn(dev, |
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| 408 | "unreliable CPU thermal sensor; check erratum 319\n"); |
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| 409 | } |
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| 9100 | turbocat | 410 | */ |
| 9079 | turbocat | 411 | data = kzalloc(sizeof(struct k10temp_data), GFP_KERNEL); |
| 412 | memset(data, 0x0, sizeof(struct k10temp_data)); |
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| 413 | if (!data) |
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| 414 | return -ENOMEM; |
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| 415 | |||
| 416 | data->pdev = pdev; |
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| 417 | data->show_temp |= BIT(TCTL_BIT); /* Always show Tctl */ |
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| 418 | |||
| 419 | if (boot_cpu_data.x86 == 0x15 && |
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| 420 | ((boot_cpu_data.x86_model & 0xf0) == 0x60 || |
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| 421 | (boot_cpu_data.x86_model & 0xf0) == 0x70)) { |
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| 422 | data->read_htcreg = read_htcreg_nb_f15; |
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| 423 | data->read_tempreg = read_tempreg_nb_f15; |
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| 424 | |||
| 425 | } else if (boot_cpu_data.x86 == 0x17 || boot_cpu_data.x86 == 0x18) { |
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| 426 | data->temp_adjust_mask = ZEN_CUR_TEMP_RANGE_SEL_MASK; |
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| 427 | data->read_tempreg = read_tempreg_nb_zen; |
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| 428 | data->show_temp |= BIT(TDIE_BIT); /* show Tdie */ |
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| 429 | data->is_zen = true; |
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| 430 | |||
| 431 | switch (boot_cpu_data.x86_model) { |
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| 432 | case 0x1: /* Zen */ |
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| 433 | case 0x8: /* Zen+ */ |
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| 434 | case 0x11: /* Zen APU */ |
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| 435 | case 0x18: /* Zen+ APU */ |
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| 436 | k10temp_get_ccd_support(pdev, data, 4); |
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| 437 | break; |
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| 438 | case 0x31: /* Zen2 Threadripper */ |
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| 439 | case 0x71: /* Zen2 */ |
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| 440 | k10temp_get_ccd_support(pdev, data, 8); |
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| 441 | break; |
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| 442 | } |
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| 443 | } else if (boot_cpu_data.x86 == 0x19) { |
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| 444 | data->temp_adjust_mask = ZEN_CUR_TEMP_RANGE_SEL_MASK; |
||
| 445 | data->read_tempreg = read_tempreg_nb_zen; |
||
| 446 | data->show_temp |= BIT(TDIE_BIT); |
||
| 447 | data->is_zen = true; |
||
| 448 | switch (boot_cpu_data.x86_model) { |
||
| 449 | case 0x0 ... 0x1: /* Zen3 SP3/TR */ |
||
| 450 | case 0x21: /* Zen3 Ryzen Desktop */ |
||
| 451 | k10temp_get_ccd_support(pdev, data, 8); |
||
| 452 | break; |
||
| 453 | } |
||
| 454 | } else { |
||
| 455 | data->read_htcreg = read_htcreg_pci; |
||
| 456 | data->read_tempreg = read_tempreg_pci; |
||
| 457 | } |
||
| 458 | |||
| 459 | for (i = 0; i < ARRAY_SIZE(tctl_offset_table); i++) { |
||
| 460 | const struct tctl_offset *entry = &tctl_offset_table[i]; |
||
| 461 | if (boot_cpu_data.x86 == entry->model && |
||
| 462 | strstr(boot_cpu_data.x86_model_id, entry->id)) { |
||
| 463 | data->temp_offset = entry->offset; |
||
| 464 | break; |
||
| 465 | } |
||
| 466 | } |
||
| 467 | |||
| 468 | hwmon_dev->driver_data=data; |
||
| 469 | return PTR_ERR_OR_ZERO(hwmon_dev); |
||
| 470 | } |
||
| 471 | |||
| 472 | const struct pci_device_id k10temp_id_table[] = { |
||
| 473 | { PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_10H_NB_MISC) }, |
||
| 474 | { PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_11H_NB_MISC) }, |
||
| 475 | { PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_CNB17H_F3) }, |
||
| 476 | { PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_15H_NB_F3) }, |
||
| 477 | { PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_15H_M10H_F3) }, |
||
| 478 | { PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_15H_M30H_NB_F3) }, |
||
| 479 | { PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_15H_M60H_NB_F3) }, |
||
| 480 | { PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_15H_M70H_NB_F3) }, |
||
| 481 | { PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_16H_NB_F3) }, |
||
| 482 | { PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_16H_M30H_NB_F3) }, |
||
| 483 | { PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_17H_DF_F3) }, |
||
| 484 | { PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_17H_M10H_DF_F3) }, |
||
| 485 | { PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_17H_M30H_DF_F3) }, |
||
| 486 | { PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_17H_M60H_DF_F3) }, |
||
| 487 | { PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_17H_M70H_DF_F3) }, |
||
| 488 | { PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_19H_DF_F3) }, |
||
| 489 | { PCI_VDEVICE(HYGON, PCI_DEVICE_ID_AMD_17H_DF_F3) }, |
||
| 490 | {} |
||
| 491 | }; |
||
| 492 | |||
| 9100 | turbocat | 493 | #define K10TEMP_NA (~0) |
| 494 | #define CHANEL_MAX 9 |
||
| 495 | |||
| 496 | #pragma pack(push, 1) |
||
| 497 | struct{ |
||
| 498 | int Tctl; |
||
| 499 | int Tdie; |
||
| 500 | int Tccd1; |
||
| 501 | int Tccd2; |
||
| 502 | int Tccd3; |
||
| 503 | int Tccd4; |
||
| 504 | int Tccd5; |
||
| 505 | int Tccd6; |
||
| 506 | int Tccd7; |
||
| 507 | int Tccd8; |
||
| 508 | |||
| 509 | int Tmax; |
||
| 510 | int Tcrit; |
||
| 511 | int Tcrit_hyst; |
||
| 512 | }k10temp_out; |
||
| 513 | #pragma pack(pop) |
||
| 514 | |||
| 515 | struct device k10temp_device; |
||
| 516 | |||
| 517 | void read_temp_info(struct device *dev, u32 attr, int channel, int *val){ |
||
| 518 | long temp=0; |
||
| 519 | if(k10temp_is_visible(dev->driver_data, hwmon_temp, attr, channel)){ |
||
| 520 | k10temp_read_temp(dev, attr, channel, &temp); |
||
| 521 | *val=temp; |
||
| 522 | }else{ |
||
| 523 | *val=K10TEMP_NA; |
||
| 524 | } |
||
| 9079 | turbocat | 525 | } |
| 526 | |||
| 9100 | turbocat | 527 | void read_all_info(struct device* dev){ |
| 528 | for(int c=0; c<=CHANEL_MAX; c++){ |
||
| 529 | read_temp_info(dev, hwmon_temp_input, c, (int*)&k10temp_out+c); |
||
| 530 | } |
||
| 531 | read_temp_info(dev, hwmon_temp_max, 0, &k10temp_out.Tmax); |
||
| 532 | read_temp_info(dev, hwmon_temp_crit, 0, &k10temp_out.Tcrit); |
||
| 533 | read_temp_info(dev, hwmon_temp_crit_hyst, 0, &k10temp_out.Tcrit_hyst); |
||
| 9079 | turbocat | 534 | } |
| 535 | |||
| 9100 | turbocat | 536 | int __stdcall service_proc(ioctl_t *my_ctl){ |
| 537 | if(!my_ctl || !my_ctl->output){ |
||
| 538 | return 1; |
||
| 9079 | turbocat | 539 | } |
| 9100 | turbocat | 540 | read_all_info(&k10temp_device); |
| 541 | if(my_ctl->out_size == sizeof(k10temp_out)){ |
||
| 542 | memcpy(my_ctl->output, &k10temp_out, sizeof(k10temp_out)); |
||
| 543 | return 0; |
||
| 544 | } |
||
| 545 | return 1; |
||
| 9079 | turbocat | 546 | } |
| 547 | |||
| 9100 | turbocat | 548 | extern void init_amd_nbs(void); |
| 9079 | turbocat | 549 | |
| 550 | uint32_t drvEntry(int action, char *cmdline){ |
||
| 551 | if(action != 1){ |
||
| 552 | return 0; |
||
| 553 | } |
||
| 9100 | turbocat | 554 | pci_dev_t device; |
| 555 | const struct pci_device_id *k10temp_id; |
||
| 9079 | turbocat | 556 | int err; |
| 557 | |||
| 558 | cpu_detect(&boot_cpu_data); |
||
| 559 | |||
| 560 | err = enum_pci_devices(); |
||
| 561 | if(unlikely(err != 0)) { |
||
| 9100 | turbocat | 562 | printk("k10temp: Device enumeration failed!\n"); |
| 9079 | turbocat | 563 | return -1; |
| 564 | } |
||
| 565 | |||
| 566 | k10temp_id = find_pci_device(&device, k10temp_id_table); |
||
| 9100 | turbocat | 567 | |
| 568 | if(unlikely(k10temp_id == NULL)){ |
||
| 569 | printk("k10temp: Device not found!\n"); |
||
| 9079 | turbocat | 570 | return -ENODEV; |
| 571 | } |
||
| 9100 | turbocat | 572 | |
| 9079 | turbocat | 573 | init_amd_nbs(); |
| 9100 | turbocat | 574 | k10temp_probe(&device.pci_dev, k10temp_id, &k10temp_device); |
| 9079 | turbocat | 575 | return RegService("k10temp", service_proc); |
| 576 | } |