Subversion Repositories Kolibri OS

#       define RADEON_PLL_WR_EN             (1 << 7)

#       define RADEON_PLL_DIV_SEL           (3 << 8)

#       define RADEON_PLL2_DIV_SEL_MASK     ~(3 << 8)

#       define RADEON_FORCEON_MCLKA         (1 << 16)

#       define RADEON_FORCEON_MCLKB         (1 << 17)

#       define RADEON_FORCEON_YCLKA         (1 << 18)

#       define RADEON_FORCEON_YCLKB         (1 << 19)

#       define RADEON_FORCEON_MC            (1 << 20)

#       define RADEON_FORCEON_AIC           (1 << 21)

#       define R300_DISABLE_MC_MCLKA        (1 << 21)

#       define R300_DISABLE_MC_MCLKB        (1 << 21)

{

    u32_t  clock_cntl_index;

    u32_t  mclk_cntl;

    u32_t  rbbm_soft_reset;

    u32_t  host_path_cntl;

    {

	        /* may need something similar for newer chips */

        clock_cntl_index = INREG(RADEON_CLOCK_CNTL_INDEX);

        mclk_cntl = INPLL( RADEON_MCLK_CNTL);

						    RADEON_FORCEON_MCLKA |

						    RADEON_FORCEON_MCLKB |

						    RADEON_FORCEON_YCLKA |

						    RADEON_FORCEON_YCLKB |

						    RADEON_FORCEON_MC |

						    RADEON_FORCEON_AIC));

	}

					      RADEON_SOFT_RESET_CP |

					      RADEON_SOFT_RESET_HI |

					      RADEON_SOFT_RESET_SE |

					      RADEON_SOFT_RESET_RE |

					      RADEON_SOFT_RESET_PP |

					      RADEON_SOFT_RESET_E2 |

					      RADEON_SOFT_RESET_RB));

    INREG(RADEON_RBBM_SOFT_RESET);

    OUTREG(RADEON_RBBM_SOFT_RESET, (rbbm_soft_reset &

					      ~(RADEON_SOFT_RESET_CP |

						RADEON_SOFT_RESET_HI |

						RADEON_SOFT_RESET_SE |

						RADEON_SOFT_RESET_RE |

						RADEON_SOFT_RESET_PP |

						RADEON_SOFT_RESET_E2 |

						RADEON_SOFT_RESET_RB)));

    INREG(RADEON_RBBM_SOFT_RESET);

        OUTPLL(RADEON_MCLK_CNTL, mclk_cntl);

        OUTREG(RADEON_CLOCK_CNTL_INDEX, clock_cntl_index);

        OUTREG(RADEON_RBBM_SOFT_RESET, rbbm_soft_reset);

	}

 };

{

     int i;

        if (required <= (INREG(RADEON_RBBM_STATUS) & RADEON_RBBM_FIFOCNT_MASK))

           return TRUE;

     return FALSE;

}

{

    int i;

    for (i = 0; i < 200; i++)

    {

        if (required <= (INREG(RADEON_RBBM_STATUS) &

                        RADEON_RBBM_FIFOCNT_MASK))

           return ;

        delay(2);

    };

};

 * Flush all dirty data in the Pixel Cache to memory.

 */

R5xx2DFlush()

{

    int i;

                R5XX_DSTCACHE_FLUSH_ALL, R5XX_DSTCACHE_FLUSH_ALL);

        if (!(INREG(R5XX_DSTCACHE_CTLSTAT) & R5XX_DSTCACHE_BUSY))

            return TRUE;

         (unsigned int)INREG(R5XX_DSTCACHE_CTLSTAT));

    return FALSE;

}

R5xx2DIdleLocal()                                //R100-R500

{

    int i;

    for (i = 0; i < R5XX_LOOP_COUNT; i++)

        if (64 == (INREG(R5XX_RBBM_STATUS) & R5XX_RBBM_FIFOCNT_MASK))

            break;

        dbgprintf("%s: FIFO Timeout 0x%08X.\n", __func__,INREG(R5XX_RBBM_STATUS));

        return FALSE;

    }

    for (i = 0; i < R5XX_LOOP_COUNT; i++) {

        if (!(INREG(R5XX_RBBM_STATUS) & R5XX_RBBM_ACTIVE)) {

            R5xx2DFlush();

            return TRUE;

        }

    }

    dbgprintf("%s: Idle Timeout 0x%08X.\n", __func__,INREG(R5XX_RBBM_STATUS));

    return FALSE;

}

R5xx2DSetup()

{

     * set them appropriately before any accel ops, but let's avoid

     * random bogus DMA in case we inadvertently trigger the engine

     * in the wrong place (happened). */

    R5xxFIFOWaitLocal(2);

    OUTREG(R5XX_DST_PITCH_OFFSET,rhd.dst_pitch_offset);

    OUTREG(R5XX_SRC_PITCH_OFFSET,rhd.dst_pitch_offset);

    MASKREG(R5XX_DP_DATATYPE, 0, R5XX_HOST_BIG_ENDIAN_EN);

    OUTREG(R5XX_SC_TOP_LEFT, 0);

    OUTREG(R5XX_SC_BOTTOM_RIGHT,

           RADEON_DEFAULT_SC_RIGHT_MAX | RADEON_DEFAULT_SC_BOTTOM_MAX);

    OUTREG(R5XX_DEFAULT_SC_BOTTOM_RIGHT,

           RADEON_DEFAULT_SC_RIGHT_MAX | RADEON_DEFAULT_SC_BOTTOM_MAX);

//    OUTREG(R5XX_DP_GUI_MASTER_CNTL, rhd.gui_control |

//           R5XX_GMC_BRUSH_SOLID_COLOR | R5XX_GMC_SRC_DATATYPE_COLOR);

    OUTREG(R5XX_DP_CNTL, R5XX_DST_X_LEFT_TO_RIGHT | R5XX_DST_Y_TOP_TO_BOTTOM);

    OUTREG(R5XX_DP_BRUSH_FRGD_CLR, 0xFFFFFFFF);

    OUTREG(R5XX_DP_BRUSH_BKGD_CLR, 0x00000000);

    OUTREG(R5XX_DP_SRC_FRGD_CLR, 0xFFFFFFFF);

    OUTREG(R5XX_DP_SRC_BKGD_CLR, 0x00000000);

    OUTREG(R5XX_DP_WRITE_MASK, 0xFFFFFFFF);

}

{

    if (!R5xxFIFOWaitLocal(required)) {

      radeon_engine_reset(&rhd);

      R5xx2DSetup();

    }

}

{

    if (!R5xx2DIdleLocal()) {

  //    R5xx2DReset();

      R5xx2DSetup();

    }

}

{

    u32_t base;

    int screensize;

    int screenpitch;

    screenpitch = GetScreenPitch();

    rhd.displayHeight = screensize & 0xFFFF;

    rhd.__ymin = 0;

    rhd.__xmax = rhd.displayWidth  - 1;

    rhd.__ymax = rhd.displayHeight - 1;

    clip.ymin = 0;

    clip.xmax = rhd.displayWidth  - 1;

    clip.ymax = rhd.displayHeight - 1;

               rhd.displayWidth, rhd.displayHeight);

                      | RADEON_GMC_CLR_CMP_CNTL_DIS

                      | RADEON_GMC_DST_PITCH_OFFSET_CNTL);

                               (rhd.fbLocation  >> 10));

    scr_pixmap.height = rhd.displayHeight;

    scr_pixmap.format = PICT_a8r8g8b8;

    scr_pixmap.flags  = PX_MEM_LOCAL;

    scr_pixmap.pitch  = rhd.displayWidth * 4     ;//screenpitch;

    scr_pixmap.local  = rhd.fbLocation;

    scr_pixmap.pitch_offset =  rhd.dst_pitch_offset;

    scr_pixmap.mapped = 0;

    OUTREG(R5XX_DST_PITCH_OFFSET,rhd.dst_pitch_offset);

    OUTREG(R5XX_SRC_PITCH_OFFSET,rhd.dst_pitch_offset);

    MASKREG(R5XX_DP_DATATYPE, 0, R5XX_HOST_BIG_ENDIAN_EN);