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5270 | serge | 1 | /* |
2 | * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas. |
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3 | * All Rights Reserved. |
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4 | * |
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5 | * Permission is hereby granted, free of charge, to any person obtaining a |
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6 | * copy of this software and associated documentation files (the |
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7 | * "Software"), to deal in the Software without restriction, including |
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8 | * without limitation the rights to use, copy, modify, merge, publish, |
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9 | * distribute, sub license, and/or sell copies of the Software, and to |
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10 | * permit persons to whom the Software is furnished to do so, subject to |
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11 | * the following conditions: |
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12 | * |
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13 | * The above copyright notice and this permission notice (including the |
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14 | * next paragraph) shall be included in all copies or substantial portions |
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15 | * of the Software. |
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16 | * |
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17 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS |
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18 | * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF |
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19 | * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. |
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20 | * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR |
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21 | * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, |
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22 | * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE |
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23 | * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. |
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24 | * |
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25 | */ |
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26 | |||
27 | #ifndef _UAPI_I915_DRM_H_ |
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28 | #define _UAPI_I915_DRM_H_ |
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29 | |||
30 | #include |
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31 | |||
32 | /* Please note that modifications to all structs defined here are |
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33 | * subject to backwards-compatibility constraints. |
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34 | */ |
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35 | |||
36 | /** |
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37 | * DOC: uevents generated by i915 on it's device node |
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38 | * |
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39 | * I915_L3_PARITY_UEVENT - Generated when the driver receives a parity mismatch |
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40 | * event from the gpu l3 cache. Additional information supplied is ROW, |
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41 | * BANK, SUBBANK, SLICE of the affected cacheline. Userspace should keep |
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42 | * track of these events and if a specific cache-line seems to have a |
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43 | * persistent error remap it with the l3 remapping tool supplied in |
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44 | * intel-gpu-tools. The value supplied with the event is always 1. |
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45 | * |
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46 | * I915_ERROR_UEVENT - Generated upon error detection, currently only via |
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47 | * hangcheck. The error detection event is a good indicator of when things |
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48 | * began to go badly. The value supplied with the event is a 1 upon error |
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49 | * detection, and a 0 upon reset completion, signifying no more error |
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50 | * exists. NOTE: Disabling hangcheck or reset via module parameter will |
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51 | * cause the related events to not be seen. |
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52 | * |
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53 | * I915_RESET_UEVENT - Event is generated just before an attempt to reset the |
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54 | * the GPU. The value supplied with the event is always 1. NOTE: Disable |
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55 | * reset via module parameter will cause this event to not be seen. |
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56 | */ |
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57 | #define I915_L3_PARITY_UEVENT "L3_PARITY_ERROR" |
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58 | #define I915_ERROR_UEVENT "ERROR" |
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59 | #define I915_RESET_UEVENT "RESET" |
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60 | |||
61 | /* Each region is a minimum of 16k, and there are at most 255 of them. |
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62 | */ |
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63 | #define I915_NR_TEX_REGIONS 255 /* table size 2k - maximum due to use |
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64 | * of chars for next/prev indices */ |
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65 | #define I915_LOG_MIN_TEX_REGION_SIZE 14 |
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66 | |||
67 | typedef struct _drm_i915_init { |
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68 | enum { |
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69 | I915_INIT_DMA = 0x01, |
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70 | I915_CLEANUP_DMA = 0x02, |
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71 | I915_RESUME_DMA = 0x03 |
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72 | } func; |
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73 | unsigned int mmio_offset; |
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74 | int sarea_priv_offset; |
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75 | unsigned int ring_start; |
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76 | unsigned int ring_end; |
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77 | unsigned int ring_size; |
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78 | unsigned int front_offset; |
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79 | unsigned int back_offset; |
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80 | unsigned int depth_offset; |
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81 | unsigned int w; |
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82 | unsigned int h; |
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83 | unsigned int pitch; |
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84 | unsigned int pitch_bits; |
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85 | unsigned int back_pitch; |
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86 | unsigned int depth_pitch; |
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87 | unsigned int cpp; |
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88 | unsigned int chipset; |
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89 | } drm_i915_init_t; |
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90 | |||
91 | typedef struct _drm_i915_sarea { |
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92 | struct drm_tex_region texList[I915_NR_TEX_REGIONS + 1]; |
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93 | int last_upload; /* last time texture was uploaded */ |
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94 | int last_enqueue; /* last time a buffer was enqueued */ |
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95 | int last_dispatch; /* age of the most recently dispatched buffer */ |
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96 | int ctxOwner; /* last context to upload state */ |
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97 | int texAge; |
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98 | int pf_enabled; /* is pageflipping allowed? */ |
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99 | int pf_active; |
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100 | int pf_current_page; /* which buffer is being displayed? */ |
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101 | int perf_boxes; /* performance boxes to be displayed */ |
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102 | int width, height; /* screen size in pixels */ |
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103 | |||
104 | drm_handle_t front_handle; |
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105 | int front_offset; |
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106 | int front_size; |
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107 | |||
108 | drm_handle_t back_handle; |
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109 | int back_offset; |
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110 | int back_size; |
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111 | |||
112 | drm_handle_t depth_handle; |
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113 | int depth_offset; |
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114 | int depth_size; |
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115 | |||
116 | drm_handle_t tex_handle; |
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117 | int tex_offset; |
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118 | int tex_size; |
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119 | int log_tex_granularity; |
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120 | int pitch; |
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121 | int rotation; /* 0, 90, 180 or 270 */ |
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122 | int rotated_offset; |
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123 | int rotated_size; |
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124 | int rotated_pitch; |
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125 | int virtualX, virtualY; |
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126 | |||
127 | unsigned int front_tiled; |
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128 | unsigned int back_tiled; |
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129 | unsigned int depth_tiled; |
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130 | unsigned int rotated_tiled; |
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131 | unsigned int rotated2_tiled; |
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132 | |||
133 | int pipeA_x; |
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134 | int pipeA_y; |
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135 | int pipeA_w; |
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136 | int pipeA_h; |
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137 | int pipeB_x; |
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138 | int pipeB_y; |
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139 | int pipeB_w; |
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140 | int pipeB_h; |
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141 | |||
142 | /* fill out some space for old userspace triple buffer */ |
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143 | drm_handle_t unused_handle; |
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144 | __u32 unused1, unused2, unused3; |
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145 | |||
146 | /* buffer object handles for static buffers. May change |
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147 | * over the lifetime of the client. |
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148 | */ |
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149 | __u32 front_bo_handle; |
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150 | __u32 back_bo_handle; |
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151 | __u32 unused_bo_handle; |
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152 | __u32 depth_bo_handle; |
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153 | |||
154 | } drm_i915_sarea_t; |
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155 | |||
156 | /* due to userspace building against these headers we need some compat here */ |
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157 | #define planeA_x pipeA_x |
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158 | #define planeA_y pipeA_y |
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159 | #define planeA_w pipeA_w |
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160 | #define planeA_h pipeA_h |
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161 | #define planeB_x pipeB_x |
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162 | #define planeB_y pipeB_y |
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163 | #define planeB_w pipeB_w |
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164 | #define planeB_h pipeB_h |
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165 | |||
166 | /* Flags for perf_boxes |
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167 | */ |
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168 | #define I915_BOX_RING_EMPTY 0x1 |
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169 | #define I915_BOX_FLIP 0x2 |
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170 | #define I915_BOX_WAIT 0x4 |
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171 | #define I915_BOX_TEXTURE_LOAD 0x8 |
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172 | #define I915_BOX_LOST_CONTEXT 0x10 |
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173 | |||
6082 | serge | 174 | /* |
175 | * i915 specific ioctls. |
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176 | * |
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177 | * The device specific ioctl range is [DRM_COMMAND_BASE, DRM_COMMAND_END) ie |
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178 | * [0x40, 0xa0) (a0 is excluded). The numbers below are defined as offset |
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179 | * against DRM_COMMAND_BASE and should be between [0x0, 0x60). |
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5270 | serge | 180 | */ |
181 | #define DRM_I915_INIT 0x00 |
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182 | #define DRM_I915_FLUSH 0x01 |
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183 | #define DRM_I915_FLIP 0x02 |
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184 | #define DRM_I915_BATCHBUFFER 0x03 |
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185 | #define DRM_I915_IRQ_EMIT 0x04 |
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186 | #define DRM_I915_IRQ_WAIT 0x05 |
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187 | #define DRM_I915_GETPARAM 0x06 |
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188 | #define DRM_I915_SETPARAM 0x07 |
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189 | #define DRM_I915_ALLOC 0x08 |
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190 | #define DRM_I915_FREE 0x09 |
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191 | #define DRM_I915_INIT_HEAP 0x0a |
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192 | #define DRM_I915_CMDBUFFER 0x0b |
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193 | #define DRM_I915_DESTROY_HEAP 0x0c |
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194 | #define DRM_I915_SET_VBLANK_PIPE 0x0d |
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195 | #define DRM_I915_GET_VBLANK_PIPE 0x0e |
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196 | #define DRM_I915_VBLANK_SWAP 0x0f |
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197 | #define DRM_I915_HWS_ADDR 0x11 |
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198 | #define DRM_I915_GEM_INIT 0x13 |
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199 | #define DRM_I915_GEM_EXECBUFFER 0x14 |
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200 | #define DRM_I915_GEM_PIN 0x15 |
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201 | #define DRM_I915_GEM_UNPIN 0x16 |
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202 | #define DRM_I915_GEM_BUSY 0x17 |
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203 | #define DRM_I915_GEM_THROTTLE 0x18 |
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204 | #define DRM_I915_GEM_ENTERVT 0x19 |
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205 | #define DRM_I915_GEM_LEAVEVT 0x1a |
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206 | #define DRM_I915_GEM_CREATE 0x1b |
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207 | #define DRM_I915_GEM_PREAD 0x1c |
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208 | #define DRM_I915_GEM_PWRITE 0x1d |
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209 | #define DRM_I915_GEM_MMAP 0x1e |
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210 | #define DRM_I915_GEM_SET_DOMAIN 0x1f |
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211 | #define DRM_I915_GEM_SW_FINISH 0x20 |
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212 | #define DRM_I915_GEM_SET_TILING 0x21 |
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213 | #define DRM_I915_GEM_GET_TILING 0x22 |
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214 | #define DRM_I915_GEM_GET_APERTURE 0x23 |
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215 | #define DRM_I915_GEM_MMAP_GTT 0x24 |
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216 | #define DRM_I915_GET_PIPE_FROM_CRTC_ID 0x25 |
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217 | #define DRM_I915_GEM_MADVISE 0x26 |
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218 | #define DRM_I915_OVERLAY_PUT_IMAGE 0x27 |
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219 | #define DRM_I915_OVERLAY_ATTRS 0x28 |
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220 | #define DRM_I915_GEM_EXECBUFFER2 0x29 |
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221 | #define DRM_I915_GET_SPRITE_COLORKEY 0x2a |
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222 | #define DRM_I915_SET_SPRITE_COLORKEY 0x2b |
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223 | #define DRM_I915_GEM_WAIT 0x2c |
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224 | #define DRM_I915_GEM_CONTEXT_CREATE 0x2d |
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225 | #define DRM_I915_GEM_CONTEXT_DESTROY 0x2e |
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226 | #define DRM_I915_GEM_SET_CACHING 0x2f |
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227 | #define DRM_I915_GEM_GET_CACHING 0x30 |
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228 | #define DRM_I915_REG_READ 0x31 |
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229 | #define DRM_I915_GET_RESET_STATS 0x32 |
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230 | #define DRM_I915_GEM_USERPTR 0x33 |
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6082 | serge | 231 | #define DRM_I915_GEM_CONTEXT_GETPARAM 0x34 |
232 | #define DRM_I915_GEM_CONTEXT_SETPARAM 0x35 |
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5270 | serge | 233 | |
234 | #define DRM_IOCTL_I915_INIT DRM_IOW( DRM_COMMAND_BASE + DRM_I915_INIT, drm_i915_init_t) |
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235 | #define DRM_IOCTL_I915_FLUSH DRM_IO ( DRM_COMMAND_BASE + DRM_I915_FLUSH) |
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236 | #define DRM_IOCTL_I915_FLIP DRM_IO ( DRM_COMMAND_BASE + DRM_I915_FLIP) |
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237 | #define DRM_IOCTL_I915_BATCHBUFFER DRM_IOW( DRM_COMMAND_BASE + DRM_I915_BATCHBUFFER, drm_i915_batchbuffer_t) |
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238 | #define DRM_IOCTL_I915_IRQ_EMIT DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_IRQ_EMIT, drm_i915_irq_emit_t) |
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239 | #define DRM_IOCTL_I915_IRQ_WAIT DRM_IOW( DRM_COMMAND_BASE + DRM_I915_IRQ_WAIT, drm_i915_irq_wait_t) |
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240 | #define DRM_IOCTL_I915_GETPARAM DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GETPARAM, drm_i915_getparam_t) |
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241 | #define DRM_IOCTL_I915_SETPARAM DRM_IOW( DRM_COMMAND_BASE + DRM_I915_SETPARAM, drm_i915_setparam_t) |
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242 | #define DRM_IOCTL_I915_ALLOC DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_ALLOC, drm_i915_mem_alloc_t) |
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243 | #define DRM_IOCTL_I915_FREE DRM_IOW( DRM_COMMAND_BASE + DRM_I915_FREE, drm_i915_mem_free_t) |
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244 | #define DRM_IOCTL_I915_INIT_HEAP DRM_IOW( DRM_COMMAND_BASE + DRM_I915_INIT_HEAP, drm_i915_mem_init_heap_t) |
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245 | #define DRM_IOCTL_I915_CMDBUFFER DRM_IOW( DRM_COMMAND_BASE + DRM_I915_CMDBUFFER, drm_i915_cmdbuffer_t) |
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246 | #define DRM_IOCTL_I915_DESTROY_HEAP DRM_IOW( DRM_COMMAND_BASE + DRM_I915_DESTROY_HEAP, drm_i915_mem_destroy_heap_t) |
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247 | #define DRM_IOCTL_I915_SET_VBLANK_PIPE DRM_IOW( DRM_COMMAND_BASE + DRM_I915_SET_VBLANK_PIPE, drm_i915_vblank_pipe_t) |
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248 | #define DRM_IOCTL_I915_GET_VBLANK_PIPE DRM_IOR( DRM_COMMAND_BASE + DRM_I915_GET_VBLANK_PIPE, drm_i915_vblank_pipe_t) |
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249 | #define DRM_IOCTL_I915_VBLANK_SWAP DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_VBLANK_SWAP, drm_i915_vblank_swap_t) |
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250 | #define DRM_IOCTL_I915_HWS_ADDR DRM_IOW(DRM_COMMAND_BASE + DRM_I915_HWS_ADDR, struct drm_i915_gem_init) |
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251 | #define DRM_IOCTL_I915_GEM_INIT DRM_IOW(DRM_COMMAND_BASE + DRM_I915_GEM_INIT, struct drm_i915_gem_init) |
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252 | #define DRM_IOCTL_I915_GEM_EXECBUFFER DRM_IOW(DRM_COMMAND_BASE + DRM_I915_GEM_EXECBUFFER, struct drm_i915_gem_execbuffer) |
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253 | #define DRM_IOCTL_I915_GEM_EXECBUFFER2 DRM_IOW(DRM_COMMAND_BASE + DRM_I915_GEM_EXECBUFFER2, struct drm_i915_gem_execbuffer2) |
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254 | #define DRM_IOCTL_I915_GEM_PIN DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_PIN, struct drm_i915_gem_pin) |
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255 | #define DRM_IOCTL_I915_GEM_UNPIN DRM_IOW(DRM_COMMAND_BASE + DRM_I915_GEM_UNPIN, struct drm_i915_gem_unpin) |
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256 | #define DRM_IOCTL_I915_GEM_BUSY DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_BUSY, struct drm_i915_gem_busy) |
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257 | #define DRM_IOCTL_I915_GEM_SET_CACHING DRM_IOW(DRM_COMMAND_BASE + DRM_I915_GEM_SET_CACHING, struct drm_i915_gem_caching) |
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258 | #define DRM_IOCTL_I915_GEM_GET_CACHING DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_GET_CACHING, struct drm_i915_gem_caching) |
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259 | #define DRM_IOCTL_I915_GEM_THROTTLE DRM_IO ( DRM_COMMAND_BASE + DRM_I915_GEM_THROTTLE) |
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260 | #define DRM_IOCTL_I915_GEM_ENTERVT DRM_IO(DRM_COMMAND_BASE + DRM_I915_GEM_ENTERVT) |
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261 | #define DRM_IOCTL_I915_GEM_LEAVEVT DRM_IO(DRM_COMMAND_BASE + DRM_I915_GEM_LEAVEVT) |
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262 | #define DRM_IOCTL_I915_GEM_CREATE DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_CREATE, struct drm_i915_gem_create) |
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263 | #define DRM_IOCTL_I915_GEM_PREAD DRM_IOW (DRM_COMMAND_BASE + DRM_I915_GEM_PREAD, struct drm_i915_gem_pread) |
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264 | #define DRM_IOCTL_I915_GEM_PWRITE DRM_IOW (DRM_COMMAND_BASE + DRM_I915_GEM_PWRITE, struct drm_i915_gem_pwrite) |
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265 | #define DRM_IOCTL_I915_GEM_MMAP DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_MMAP, struct drm_i915_gem_mmap) |
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266 | #define DRM_IOCTL_I915_GEM_MMAP_GTT DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_MMAP_GTT, struct drm_i915_gem_mmap_gtt) |
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267 | #define DRM_IOCTL_I915_GEM_SET_DOMAIN DRM_IOW (DRM_COMMAND_BASE + DRM_I915_GEM_SET_DOMAIN, struct drm_i915_gem_set_domain) |
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268 | #define DRM_IOCTL_I915_GEM_SW_FINISH DRM_IOW (DRM_COMMAND_BASE + DRM_I915_GEM_SW_FINISH, struct drm_i915_gem_sw_finish) |
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269 | #define DRM_IOCTL_I915_GEM_SET_TILING DRM_IOWR (DRM_COMMAND_BASE + DRM_I915_GEM_SET_TILING, struct drm_i915_gem_set_tiling) |
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270 | #define DRM_IOCTL_I915_GEM_GET_TILING DRM_IOWR (DRM_COMMAND_BASE + DRM_I915_GEM_GET_TILING, struct drm_i915_gem_get_tiling) |
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271 | #define DRM_IOCTL_I915_GEM_GET_APERTURE DRM_IOR (DRM_COMMAND_BASE + DRM_I915_GEM_GET_APERTURE, struct drm_i915_gem_get_aperture) |
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272 | #define DRM_IOCTL_I915_GET_PIPE_FROM_CRTC_ID DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GET_PIPE_FROM_CRTC_ID, struct drm_i915_get_pipe_from_crtc_id) |
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273 | #define DRM_IOCTL_I915_GEM_MADVISE DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_MADVISE, struct drm_i915_gem_madvise) |
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274 | #define DRM_IOCTL_I915_OVERLAY_PUT_IMAGE DRM_IOW(DRM_COMMAND_BASE + DRM_I915_OVERLAY_PUT_IMAGE, struct drm_intel_overlay_put_image) |
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275 | #define DRM_IOCTL_I915_OVERLAY_ATTRS DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_OVERLAY_ATTRS, struct drm_intel_overlay_attrs) |
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276 | #define DRM_IOCTL_I915_SET_SPRITE_COLORKEY DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_SET_SPRITE_COLORKEY, struct drm_intel_sprite_colorkey) |
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6082 | serge | 277 | #define DRM_IOCTL_I915_GET_SPRITE_COLORKEY DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GET_SPRITE_COLORKEY, struct drm_intel_sprite_colorkey) |
5270 | serge | 278 | #define DRM_IOCTL_I915_GEM_WAIT DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_WAIT, struct drm_i915_gem_wait) |
279 | #define DRM_IOCTL_I915_GEM_CONTEXT_CREATE DRM_IOWR (DRM_COMMAND_BASE + DRM_I915_GEM_CONTEXT_CREATE, struct drm_i915_gem_context_create) |
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280 | #define DRM_IOCTL_I915_GEM_CONTEXT_DESTROY DRM_IOW (DRM_COMMAND_BASE + DRM_I915_GEM_CONTEXT_DESTROY, struct drm_i915_gem_context_destroy) |
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281 | #define DRM_IOCTL_I915_REG_READ DRM_IOWR (DRM_COMMAND_BASE + DRM_I915_REG_READ, struct drm_i915_reg_read) |
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282 | #define DRM_IOCTL_I915_GET_RESET_STATS DRM_IOWR (DRM_COMMAND_BASE + DRM_I915_GET_RESET_STATS, struct drm_i915_reset_stats) |
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283 | #define DRM_IOCTL_I915_GEM_USERPTR DRM_IOWR (DRM_COMMAND_BASE + DRM_I915_GEM_USERPTR, struct drm_i915_gem_userptr) |
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6082 | serge | 284 | #define DRM_IOCTL_I915_GEM_CONTEXT_GETPARAM DRM_IOWR (DRM_COMMAND_BASE + DRM_I915_GEM_CONTEXT_GETPARAM, struct drm_i915_gem_context_param) |
285 | #define DRM_IOCTL_I915_GEM_CONTEXT_SETPARAM DRM_IOWR (DRM_COMMAND_BASE + DRM_I915_GEM_CONTEXT_SETPARAM, struct drm_i915_gem_context_param) |
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5270 | serge | 286 | |
287 | /* Allow drivers to submit batchbuffers directly to hardware, relying |
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288 | * on the security mechanisms provided by hardware. |
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289 | */ |
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290 | typedef struct drm_i915_batchbuffer { |
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291 | int start; /* agp offset */ |
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292 | int used; /* nr bytes in use */ |
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293 | int DR1; /* hw flags for GFX_OP_DRAWRECT_INFO */ |
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294 | int DR4; /* window origin for GFX_OP_DRAWRECT_INFO */ |
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295 | int num_cliprects; /* mulitpass with multiple cliprects? */ |
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296 | struct drm_clip_rect __user *cliprects; /* pointer to userspace cliprects */ |
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297 | } drm_i915_batchbuffer_t; |
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298 | |||
299 | /* As above, but pass a pointer to userspace buffer which can be |
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300 | * validated by the kernel prior to sending to hardware. |
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301 | */ |
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302 | typedef struct _drm_i915_cmdbuffer { |
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303 | char __user *buf; /* pointer to userspace command buffer */ |
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304 | int sz; /* nr bytes in buf */ |
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305 | int DR1; /* hw flags for GFX_OP_DRAWRECT_INFO */ |
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306 | int DR4; /* window origin for GFX_OP_DRAWRECT_INFO */ |
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307 | int num_cliprects; /* mulitpass with multiple cliprects? */ |
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308 | struct drm_clip_rect __user *cliprects; /* pointer to userspace cliprects */ |
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309 | } drm_i915_cmdbuffer_t; |
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310 | |||
311 | /* Userspace can request & wait on irq's: |
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312 | */ |
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313 | typedef struct drm_i915_irq_emit { |
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314 | int __user *irq_seq; |
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315 | } drm_i915_irq_emit_t; |
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316 | |||
317 | typedef struct drm_i915_irq_wait { |
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318 | int irq_seq; |
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319 | } drm_i915_irq_wait_t; |
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320 | |||
321 | /* Ioctl to query kernel params: |
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322 | */ |
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323 | #define I915_PARAM_IRQ_ACTIVE 1 |
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324 | #define I915_PARAM_ALLOW_BATCHBUFFER 2 |
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325 | #define I915_PARAM_LAST_DISPATCH 3 |
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326 | #define I915_PARAM_CHIPSET_ID 4 |
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327 | #define I915_PARAM_HAS_GEM 5 |
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328 | #define I915_PARAM_NUM_FENCES_AVAIL 6 |
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329 | #define I915_PARAM_HAS_OVERLAY 7 |
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330 | #define I915_PARAM_HAS_PAGEFLIPPING 8 |
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331 | #define I915_PARAM_HAS_EXECBUF2 9 |
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332 | #define I915_PARAM_HAS_BSD 10 |
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333 | #define I915_PARAM_HAS_BLT 11 |
||
334 | #define I915_PARAM_HAS_RELAXED_FENCING 12 |
||
335 | #define I915_PARAM_HAS_COHERENT_RINGS 13 |
||
336 | #define I915_PARAM_HAS_EXEC_CONSTANTS 14 |
||
337 | #define I915_PARAM_HAS_RELAXED_DELTA 15 |
||
338 | #define I915_PARAM_HAS_GEN7_SOL_RESET 16 |
||
339 | #define I915_PARAM_HAS_LLC 17 |
||
340 | #define I915_PARAM_HAS_ALIASING_PPGTT 18 |
||
341 | #define I915_PARAM_HAS_WAIT_TIMEOUT 19 |
||
342 | #define I915_PARAM_HAS_SEMAPHORES 20 |
||
343 | #define I915_PARAM_HAS_PRIME_VMAP_FLUSH 21 |
||
344 | #define I915_PARAM_HAS_VEBOX 22 |
||
345 | #define I915_PARAM_HAS_SECURE_BATCHES 23 |
||
346 | #define I915_PARAM_HAS_PINNED_BATCHES 24 |
||
347 | #define I915_PARAM_HAS_EXEC_NO_RELOC 25 |
||
348 | #define I915_PARAM_HAS_EXEC_HANDLE_LUT 26 |
||
349 | #define I915_PARAM_HAS_WT 27 |
||
350 | #define I915_PARAM_CMD_PARSER_VERSION 28 |
||
351 | #define I915_PARAM_HAS_COHERENT_PHYS_GTT 29 |
||
6082 | serge | 352 | #define I915_PARAM_MMAP_VERSION 30 |
353 | #define I915_PARAM_HAS_BSD2 31 |
||
354 | #define I915_PARAM_REVISION 32 |
||
355 | #define I915_PARAM_SUBSLICE_TOTAL 33 |
||
356 | #define I915_PARAM_EU_TOTAL 34 |
||
357 | #define I915_PARAM_HAS_GPU_RESET 35 |
||
358 | #define I915_PARAM_HAS_RESOURCE_STREAMER 36 |
||
5270 | serge | 359 | |
360 | typedef struct drm_i915_getparam { |
||
6082 | serge | 361 | __s32 param; |
362 | /* |
||
363 | * WARNING: Using pointers instead of fixed-size u64 means we need to write |
||
364 | * compat32 code. Don't repeat this mistake. |
||
365 | */ |
||
5270 | serge | 366 | int __user *value; |
367 | } drm_i915_getparam_t; |
||
368 | |||
369 | /* Ioctl to set kernel params: |
||
370 | */ |
||
371 | #define I915_SETPARAM_USE_MI_BATCHBUFFER_START 1 |
||
372 | #define I915_SETPARAM_TEX_LRU_LOG_GRANULARITY 2 |
||
373 | #define I915_SETPARAM_ALLOW_BATCHBUFFER 3 |
||
374 | #define I915_SETPARAM_NUM_USED_FENCES 4 |
||
375 | |||
376 | typedef struct drm_i915_setparam { |
||
377 | int param; |
||
378 | int value; |
||
379 | } drm_i915_setparam_t; |
||
380 | |||
381 | /* A memory manager for regions of shared memory: |
||
382 | */ |
||
383 | #define I915_MEM_REGION_AGP 1 |
||
384 | |||
385 | typedef struct drm_i915_mem_alloc { |
||
386 | int region; |
||
387 | int alignment; |
||
388 | int size; |
||
389 | int __user *region_offset; /* offset from start of fb or agp */ |
||
390 | } drm_i915_mem_alloc_t; |
||
391 | |||
392 | typedef struct drm_i915_mem_free { |
||
393 | int region; |
||
394 | int region_offset; |
||
395 | } drm_i915_mem_free_t; |
||
396 | |||
397 | typedef struct drm_i915_mem_init_heap { |
||
398 | int region; |
||
399 | int size; |
||
400 | int start; |
||
401 | } drm_i915_mem_init_heap_t; |
||
402 | |||
403 | /* Allow memory manager to be torn down and re-initialized (eg on |
||
404 | * rotate): |
||
405 | */ |
||
406 | typedef struct drm_i915_mem_destroy_heap { |
||
407 | int region; |
||
408 | } drm_i915_mem_destroy_heap_t; |
||
409 | |||
410 | /* Allow X server to configure which pipes to monitor for vblank signals |
||
411 | */ |
||
412 | #define DRM_I915_VBLANK_PIPE_A 1 |
||
413 | #define DRM_I915_VBLANK_PIPE_B 2 |
||
414 | |||
415 | typedef struct drm_i915_vblank_pipe { |
||
416 | int pipe; |
||
417 | } drm_i915_vblank_pipe_t; |
||
418 | |||
419 | /* Schedule buffer swap at given vertical blank: |
||
420 | */ |
||
421 | typedef struct drm_i915_vblank_swap { |
||
422 | drm_drawable_t drawable; |
||
423 | enum drm_vblank_seq_type seqtype; |
||
424 | unsigned int sequence; |
||
425 | } drm_i915_vblank_swap_t; |
||
426 | |||
427 | typedef struct drm_i915_hws_addr { |
||
428 | __u64 addr; |
||
429 | } drm_i915_hws_addr_t; |
||
430 | |||
431 | struct drm_i915_gem_init { |
||
432 | /** |
||
433 | * Beginning offset in the GTT to be managed by the DRM memory |
||
434 | * manager. |
||
435 | */ |
||
436 | __u64 gtt_start; |
||
437 | /** |
||
438 | * Ending offset in the GTT to be managed by the DRM memory |
||
439 | * manager. |
||
440 | */ |
||
441 | __u64 gtt_end; |
||
442 | }; |
||
443 | |||
444 | struct drm_i915_gem_create { |
||
445 | /** |
||
446 | * Requested size for the object. |
||
447 | * |
||
448 | * The (page-aligned) allocated size for the object will be returned. |
||
449 | */ |
||
450 | __u64 size; |
||
451 | /** |
||
452 | * Returned handle for the object. |
||
453 | * |
||
454 | * Object handles are nonzero. |
||
455 | */ |
||
456 | __u32 handle; |
||
457 | __u32 pad; |
||
458 | }; |
||
459 | |||
460 | struct drm_i915_gem_pread { |
||
461 | /** Handle for the object being read. */ |
||
462 | __u32 handle; |
||
463 | __u32 pad; |
||
464 | /** Offset into the object to read from */ |
||
465 | __u64 offset; |
||
466 | /** Length of data to read */ |
||
467 | __u64 size; |
||
468 | /** |
||
469 | * Pointer to write the data into. |
||
470 | * |
||
471 | * This is a fixed-size type for 32/64 compatibility. |
||
472 | */ |
||
473 | __u64 data_ptr; |
||
474 | }; |
||
475 | |||
476 | struct drm_i915_gem_pwrite { |
||
477 | /** Handle for the object being written to. */ |
||
478 | __u32 handle; |
||
479 | __u32 pad; |
||
480 | /** Offset into the object to write to */ |
||
481 | __u64 offset; |
||
482 | /** Length of data to write */ |
||
483 | __u64 size; |
||
484 | /** |
||
485 | * Pointer to read the data from. |
||
486 | * |
||
487 | * This is a fixed-size type for 32/64 compatibility. |
||
488 | */ |
||
489 | __u64 data_ptr; |
||
490 | }; |
||
491 | |||
492 | struct drm_i915_gem_mmap { |
||
493 | /** Handle for the object being mapped. */ |
||
494 | __u32 handle; |
||
495 | __u32 pad; |
||
496 | /** Offset in the object to map. */ |
||
497 | __u64 offset; |
||
498 | /** |
||
499 | * Length of data to map. |
||
500 | * |
||
501 | * The value will be page-aligned. |
||
502 | */ |
||
503 | __u64 size; |
||
504 | /** |
||
505 | * Returned pointer the data was mapped at. |
||
506 | * |
||
507 | * This is a fixed-size type for 32/64 compatibility. |
||
508 | */ |
||
509 | __u64 addr_ptr; |
||
6082 | serge | 510 | |
511 | /** |
||
512 | * Flags for extended behaviour. |
||
513 | * |
||
514 | * Added in version 2. |
||
515 | */ |
||
516 | __u64 flags; |
||
517 | #define I915_MMAP_WC 0x1 |
||
5270 | serge | 518 | }; |
519 | |||
520 | struct drm_i915_gem_mmap_gtt { |
||
521 | /** Handle for the object being mapped. */ |
||
522 | __u32 handle; |
||
523 | __u32 pad; |
||
524 | /** |
||
525 | * Fake offset to use for subsequent mmap call |
||
526 | * |
||
527 | * This is a fixed-size type for 32/64 compatibility. |
||
528 | */ |
||
529 | __u64 offset; |
||
530 | }; |
||
531 | |||
532 | struct drm_i915_gem_set_domain { |
||
533 | /** Handle for the object */ |
||
534 | __u32 handle; |
||
535 | |||
536 | /** New read domains */ |
||
537 | __u32 read_domains; |
||
538 | |||
539 | /** New write domain */ |
||
540 | __u32 write_domain; |
||
541 | }; |
||
542 | |||
543 | struct drm_i915_gem_sw_finish { |
||
544 | /** Handle for the object */ |
||
545 | __u32 handle; |
||
546 | }; |
||
547 | |||
548 | struct drm_i915_gem_relocation_entry { |
||
549 | /** |
||
550 | * Handle of the buffer being pointed to by this relocation entry. |
||
551 | * |
||
552 | * It's appealing to make this be an index into the mm_validate_entry |
||
553 | * list to refer to the buffer, but this allows the driver to create |
||
554 | * a relocation list for state buffers and not re-write it per |
||
555 | * exec using the buffer. |
||
556 | */ |
||
557 | __u32 target_handle; |
||
558 | |||
559 | /** |
||
560 | * Value to be added to the offset of the target buffer to make up |
||
561 | * the relocation entry. |
||
562 | */ |
||
563 | __u32 delta; |
||
564 | |||
565 | /** Offset in the buffer the relocation entry will be written into */ |
||
566 | __u64 offset; |
||
567 | |||
568 | /** |
||
569 | * Offset value of the target buffer that the relocation entry was last |
||
570 | * written as. |
||
571 | * |
||
572 | * If the buffer has the same offset as last time, we can skip syncing |
||
573 | * and writing the relocation. This value is written back out by |
||
574 | * the execbuffer ioctl when the relocation is written. |
||
575 | */ |
||
576 | __u64 presumed_offset; |
||
577 | |||
578 | /** |
||
579 | * Target memory domains read by this operation. |
||
580 | */ |
||
581 | __u32 read_domains; |
||
582 | |||
583 | /** |
||
584 | * Target memory domains written by this operation. |
||
585 | * |
||
586 | * Note that only one domain may be written by the whole |
||
587 | * execbuffer operation, so that where there are conflicts, |
||
588 | * the application will get -EINVAL back. |
||
589 | */ |
||
590 | __u32 write_domain; |
||
591 | }; |
||
592 | |||
593 | /** @{ |
||
594 | * Intel memory domains |
||
595 | * |
||
596 | * Most of these just align with the various caches in |
||
597 | * the system and are used to flush and invalidate as |
||
598 | * objects end up cached in different domains. |
||
599 | */ |
||
600 | /** CPU cache */ |
||
601 | #define I915_GEM_DOMAIN_CPU 0x00000001 |
||
602 | /** Render cache, used by 2D and 3D drawing */ |
||
603 | #define I915_GEM_DOMAIN_RENDER 0x00000002 |
||
604 | /** Sampler cache, used by texture engine */ |
||
605 | #define I915_GEM_DOMAIN_SAMPLER 0x00000004 |
||
606 | /** Command queue, used to load batch buffers */ |
||
607 | #define I915_GEM_DOMAIN_COMMAND 0x00000008 |
||
608 | /** Instruction cache, used by shader programs */ |
||
609 | #define I915_GEM_DOMAIN_INSTRUCTION 0x00000010 |
||
610 | /** Vertex address cache */ |
||
611 | #define I915_GEM_DOMAIN_VERTEX 0x00000020 |
||
612 | /** GTT domain - aperture and scanout */ |
||
613 | #define I915_GEM_DOMAIN_GTT 0x00000040 |
||
614 | /** @} */ |
||
615 | |||
616 | struct drm_i915_gem_exec_object { |
||
617 | /** |
||
618 | * User's handle for a buffer to be bound into the GTT for this |
||
619 | * operation. |
||
620 | */ |
||
621 | __u32 handle; |
||
622 | |||
623 | /** Number of relocations to be performed on this buffer */ |
||
624 | __u32 relocation_count; |
||
625 | /** |
||
626 | * Pointer to array of struct drm_i915_gem_relocation_entry containing |
||
627 | * the relocations to be performed in this buffer. |
||
628 | */ |
||
629 | __u64 relocs_ptr; |
||
630 | |||
631 | /** Required alignment in graphics aperture */ |
||
632 | __u64 alignment; |
||
633 | |||
634 | /** |
||
635 | * Returned value of the updated offset of the object, for future |
||
636 | * presumed_offset writes. |
||
637 | */ |
||
638 | __u64 offset; |
||
639 | }; |
||
640 | |||
641 | struct drm_i915_gem_execbuffer { |
||
642 | /** |
||
643 | * List of buffers to be validated with their relocations to be |
||
644 | * performend on them. |
||
645 | * |
||
646 | * This is a pointer to an array of struct drm_i915_gem_validate_entry. |
||
647 | * |
||
648 | * These buffers must be listed in an order such that all relocations |
||
649 | * a buffer is performing refer to buffers that have already appeared |
||
650 | * in the validate list. |
||
651 | */ |
||
652 | __u64 buffers_ptr; |
||
653 | __u32 buffer_count; |
||
654 | |||
655 | /** Offset in the batchbuffer to start execution from. */ |
||
656 | __u32 batch_start_offset; |
||
657 | /** Bytes used in batchbuffer from batch_start_offset */ |
||
658 | __u32 batch_len; |
||
659 | __u32 DR1; |
||
660 | __u32 DR4; |
||
661 | __u32 num_cliprects; |
||
662 | /** This is a struct drm_clip_rect *cliprects */ |
||
663 | __u64 cliprects_ptr; |
||
664 | }; |
||
665 | |||
666 | struct drm_i915_gem_exec_object2 { |
||
667 | /** |
||
668 | * User's handle for a buffer to be bound into the GTT for this |
||
669 | * operation. |
||
670 | */ |
||
671 | __u32 handle; |
||
672 | |||
673 | /** Number of relocations to be performed on this buffer */ |
||
674 | __u32 relocation_count; |
||
675 | /** |
||
676 | * Pointer to array of struct drm_i915_gem_relocation_entry containing |
||
677 | * the relocations to be performed in this buffer. |
||
678 | */ |
||
679 | __u64 relocs_ptr; |
||
680 | |||
681 | /** Required alignment in graphics aperture */ |
||
682 | __u64 alignment; |
||
683 | |||
684 | /** |
||
685 | * Returned value of the updated offset of the object, for future |
||
686 | * presumed_offset writes. |
||
687 | */ |
||
688 | __u64 offset; |
||
689 | |||
690 | #define EXEC_OBJECT_NEEDS_FENCE (1<<0) |
||
691 | #define EXEC_OBJECT_NEEDS_GTT (1<<1) |
||
692 | #define EXEC_OBJECT_WRITE (1<<2) |
||
6082 | serge | 693 | #define EXEC_OBJECT_SUPPORTS_48B_ADDRESS (1<<3) |
694 | #define __EXEC_OBJECT_UNKNOWN_FLAGS -(EXEC_OBJECT_SUPPORTS_48B_ADDRESS<<1) |
||
5270 | serge | 695 | __u64 flags; |
696 | |||
697 | __u64 rsvd1; |
||
698 | __u64 rsvd2; |
||
699 | }; |
||
700 | |||
701 | struct drm_i915_gem_execbuffer2 { |
||
702 | /** |
||
703 | * List of gem_exec_object2 structs |
||
704 | */ |
||
705 | __u64 buffers_ptr; |
||
706 | __u32 buffer_count; |
||
707 | |||
708 | /** Offset in the batchbuffer to start execution from. */ |
||
709 | __u32 batch_start_offset; |
||
710 | /** Bytes used in batchbuffer from batch_start_offset */ |
||
711 | __u32 batch_len; |
||
712 | __u32 DR1; |
||
713 | __u32 DR4; |
||
714 | __u32 num_cliprects; |
||
715 | /** This is a struct drm_clip_rect *cliprects */ |
||
716 | __u64 cliprects_ptr; |
||
717 | #define I915_EXEC_RING_MASK (7<<0) |
||
718 | #define I915_EXEC_DEFAULT (0<<0) |
||
719 | #define I915_EXEC_RENDER (1<<0) |
||
720 | #define I915_EXEC_BSD (2<<0) |
||
721 | #define I915_EXEC_BLT (3<<0) |
||
722 | #define I915_EXEC_VEBOX (4<<0) |
||
723 | |||
724 | /* Used for switching the constants addressing mode on gen4+ RENDER ring. |
||
725 | * Gen6+ only supports relative addressing to dynamic state (default) and |
||
726 | * absolute addressing. |
||
727 | * |
||
728 | * These flags are ignored for the BSD and BLT rings. |
||
729 | */ |
||
730 | #define I915_EXEC_CONSTANTS_MASK (3<<6) |
||
731 | #define I915_EXEC_CONSTANTS_REL_GENERAL (0<<6) /* default */ |
||
732 | #define I915_EXEC_CONSTANTS_ABSOLUTE (1<<6) |
||
733 | #define I915_EXEC_CONSTANTS_REL_SURFACE (2<<6) /* gen4/5 only */ |
||
734 | __u64 flags; |
||
735 | __u64 rsvd1; /* now used for context info */ |
||
736 | __u64 rsvd2; |
||
737 | }; |
||
738 | |||
739 | /** Resets the SO write offset registers for transform feedback on gen7. */ |
||
740 | #define I915_EXEC_GEN7_SOL_RESET (1<<8) |
||
741 | |||
742 | /** Request a privileged ("secure") batch buffer. Note only available for |
||
743 | * DRM_ROOT_ONLY | DRM_MASTER processes. |
||
744 | */ |
||
745 | #define I915_EXEC_SECURE (1<<9) |
||
746 | |||
747 | /** Inform the kernel that the batch is and will always be pinned. This |
||
748 | * negates the requirement for a workaround to be performed to avoid |
||
749 | * an incoherent CS (such as can be found on 830/845). If this flag is |
||
750 | * not passed, the kernel will endeavour to make sure the batch is |
||
751 | * coherent with the CS before execution. If this flag is passed, |
||
752 | * userspace assumes the responsibility for ensuring the same. |
||
753 | */ |
||
754 | #define I915_EXEC_IS_PINNED (1<<10) |
||
755 | |||
756 | /** Provide a hint to the kernel that the command stream and auxiliary |
||
757 | * state buffers already holds the correct presumed addresses and so the |
||
758 | * relocation process may be skipped if no buffers need to be moved in |
||
759 | * preparation for the execbuffer. |
||
760 | */ |
||
761 | #define I915_EXEC_NO_RELOC (1<<11) |
||
762 | |||
763 | /** Use the reloc.handle as an index into the exec object array rather |
||
764 | * than as the per-file handle. |
||
765 | */ |
||
766 | #define I915_EXEC_HANDLE_LUT (1<<12) |
||
767 | |||
6082 | serge | 768 | /** Used for switching BSD rings on the platforms with two BSD rings */ |
769 | #define I915_EXEC_BSD_MASK (3<<13) |
||
770 | #define I915_EXEC_BSD_DEFAULT (0<<13) /* default ping-pong mode */ |
||
771 | #define I915_EXEC_BSD_RING1 (1<<13) |
||
772 | #define I915_EXEC_BSD_RING2 (2<<13) |
||
5270 | serge | 773 | |
6082 | serge | 774 | /** Tell the kernel that the batchbuffer is processed by |
775 | * the resource streamer. |
||
776 | */ |
||
777 | #define I915_EXEC_RESOURCE_STREAMER (1<<15) |
||
778 | |||
779 | #define __I915_EXEC_UNKNOWN_FLAGS -(I915_EXEC_RESOURCE_STREAMER<<1) |
||
780 | |||
5270 | serge | 781 | #define I915_EXEC_CONTEXT_ID_MASK (0xffffffff) |
782 | #define i915_execbuffer2_set_context_id(eb2, context) \ |
||
783 | (eb2).rsvd1 = context & I915_EXEC_CONTEXT_ID_MASK |
||
784 | #define i915_execbuffer2_get_context_id(eb2) \ |
||
785 | ((eb2).rsvd1 & I915_EXEC_CONTEXT_ID_MASK) |
||
786 | |||
787 | struct drm_i915_gem_pin { |
||
788 | /** Handle of the buffer to be pinned. */ |
||
789 | __u32 handle; |
||
790 | __u32 pad; |
||
791 | |||
792 | /** alignment required within the aperture */ |
||
793 | __u64 alignment; |
||
794 | |||
795 | /** Returned GTT offset of the buffer. */ |
||
796 | __u64 offset; |
||
797 | }; |
||
798 | |||
799 | struct drm_i915_gem_unpin { |
||
800 | /** Handle of the buffer to be unpinned. */ |
||
801 | __u32 handle; |
||
802 | __u32 pad; |
||
803 | }; |
||
804 | |||
805 | struct drm_i915_gem_busy { |
||
806 | /** Handle of the buffer to check for busy */ |
||
807 | __u32 handle; |
||
808 | |||
809 | /** Return busy status (1 if busy, 0 if idle). |
||
810 | * The high word is used to indicate on which rings the object |
||
811 | * currently resides: |
||
812 | * 16:31 - busy (r or r/w) rings (16 render, 17 bsd, 18 blt, etc) |
||
813 | */ |
||
814 | __u32 busy; |
||
815 | }; |
||
816 | |||
817 | /** |
||
818 | * I915_CACHING_NONE |
||
819 | * |
||
820 | * GPU access is not coherent with cpu caches. Default for machines without an |
||
821 | * LLC. |
||
822 | */ |
||
823 | #define I915_CACHING_NONE 0 |
||
824 | /** |
||
825 | * I915_CACHING_CACHED |
||
826 | * |
||
827 | * GPU access is coherent with cpu caches and furthermore the data is cached in |
||
828 | * last-level caches shared between cpu cores and the gpu GT. Default on |
||
829 | * machines with HAS_LLC. |
||
830 | */ |
||
831 | #define I915_CACHING_CACHED 1 |
||
832 | /** |
||
833 | * I915_CACHING_DISPLAY |
||
834 | * |
||
835 | * Special GPU caching mode which is coherent with the scanout engines. |
||
836 | * Transparently falls back to I915_CACHING_NONE on platforms where no special |
||
837 | * cache mode (like write-through or gfdt flushing) is available. The kernel |
||
838 | * automatically sets this mode when using a buffer as a scanout target. |
||
839 | * Userspace can manually set this mode to avoid a costly stall and clflush in |
||
840 | * the hotpath of drawing the first frame. |
||
841 | */ |
||
842 | #define I915_CACHING_DISPLAY 2 |
||
843 | |||
844 | struct drm_i915_gem_caching { |
||
845 | /** |
||
846 | * Handle of the buffer to set/get the caching level of. */ |
||
847 | __u32 handle; |
||
848 | |||
849 | /** |
||
850 | * Cacheing level to apply or return value |
||
851 | * |
||
852 | * bits0-15 are for generic caching control (i.e. the above defined |
||
853 | * values). bits16-31 are reserved for platform-specific variations |
||
854 | * (e.g. l3$ caching on gen7). */ |
||
855 | __u32 caching; |
||
856 | }; |
||
857 | |||
858 | #define I915_TILING_NONE 0 |
||
859 | #define I915_TILING_X 1 |
||
860 | #define I915_TILING_Y 2 |
||
861 | |||
862 | #define I915_BIT_6_SWIZZLE_NONE 0 |
||
863 | #define I915_BIT_6_SWIZZLE_9 1 |
||
864 | #define I915_BIT_6_SWIZZLE_9_10 2 |
||
865 | #define I915_BIT_6_SWIZZLE_9_11 3 |
||
866 | #define I915_BIT_6_SWIZZLE_9_10_11 4 |
||
867 | /* Not seen by userland */ |
||
868 | #define I915_BIT_6_SWIZZLE_UNKNOWN 5 |
||
869 | /* Seen by userland. */ |
||
870 | #define I915_BIT_6_SWIZZLE_9_17 6 |
||
871 | #define I915_BIT_6_SWIZZLE_9_10_17 7 |
||
872 | |||
873 | struct drm_i915_gem_set_tiling { |
||
874 | /** Handle of the buffer to have its tiling state updated */ |
||
875 | __u32 handle; |
||
876 | |||
877 | /** |
||
878 | * Tiling mode for the object (I915_TILING_NONE, I915_TILING_X, |
||
879 | * I915_TILING_Y). |
||
880 | * |
||
881 | * This value is to be set on request, and will be updated by the |
||
882 | * kernel on successful return with the actual chosen tiling layout. |
||
883 | * |
||
884 | * The tiling mode may be demoted to I915_TILING_NONE when the system |
||
885 | * has bit 6 swizzling that can't be managed correctly by GEM. |
||
886 | * |
||
887 | * Buffer contents become undefined when changing tiling_mode. |
||
888 | */ |
||
889 | __u32 tiling_mode; |
||
890 | |||
891 | /** |
||
892 | * Stride in bytes for the object when in I915_TILING_X or |
||
893 | * I915_TILING_Y. |
||
894 | */ |
||
895 | __u32 stride; |
||
896 | |||
897 | /** |
||
898 | * Returned address bit 6 swizzling required for CPU access through |
||
899 | * mmap mapping. |
||
900 | */ |
||
901 | __u32 swizzle_mode; |
||
902 | }; |
||
903 | |||
904 | struct drm_i915_gem_get_tiling { |
||
905 | /** Handle of the buffer to get tiling state for. */ |
||
906 | __u32 handle; |
||
907 | |||
908 | /** |
||
909 | * Current tiling mode for the object (I915_TILING_NONE, I915_TILING_X, |
||
910 | * I915_TILING_Y). |
||
911 | */ |
||
912 | __u32 tiling_mode; |
||
913 | |||
914 | /** |
||
915 | * Returned address bit 6 swizzling required for CPU access through |
||
916 | * mmap mapping. |
||
917 | */ |
||
918 | __u32 swizzle_mode; |
||
919 | |||
920 | /** |
||
921 | * Returned address bit 6 swizzling required for CPU access through |
||
922 | * mmap mapping whilst bound. |
||
923 | */ |
||
924 | __u32 phys_swizzle_mode; |
||
925 | }; |
||
926 | |||
927 | struct drm_i915_gem_get_aperture { |
||
928 | /** Total size of the aperture used by i915_gem_execbuffer, in bytes */ |
||
929 | __u64 aper_size; |
||
930 | |||
931 | /** |
||
932 | * Available space in the aperture used by i915_gem_execbuffer, in |
||
933 | * bytes |
||
934 | */ |
||
935 | __u64 aper_available_size; |
||
936 | }; |
||
937 | |||
938 | struct drm_i915_get_pipe_from_crtc_id { |
||
939 | /** ID of CRTC being requested **/ |
||
940 | __u32 crtc_id; |
||
941 | |||
942 | /** pipe of requested CRTC **/ |
||
943 | __u32 pipe; |
||
944 | }; |
||
945 | |||
946 | #define I915_MADV_WILLNEED 0 |
||
947 | #define I915_MADV_DONTNEED 1 |
||
948 | #define __I915_MADV_PURGED 2 /* internal state */ |
||
949 | |||
950 | struct drm_i915_gem_madvise { |
||
951 | /** Handle of the buffer to change the backing store advice */ |
||
952 | __u32 handle; |
||
953 | |||
954 | /* Advice: either the buffer will be needed again in the near future, |
||
955 | * or wont be and could be discarded under memory pressure. |
||
956 | */ |
||
957 | __u32 madv; |
||
958 | |||
959 | /** Whether the backing store still exists. */ |
||
960 | __u32 retained; |
||
961 | }; |
||
962 | |||
963 | /* flags */ |
||
964 | #define I915_OVERLAY_TYPE_MASK 0xff |
||
965 | #define I915_OVERLAY_YUV_PLANAR 0x01 |
||
966 | #define I915_OVERLAY_YUV_PACKED 0x02 |
||
967 | #define I915_OVERLAY_RGB 0x03 |
||
968 | |||
969 | #define I915_OVERLAY_DEPTH_MASK 0xff00 |
||
970 | #define I915_OVERLAY_RGB24 0x1000 |
||
971 | #define I915_OVERLAY_RGB16 0x2000 |
||
972 | #define I915_OVERLAY_RGB15 0x3000 |
||
973 | #define I915_OVERLAY_YUV422 0x0100 |
||
974 | #define I915_OVERLAY_YUV411 0x0200 |
||
975 | #define I915_OVERLAY_YUV420 0x0300 |
||
976 | #define I915_OVERLAY_YUV410 0x0400 |
||
977 | |||
978 | #define I915_OVERLAY_SWAP_MASK 0xff0000 |
||
979 | #define I915_OVERLAY_NO_SWAP 0x000000 |
||
980 | #define I915_OVERLAY_UV_SWAP 0x010000 |
||
981 | #define I915_OVERLAY_Y_SWAP 0x020000 |
||
982 | #define I915_OVERLAY_Y_AND_UV_SWAP 0x030000 |
||
983 | |||
984 | #define I915_OVERLAY_FLAGS_MASK 0xff000000 |
||
985 | #define I915_OVERLAY_ENABLE 0x01000000 |
||
986 | |||
987 | struct drm_intel_overlay_put_image { |
||
988 | /* various flags and src format description */ |
||
989 | __u32 flags; |
||
990 | /* source picture description */ |
||
991 | __u32 bo_handle; |
||
992 | /* stride values and offsets are in bytes, buffer relative */ |
||
993 | __u16 stride_Y; /* stride for packed formats */ |
||
994 | __u16 stride_UV; |
||
995 | __u32 offset_Y; /* offset for packet formats */ |
||
996 | __u32 offset_U; |
||
997 | __u32 offset_V; |
||
998 | /* in pixels */ |
||
999 | __u16 src_width; |
||
1000 | __u16 src_height; |
||
1001 | /* to compensate the scaling factors for partially covered surfaces */ |
||
1002 | __u16 src_scan_width; |
||
1003 | __u16 src_scan_height; |
||
1004 | /* output crtc description */ |
||
1005 | __u32 crtc_id; |
||
1006 | __u16 dst_x; |
||
1007 | __u16 dst_y; |
||
1008 | __u16 dst_width; |
||
1009 | __u16 dst_height; |
||
1010 | }; |
||
1011 | |||
1012 | /* flags */ |
||
1013 | #define I915_OVERLAY_UPDATE_ATTRS (1<<0) |
||
1014 | #define I915_OVERLAY_UPDATE_GAMMA (1<<1) |
||
6082 | serge | 1015 | #define I915_OVERLAY_DISABLE_DEST_COLORKEY (1<<2) |
5270 | serge | 1016 | struct drm_intel_overlay_attrs { |
1017 | __u32 flags; |
||
1018 | __u32 color_key; |
||
1019 | __s32 brightness; |
||
1020 | __u32 contrast; |
||
1021 | __u32 saturation; |
||
1022 | __u32 gamma0; |
||
1023 | __u32 gamma1; |
||
1024 | __u32 gamma2; |
||
1025 | __u32 gamma3; |
||
1026 | __u32 gamma4; |
||
1027 | __u32 gamma5; |
||
1028 | }; |
||
1029 | |||
1030 | /* |
||
1031 | * Intel sprite handling |
||
1032 | * |
||
1033 | * Color keying works with a min/mask/max tuple. Both source and destination |
||
1034 | * color keying is allowed. |
||
1035 | * |
||
1036 | * Source keying: |
||
1037 | * Sprite pixels within the min & max values, masked against the color channels |
||
1038 | * specified in the mask field, will be transparent. All other pixels will |
||
1039 | * be displayed on top of the primary plane. For RGB surfaces, only the min |
||
1040 | * and mask fields will be used; ranged compares are not allowed. |
||
1041 | * |
||
1042 | * Destination keying: |
||
1043 | * Primary plane pixels that match the min value, masked against the color |
||
1044 | * channels specified in the mask field, will be replaced by corresponding |
||
1045 | * pixels from the sprite plane. |
||
1046 | * |
||
1047 | * Note that source & destination keying are exclusive; only one can be |
||
1048 | * active on a given plane. |
||
1049 | */ |
||
1050 | |||
1051 | #define I915_SET_COLORKEY_NONE (1<<0) /* disable color key matching */ |
||
1052 | #define I915_SET_COLORKEY_DESTINATION (1<<1) |
||
1053 | #define I915_SET_COLORKEY_SOURCE (1<<2) |
||
1054 | struct drm_intel_sprite_colorkey { |
||
1055 | __u32 plane_id; |
||
1056 | __u32 min_value; |
||
1057 | __u32 channel_mask; |
||
1058 | __u32 max_value; |
||
1059 | __u32 flags; |
||
1060 | }; |
||
1061 | |||
1062 | struct drm_i915_gem_wait { |
||
1063 | /** Handle of BO we shall wait on */ |
||
1064 | __u32 bo_handle; |
||
1065 | __u32 flags; |
||
1066 | /** Number of nanoseconds to wait, Returns time remaining. */ |
||
1067 | __s64 timeout_ns; |
||
1068 | }; |
||
1069 | |||
1070 | struct drm_i915_gem_context_create { |
||
1071 | /* output: id of new context*/ |
||
1072 | __u32 ctx_id; |
||
1073 | __u32 pad; |
||
1074 | }; |
||
1075 | |||
1076 | struct drm_i915_gem_context_destroy { |
||
1077 | __u32 ctx_id; |
||
1078 | __u32 pad; |
||
1079 | }; |
||
1080 | |||
1081 | struct drm_i915_reg_read { |
||
1082 | __u64 offset; |
||
1083 | __u64 val; /* Return value */ |
||
1084 | }; |
||
6082 | serge | 1085 | /* Known registers: |
1086 | * |
||
1087 | * Render engine timestamp - 0x2358 + 64bit - gen7+ |
||
1088 | * - Note this register returns an invalid value if using the default |
||
1089 | * single instruction 8byte read, in order to workaround that use |
||
1090 | * offset (0x2538 | 1) instead. |
||
1091 | * |
||
1092 | */ |
||
5270 | serge | 1093 | |
1094 | struct drm_i915_reset_stats { |
||
1095 | __u32 ctx_id; |
||
1096 | __u32 flags; |
||
1097 | |||
1098 | /* All resets since boot/module reload, for all contexts */ |
||
1099 | __u32 reset_count; |
||
1100 | |||
1101 | /* Number of batches lost when active in GPU, for this context */ |
||
1102 | __u32 batch_active; |
||
1103 | |||
1104 | /* Number of batches lost pending for execution, for this context */ |
||
1105 | __u32 batch_pending; |
||
1106 | |||
1107 | __u32 pad; |
||
1108 | }; |
||
1109 | |||
1110 | struct drm_i915_gem_userptr { |
||
1111 | __u64 user_ptr; |
||
1112 | __u64 user_size; |
||
1113 | __u32 flags; |
||
1114 | #define I915_USERPTR_READ_ONLY 0x1 |
||
1115 | #define I915_USERPTR_UNSYNCHRONIZED 0x80000000 |
||
1116 | /** |
||
1117 | * Returned handle for the object. |
||
1118 | * |
||
1119 | * Object handles are nonzero. |
||
1120 | */ |
||
1121 | __u32 handle; |
||
1122 | }; |
||
1123 | |||
6082 | serge | 1124 | struct drm_i915_gem_context_param { |
1125 | __u32 ctx_id; |
||
1126 | __u32 size; |
||
1127 | __u64 param; |
||
1128 | #define I915_CONTEXT_PARAM_BAN_PERIOD 0x1 |
||
1129 | #define I915_CONTEXT_PARAM_NO_ZEROMAP 0x2 |
||
1130 | __u64 value; |
||
1131 | }; |
||
1132 | |||
1133 | |||
5270 | serge | 1134 | struct drm_i915_mask { |
1135 | __u32 handle; |
||
1136 | __u32 width; |
||
1137 | __u32 height; |
||
1138 | __u32 bo_size; |
||
1139 | __u32 bo_pitch; |
||
1140 | __u32 bo_map; |
||
1141 | }; |
||
1142 | |||
1143 | struct drm_i915_fb_info { |
||
1144 | __u32 name; |
||
1145 | __u32 width; |
||
1146 | __u32 height; |
||
1147 | __u32 pitch; |
||
1148 | __u32 tiling; |
||
1149 | __u32 crtc; |
||
1150 | __u32 pipe; |
||
1151 | }; |
||
1152 | |||
1153 | struct drm_i915_mask_update { |
||
1154 | __u32 handle; |
||
1155 | __u32 dx; |
||
1156 | __u32 dy; |
||
1157 | __u32 width; |
||
1158 | __u32 height; |
||
1159 | __u32 bo_pitch; |
||
1160 | __u32 bo_map; |
||
6082 | serge | 1161 | __u32 forced; |
5270 | serge | 1162 | }; |
1163 | |||
1164 | |||
1165 | #endif /* _UAPI_I915_DRM_H_ */2) |