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Rev | Author | Line No. | Line |
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1964 | serge | 1 | /* |
2 | * pci.h |
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3 | * |
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4 | * PCI defines and function prototypes |
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5 | * Copyright 1994, Drew Eckhardt |
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6 | * Copyright 1997--1999 Martin Mares |
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7 | * |
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8 | * For more information, please consult the following manuals (look at |
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9 | * http://www.pcisig.com/ for how to get them): |
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10 | * |
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11 | * PCI BIOS Specification |
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12 | * PCI Local Bus Specification |
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13 | * PCI to PCI Bridge Specification |
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14 | * PCI System Design Guide |
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15 | */ |
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1408 | serge | 16 | |
17 | #include |
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18 | #include |
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19 | |||
1964 | serge | 20 | #ifndef __PCI_H__ |
21 | #define __PCI_H__ |
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1628 | serge | 22 | |
1408 | serge | 23 | #define PCI_ANY_ID (~0) |
24 | |||
25 | |||
26 | #define PCI_CLASS_NOT_DEFINED 0x0000 |
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27 | #define PCI_CLASS_NOT_DEFINED_VGA 0x0001 |
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28 | |||
29 | #define PCI_BASE_CLASS_STORAGE 0x01 |
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30 | #define PCI_CLASS_STORAGE_SCSI 0x0100 |
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31 | #define PCI_CLASS_STORAGE_IDE 0x0101 |
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32 | #define PCI_CLASS_STORAGE_FLOPPY 0x0102 |
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33 | #define PCI_CLASS_STORAGE_IPI 0x0103 |
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34 | #define PCI_CLASS_STORAGE_RAID 0x0104 |
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35 | #define PCI_CLASS_STORAGE_SATA 0x0106 |
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36 | #define PCI_CLASS_STORAGE_SATA_AHCI 0x010601 |
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37 | #define PCI_CLASS_STORAGE_SAS 0x0107 |
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38 | #define PCI_CLASS_STORAGE_OTHER 0x0180 |
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39 | |||
40 | #define PCI_BASE_CLASS_NETWORK 0x02 |
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41 | #define PCI_CLASS_NETWORK_ETHERNET 0x0200 |
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42 | #define PCI_CLASS_NETWORK_TOKEN_RING 0x0201 |
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43 | #define PCI_CLASS_NETWORK_FDDI 0x0202 |
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44 | #define PCI_CLASS_NETWORK_ATM 0x0203 |
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45 | #define PCI_CLASS_NETWORK_OTHER 0x0280 |
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46 | |||
47 | #define PCI_BASE_CLASS_DISPLAY 0x03 |
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48 | #define PCI_CLASS_DISPLAY_VGA 0x0300 |
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49 | #define PCI_CLASS_DISPLAY_XGA 0x0301 |
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50 | #define PCI_CLASS_DISPLAY_3D 0x0302 |
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51 | #define PCI_CLASS_DISPLAY_OTHER 0x0380 |
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52 | |||
53 | #define PCI_BASE_CLASS_MULTIMEDIA 0x04 |
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54 | #define PCI_CLASS_MULTIMEDIA_VIDEO 0x0400 |
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55 | #define PCI_CLASS_MULTIMEDIA_AUDIO 0x0401 |
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56 | #define PCI_CLASS_MULTIMEDIA_PHONE 0x0402 |
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57 | #define PCI_CLASS_MULTIMEDIA_OTHER 0x0480 |
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58 | |||
59 | #define PCI_BASE_CLASS_MEMORY 0x05 |
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60 | #define PCI_CLASS_MEMORY_RAM 0x0500 |
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61 | #define PCI_CLASS_MEMORY_FLASH 0x0501 |
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62 | #define PCI_CLASS_MEMORY_OTHER 0x0580 |
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63 | |||
64 | #define PCI_BASE_CLASS_BRIDGE 0x06 |
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65 | #define PCI_CLASS_BRIDGE_HOST 0x0600 |
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66 | #define PCI_CLASS_BRIDGE_ISA 0x0601 |
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67 | #define PCI_CLASS_BRIDGE_EISA 0x0602 |
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68 | #define PCI_CLASS_BRIDGE_MC 0x0603 |
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69 | #define PCI_CLASS_BRIDGE_PCI 0x0604 |
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70 | #define PCI_CLASS_BRIDGE_PCMCIA 0x0605 |
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71 | #define PCI_CLASS_BRIDGE_NUBUS 0x0606 |
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72 | #define PCI_CLASS_BRIDGE_CARDBUS 0x0607 |
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73 | #define PCI_CLASS_BRIDGE_RACEWAY 0x0608 |
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74 | #define PCI_CLASS_BRIDGE_OTHER 0x0680 |
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75 | |||
76 | #define PCI_BASE_CLASS_COMMUNICATION 0x07 |
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77 | #define PCI_CLASS_COMMUNICATION_SERIAL 0x0700 |
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78 | #define PCI_CLASS_COMMUNICATION_PARALLEL 0x0701 |
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79 | #define PCI_CLASS_COMMUNICATION_MULTISERIAL 0x0702 |
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80 | #define PCI_CLASS_COMMUNICATION_MODEM 0x0703 |
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81 | #define PCI_CLASS_COMMUNICATION_OTHER 0x0780 |
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82 | |||
83 | #define PCI_BASE_CLASS_SYSTEM 0x08 |
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84 | #define PCI_CLASS_SYSTEM_PIC 0x0800 |
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85 | #define PCI_CLASS_SYSTEM_PIC_IOAPIC 0x080010 |
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86 | #define PCI_CLASS_SYSTEM_PIC_IOXAPIC 0x080020 |
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87 | #define PCI_CLASS_SYSTEM_DMA 0x0801 |
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88 | #define PCI_CLASS_SYSTEM_TIMER 0x0802 |
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89 | #define PCI_CLASS_SYSTEM_RTC 0x0803 |
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90 | #define PCI_CLASS_SYSTEM_PCI_HOTPLUG 0x0804 |
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91 | #define PCI_CLASS_SYSTEM_SDHCI 0x0805 |
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92 | #define PCI_CLASS_SYSTEM_OTHER 0x0880 |
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93 | |||
94 | #define PCI_BASE_CLASS_INPUT 0x09 |
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95 | #define PCI_CLASS_INPUT_KEYBOARD 0x0900 |
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96 | #define PCI_CLASS_INPUT_PEN 0x0901 |
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97 | #define PCI_CLASS_INPUT_MOUSE 0x0902 |
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98 | #define PCI_CLASS_INPUT_SCANNER 0x0903 |
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99 | #define PCI_CLASS_INPUT_GAMEPORT 0x0904 |
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100 | #define PCI_CLASS_INPUT_OTHER 0x0980 |
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101 | |||
102 | #define PCI_BASE_CLASS_DOCKING 0x0a |
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103 | #define PCI_CLASS_DOCKING_GENERIC 0x0a00 |
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104 | #define PCI_CLASS_DOCKING_OTHER 0x0a80 |
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105 | |||
106 | #define PCI_BASE_CLASS_PROCESSOR 0x0b |
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107 | #define PCI_CLASS_PROCESSOR_386 0x0b00 |
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108 | #define PCI_CLASS_PROCESSOR_486 0x0b01 |
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109 | #define PCI_CLASS_PROCESSOR_PENTIUM 0x0b02 |
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110 | #define PCI_CLASS_PROCESSOR_ALPHA 0x0b10 |
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111 | #define PCI_CLASS_PROCESSOR_POWERPC 0x0b20 |
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112 | #define PCI_CLASS_PROCESSOR_MIPS 0x0b30 |
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113 | #define PCI_CLASS_PROCESSOR_CO 0x0b40 |
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114 | |||
115 | #define PCI_BASE_CLASS_SERIAL 0x0c |
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116 | #define PCI_CLASS_SERIAL_FIREWIRE 0x0c00 |
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117 | #define PCI_CLASS_SERIAL_FIREWIRE_OHCI 0x0c0010 |
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118 | #define PCI_CLASS_SERIAL_ACCESS 0x0c01 |
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119 | #define PCI_CLASS_SERIAL_SSA 0x0c02 |
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120 | #define PCI_CLASS_SERIAL_USB 0x0c03 |
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121 | #define PCI_CLASS_SERIAL_USB_UHCI 0x0c0300 |
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122 | #define PCI_CLASS_SERIAL_USB_OHCI 0x0c0310 |
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123 | #define PCI_CLASS_SERIAL_USB_EHCI 0x0c0320 |
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124 | #define PCI_CLASS_SERIAL_FIBER 0x0c04 |
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125 | #define PCI_CLASS_SERIAL_SMBUS 0x0c05 |
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126 | |||
127 | #define PCI_BASE_CLASS_WIRELESS 0x0d |
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128 | #define PCI_CLASS_WIRELESS_RF_CONTROLLER 0x0d10 |
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129 | #define PCI_CLASS_WIRELESS_WHCI 0x0d1010 |
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130 | |||
131 | #define PCI_BASE_CLASS_INTELLIGENT 0x0e |
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132 | #define PCI_CLASS_INTELLIGENT_I2O 0x0e00 |
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133 | |||
134 | #define PCI_BASE_CLASS_SATELLITE 0x0f |
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135 | #define PCI_CLASS_SATELLITE_TV 0x0f00 |
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136 | #define PCI_CLASS_SATELLITE_AUDIO 0x0f01 |
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137 | #define PCI_CLASS_SATELLITE_VOICE 0x0f03 |
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138 | #define PCI_CLASS_SATELLITE_DATA 0x0f04 |
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139 | |||
140 | #define PCI_BASE_CLASS_CRYPT 0x10 |
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141 | #define PCI_CLASS_CRYPT_NETWORK 0x1000 |
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142 | #define PCI_CLASS_CRYPT_ENTERTAINMENT 0x1001 |
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143 | #define PCI_CLASS_CRYPT_OTHER 0x1080 |
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144 | |||
145 | #define PCI_BASE_CLASS_SIGNAL_PROCESSING 0x11 |
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146 | #define PCI_CLASS_SP_DPIO 0x1100 |
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147 | #define PCI_CLASS_SP_OTHER 0x1180 |
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148 | |||
149 | #define PCI_CLASS_OTHERS 0xff |
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150 | |||
151 | |||
1964 | serge | 152 | /* |
153 | * Under PCI, each device has 256 bytes of configuration address space, |
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154 | * of which the first 64 bytes are standardized as follows: |
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155 | */ |
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156 | #define PCI_VENDOR_ID 0x000 /* 16 bits */ |
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157 | #define PCI_DEVICE_ID 0x002 /* 16 bits */ |
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158 | #define PCI_COMMAND 0x004 /* 16 bits */ |
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159 | #define PCI_COMMAND_IO 0x001 /* Enable response in I/O space */ |
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160 | #define PCI_COMMAND_MEMORY 0x002 /* Enable response in Memory space */ |
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161 | #define PCI_COMMAND_MASTER 0x004 /* Enable bus mastering */ |
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162 | #define PCI_COMMAND_SPECIAL 0x008 /* Enable response to special cycles */ |
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163 | #define PCI_COMMAND_INVALIDATE 0x010 /* Use memory write and invalidate */ |
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164 | #define PCI_COMMAND_VGA_PALETTE 0x020 /* Enable palette snooping */ |
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165 | #define PCI_COMMAND_PARITY 0x040 /* Enable parity checking */ |
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166 | #define PCI_COMMAND_WAIT 0x080 /* Enable address/data stepping */ |
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167 | #define PCI_COMMAND_SERR 0x100 /* Enable SERR */ |
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168 | #define PCI_COMMAND_FAST_BACK 0x200 /* Enable back-to-back writes */ |
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169 | #define PCI_COMMAND_INTX_DISABLE 0x400 /* INTx Emulation Disable */ |
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1408 | serge | 170 | |
1964 | serge | 171 | #define PCI_STATUS 0x006 /* 16 bits */ |
172 | #define PCI_STATUS_CAP_LIST 0x010 /* Support Capability List */ |
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173 | #define PCI_STATUS_66MHZ 0x020 /* Support 66 Mhz PCI 2.1 bus */ |
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174 | #define PCI_STATUS_UDF 0x040 /* Support User Definable Features [obsolete] */ |
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175 | #define PCI_STATUS_FAST_BACK 0x080 /* Accept fast-back to back */ |
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176 | #define PCI_STATUS_PARITY 0x100 /* Detected parity error */ |
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177 | #define PCI_STATUS_DEVSEL_MASK 0x600 /* DEVSEL timing */ |
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178 | #define PCI_STATUS_DEVSEL_FAST 0x000 |
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179 | #define PCI_STATUS_DEVSEL_MEDIUM 0x200 |
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180 | #define PCI_STATUS_DEVSEL_SLOW 0x400 |
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181 | #define PCI_STATUS_SIG_TARGET_ABORT 0x800 /* Set on target abort */ |
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182 | #define PCI_STATUS_REC_TARGET_ABORT 0x1000 /* Master ack of " */ |
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183 | #define PCI_STATUS_REC_MASTER_ABORT 0x2000 /* Set on master abort */ |
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184 | #define PCI_STATUS_SIG_SYSTEM_ERROR 0x4000 /* Set when we drive SERR */ |
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185 | #define PCI_STATUS_DETECTED_PARITY 0x8000 /* Set on parity error */ |
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186 | |||
187 | #define PCI_CLASS_REVISION 0x08 /* High 24 bits are class, low 8 revision */ |
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188 | #define PCI_REVISION_ID 0x08 /* Revision ID */ |
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189 | #define PCI_CLASS_PROG 0x09 /* Reg. Level Programming Interface */ |
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190 | #define PCI_CLASS_DEVICE 0x0a /* Device class */ |
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191 | |||
192 | #define PCI_CACHE_LINE_SIZE 0x0c /* 8 bits */ |
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193 | #define PCI_LATENCY_TIMER 0x0d /* 8 bits */ |
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194 | #define PCI_HEADER_TYPE 0x0e /* 8 bits */ |
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195 | #define PCI_HEADER_TYPE_NORMAL 0 |
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196 | #define PCI_HEADER_TYPE_BRIDGE 1 |
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197 | #define PCI_HEADER_TYPE_CARDBUS 2 |
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198 | |||
199 | #define PCI_BIST 0x0f /* 8 bits */ |
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200 | #define PCI_BIST_CODE_MASK 0x0f /* Return result */ |
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201 | #define PCI_BIST_START 0x40 /* 1 to start BIST, 2 secs or less */ |
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202 | #define PCI_BIST_CAPABLE 0x80 /* 1 if BIST capable */ |
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203 | |||
204 | /* |
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205 | * Base addresses specify locations in memory or I/O space. |
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206 | * Decoded size can be determined by writing a value of |
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207 | * 0xffffffff to the register, and reading it back. Only |
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208 | * 1 bits are decoded. |
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209 | */ |
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210 | #define PCI_BASE_ADDRESS_0 0x10 /* 32 bits */ |
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211 | #define PCI_BASE_ADDRESS_1 0x14 /* 32 bits [htype 0,1 only] */ |
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212 | #define PCI_BASE_ADDRESS_2 0x18 /* 32 bits [htype 0 only] */ |
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213 | #define PCI_BASE_ADDRESS_3 0x1c /* 32 bits */ |
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214 | #define PCI_BASE_ADDRESS_4 0x20 /* 32 bits */ |
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215 | #define PCI_BASE_ADDRESS_5 0x24 /* 32 bits */ |
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216 | #define PCI_BASE_ADDRESS_SPACE 0x01 /* 0 = memory, 1 = I/O */ |
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217 | #define PCI_BASE_ADDRESS_SPACE_IO 0x01 |
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218 | #define PCI_BASE_ADDRESS_SPACE_MEMORY 0x00 |
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219 | #define PCI_BASE_ADDRESS_MEM_TYPE_MASK 0x06 |
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220 | #define PCI_BASE_ADDRESS_MEM_TYPE_32 0x00 /* 32 bit address */ |
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221 | #define PCI_BASE_ADDRESS_MEM_TYPE_1M 0x02 /* Below 1M [obsolete] */ |
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222 | #define PCI_BASE_ADDRESS_MEM_TYPE_64 0x04 /* 64 bit address */ |
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223 | #define PCI_BASE_ADDRESS_MEM_PREFETCH 0x08 /* prefetchable? */ |
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224 | #define PCI_BASE_ADDRESS_MEM_MASK (~0x0fUL) |
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225 | #define PCI_BASE_ADDRESS_IO_MASK (~0x03UL) |
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226 | /* bit 1 is reserved if address_space = 1 */ |
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227 | |||
228 | #define PCI_ROM_ADDRESS1 0x38 /* Same as PCI_ROM_ADDRESS, but for htype 1 */ |
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229 | |||
230 | /* Header type 0 (normal devices) */ |
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231 | #define PCI_CARDBUS_CIS 0x28 |
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232 | #define PCI_SUBSYSTEM_VENDOR_ID 0x2c |
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233 | #define PCI_SUBSYSTEM_ID 0x2e |
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234 | #define PCI_ROM_ADDRESS 0x30 /* Bits 31..11 are address, 10..1 reserved */ |
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235 | #define PCI_ROM_ADDRESS_ENABLE 0x01 |
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236 | #define PCI_ROM_ADDRESS_MASK (~0x7ffUL) |
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237 | |||
238 | #define PCI_INTERRUPT_LINE 0x3c /* 8 bits */ |
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239 | #define PCI_INTERRUPT_PIN 0x3d /* 8 bits */ |
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240 | |||
241 | |||
242 | #define PCI_CB_SUBSYSTEM_VENDOR_ID 0x40 |
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243 | #define PCI_CB_SUBSYSTEM_ID 0x42 |
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244 | |||
245 | #define PCI_CAPABILITY_LIST 0x34 /* Offset of first capability list entry */ |
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246 | #define PCI_CB_CAPABILITY_LIST 0x14 |
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247 | /* Capability lists */ |
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248 | |||
249 | #define PCI_CAP_LIST_ID 0 /* Capability ID */ |
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250 | #define PCI_CAP_ID_PM 0x01 /* Power Management */ |
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251 | #define PCI_CAP_ID_AGP 0x02 /* Accelerated Graphics Port */ |
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252 | #define PCI_CAP_ID_VPD 0x03 /* Vital Product Data */ |
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253 | #define PCI_CAP_ID_SLOTID 0x04 /* Slot Identification */ |
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254 | #define PCI_CAP_ID_MSI 0x05 /* Message Signalled Interrupts */ |
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255 | #define PCI_CAP_ID_CHSWP 0x06 /* CompactPCI HotSwap */ |
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256 | #define PCI_CAP_ID_PCIX 0x07 /* PCI-X */ |
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257 | #define PCI_CAP_ID_HT 0x08 /* HyperTransport */ |
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258 | #define PCI_CAP_ID_VNDR 0x09 /* Vendor specific capability */ |
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259 | #define PCI_CAP_ID_SHPC 0x0C /* PCI Standard Hot-Plug Controller */ |
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260 | #define PCI_CAP_ID_EXP 0x10 /* PCI Express */ |
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261 | #define PCI_CAP_ID_MSIX 0x11 /* MSI-X */ |
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262 | #define PCI_CAP_LIST_NEXT 1 /* Next capability in the list */ |
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263 | #define PCI_CAP_FLAGS 2 /* Capability defined flags (16 bits) */ |
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264 | #define PCI_CAP_SIZEOF 4 |
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265 | |||
266 | |||
267 | /* AGP registers */ |
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268 | |||
269 | #define PCI_AGP_VERSION 2 /* BCD version number */ |
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270 | #define PCI_AGP_RFU 3 /* Rest of capability flags */ |
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271 | #define PCI_AGP_STATUS 4 /* Status register */ |
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272 | #define PCI_AGP_STATUS_RQ_MASK 0xff000000 /* Maximum number of requests - 1 */ |
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273 | #define PCI_AGP_STATUS_SBA 0x0200 /* Sideband addressing supported */ |
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274 | #define PCI_AGP_STATUS_64BIT 0x0020 /* 64-bit addressing supported */ |
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275 | #define PCI_AGP_STATUS_FW 0x0010 /* FW transfers supported */ |
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276 | #define PCI_AGP_STATUS_RATE4 0x0004 /* 4x transfer rate supported */ |
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277 | #define PCI_AGP_STATUS_RATE2 0x0002 /* 2x transfer rate supported */ |
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278 | #define PCI_AGP_STATUS_RATE1 0x0001 /* 1x transfer rate supported */ |
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279 | #define PCI_AGP_COMMAND 8 /* Control register */ |
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280 | #define PCI_AGP_COMMAND_RQ_MASK 0xff000000 /* Master: Maximum number of requests */ |
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281 | #define PCI_AGP_COMMAND_SBA 0x0200 /* Sideband addressing enabled */ |
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282 | #define PCI_AGP_COMMAND_AGP 0x0100 /* Allow processing of AGP transactions */ |
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283 | #define PCI_AGP_COMMAND_64BIT 0x0020 /* Allow processing of 64-bit addresses */ |
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284 | #define PCI_AGP_COMMAND_FW 0x0010 /* Force FW transfers */ |
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285 | #define PCI_AGP_COMMAND_RATE4 0x0004 /* Use 4x rate */ |
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286 | #define PCI_AGP_COMMAND_RATE2 0x0002 /* Use 2x rate */ |
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287 | #define PCI_AGP_COMMAND_RATE1 0x0001 /* Use 1x rate */ |
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288 | #define PCI_AGP_SIZEOF 12 |
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289 | |||
290 | |||
1408 | serge | 291 | #define PCI_MAP_REG_START 0x10 |
292 | #define PCI_MAP_REG_END 0x28 |
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293 | #define PCI_MAP_ROM_REG 0x30 |
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294 | |||
295 | #define PCI_MAP_MEMORY 0x00000000 |
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296 | #define PCI_MAP_IO 0x00000001 |
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297 | |||
298 | #define PCI_MAP_MEMORY_TYPE 0x00000007 |
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299 | #define PCI_MAP_IO_TYPE 0x00000003 |
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300 | |||
301 | #define PCI_MAP_MEMORY_TYPE_32BIT 0x00000000 |
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302 | #define PCI_MAP_MEMORY_TYPE_32BIT_1M 0x00000002 |
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303 | #define PCI_MAP_MEMORY_TYPE_64BIT 0x00000004 |
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304 | #define PCI_MAP_MEMORY_TYPE_MASK 0x00000006 |
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305 | #define PCI_MAP_MEMORY_CACHABLE 0x00000008 |
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306 | #define PCI_MAP_MEMORY_ATTR_MASK 0x0000000e |
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307 | #define PCI_MAP_MEMORY_ADDRESS_MASK 0xfffffff0 |
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308 | |||
309 | #define PCI_MAP_IO_ATTR_MASK 0x00000003 |
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310 | |||
311 | |||
312 | |||
313 | #define PCI_MAP_IS_IO(b) ((b) & PCI_MAP_IO) |
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314 | #define PCI_MAP_IS_MEM(b) (!PCI_MAP_IS_IO(b)) |
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315 | |||
316 | #define PCI_MAP_IS64BITMEM(b) \ |
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317 | (((b) & PCI_MAP_MEMORY_TYPE_MASK) == PCI_MAP_MEMORY_TYPE_64BIT) |
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318 | |||
319 | #define PCIGETMEMORY(b) ((b) & PCI_MAP_MEMORY_ADDRESS_MASK) |
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320 | #define PCIGETMEMORY64HIGH(b) (*((CARD32*)&b + 1)) |
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321 | #define PCIGETMEMORY64(b) \ |
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322 | (PCIGETMEMORY(b) | ((CARD64)PCIGETMEMORY64HIGH(b) << 32)) |
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323 | |||
324 | #define PCI_MAP_IO_ADDRESS_MASK 0xfffffffc |
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325 | |||
326 | #define PCIGETIO(b) ((b) & PCI_MAP_IO_ADDRESS_MASK) |
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327 | |||
328 | #define PCI_MAP_ROM_DECODE_ENABLE 0x00000001 |
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329 | #define PCI_MAP_ROM_ADDRESS_MASK 0xfffff800 |
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330 | |||
331 | #define PCIGETROM(b) ((b) & PCI_MAP_ROM_ADDRESS_MASK) |
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332 | |||
333 | |||
334 | #ifndef PCI_DOM_MASK |
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335 | # define PCI_DOM_MASK 0x0ffu |
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336 | #endif |
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337 | #define PCI_DOMBUS_MASK (((PCI_DOM_MASK) << 8) | 0x0ffu) |
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338 | |||
339 | #define PCI_MAKE_TAG(b,d,f) ((((b) & (PCI_DOMBUS_MASK)) << 16) | \ |
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340 | (((d) & 0x00001fu) << 11) | \ |
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341 | (((f) & 0x000007u) << 8)) |
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342 | |||
343 | #define PCI_BUS_FROM_TAG(tag) (((tag) >> 16) & (PCI_DOMBUS_MASK)) |
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344 | #define PCI_DEV_FROM_TAG(tag) (((tag) & 0x0000f800u) >> 11) |
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345 | #define PCI_FUNC_FROM_TAG(tag) (((tag) & 0x00000700u) >> 8) |
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346 | #define PCI_DFN_FROM_TAG(tag) (((tag) & 0x0000ff00u) >> 8) |
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347 | |||
348 | #define PCI_DEVFN(slot, func) ((((slot) & 0x1f) << 3) | ((func) & 0x07)) |
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349 | #define PCI_SLOT(devfn) (((devfn) >> 3) & 0x1f) |
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350 | #define PCI_FUNC(devfn) ((devfn) & 0x07) |
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351 | |||
352 | |||
353 | |||
354 | typedef unsigned int PCITAG; |
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355 | |||
356 | extern inline PCITAG |
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357 | pciTag(int busnum, int devnum, int funcnum) |
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358 | { |
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359 | return(PCI_MAKE_TAG(busnum,devnum,funcnum)); |
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360 | } |
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361 | |||
1627 | serge | 362 | |
1964 | serge | 363 | struct resource |
364 | { |
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365 | resource_size_t start; |
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366 | resource_size_t end; |
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367 | // const char *name; |
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368 | unsigned long flags; |
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369 | // struct resource *parent, *sibling, *child; |
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370 | }; |
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371 | |||
1408 | serge | 372 | /* |
1964 | serge | 373 | * IO resources have these defined flags. |
1627 | serge | 374 | */ |
1964 | serge | 375 | #define IORESOURCE_BITS 0x000000ff /* Bus-specific bits */ |
1627 | serge | 376 | |
1964 | serge | 377 | #define IORESOURCE_IO 0x00000100 /* Resource type */ |
378 | #define IORESOURCE_MEM 0x00000200 |
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379 | #define IORESOURCE_IRQ 0x00000400 |
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380 | #define IORESOURCE_DMA 0x00000800 |
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1627 | serge | 381 | |
1964 | serge | 382 | #define IORESOURCE_PREFETCH 0x00001000 /* No side effects */ |
383 | #define IORESOURCE_READONLY 0x00002000 |
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384 | #define IORESOURCE_CACHEABLE 0x00004000 |
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385 | #define IORESOURCE_RANGELENGTH 0x00008000 |
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386 | #define IORESOURCE_SHADOWABLE 0x00010000 |
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387 | #define IORESOURCE_BUS_HAS_VGA 0x00080000 |
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1627 | serge | 388 | |
1964 | serge | 389 | #define IORESOURCE_DISABLED 0x10000000 |
390 | #define IORESOURCE_UNSET 0x20000000 |
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391 | #define IORESOURCE_AUTO 0x40000000 |
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392 | #define IORESOURCE_BUSY 0x80000000 /* Driver has marked this resource busy */ |
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1627 | serge | 393 | |
1964 | serge | 394 | /* ISA PnP IRQ specific bits (IORESOURCE_BITS) */ |
395 | #define IORESOURCE_IRQ_HIGHEDGE (1<<0) |
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396 | #define IORESOURCE_IRQ_LOWEDGE (1<<1) |
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397 | #define IORESOURCE_IRQ_HIGHLEVEL (1<<2) |
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398 | #define IORESOURCE_IRQ_LOWLEVEL (1<<3) |
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399 | #define IORESOURCE_IRQ_SHAREABLE (1<<4) |
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1627 | serge | 400 | |
1964 | serge | 401 | /* ISA PnP DMA specific bits (IORESOURCE_BITS) */ |
402 | #define IORESOURCE_DMA_TYPE_MASK (3<<0) |
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403 | #define IORESOURCE_DMA_8BIT (0<<0) |
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404 | #define IORESOURCE_DMA_8AND16BIT (1<<0) |
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405 | #define IORESOURCE_DMA_16BIT (2<<0) |
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1627 | serge | 406 | |
1964 | serge | 407 | #define IORESOURCE_DMA_MASTER (1<<2) |
408 | #define IORESOURCE_DMA_BYTE (1<<3) |
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409 | #define IORESOURCE_DMA_WORD (1<<4) |
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1627 | serge | 410 | |
1964 | serge | 411 | #define IORESOURCE_DMA_SPEED_MASK (3<<6) |
412 | #define IORESOURCE_DMA_COMPATIBLE (0<<6) |
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413 | #define IORESOURCE_DMA_TYPEA (1<<6) |
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414 | #define IORESOURCE_DMA_TYPEB (2<<6) |
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415 | #define IORESOURCE_DMA_TYPEF (3<<6) |
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1627 | serge | 416 | |
1964 | serge | 417 | /* ISA PnP memory I/O specific bits (IORESOURCE_BITS) */ |
418 | #define IORESOURCE_MEM_WRITEABLE (1<<0) /* dup: IORESOURCE_READONLY */ |
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419 | #define IORESOURCE_MEM_CACHEABLE (1<<1) /* dup: IORESOURCE_CACHEABLE */ |
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420 | #define IORESOURCE_MEM_RANGELENGTH (1<<2) /* dup: IORESOURCE_RANGELENGTH */ |
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421 | #define IORESOURCE_MEM_TYPE_MASK (3<<3) |
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422 | #define IORESOURCE_MEM_8BIT (0<<3) |
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423 | #define IORESOURCE_MEM_16BIT (1<<3) |
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424 | #define IORESOURCE_MEM_8AND16BIT (2<<3) |
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425 | #define IORESOURCE_MEM_32BIT (3<<3) |
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426 | #define IORESOURCE_MEM_SHADOWABLE (1<<5) /* dup: IORESOURCE_SHADOWABLE */ |
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427 | #define IORESOURCE_MEM_EXPANSIONROM (1<<6) |
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428 | |||
429 | /* PCI ROM control bits (IORESOURCE_BITS) */ |
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430 | #define IORESOURCE_ROM_ENABLE (1<<0) /* ROM is enabled, same as PCI_ROM_ADDRESS_ENABLE */ |
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431 | #define IORESOURCE_ROM_SHADOW (1<<1) /* ROM is copy at C000:0 */ |
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432 | #define IORESOURCE_ROM_COPY (1<<2) /* ROM is alloc'd copy, resource field overlaid */ |
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433 | #define IORESOURCE_ROM_BIOS_COPY (1<<3) /* ROM is BIOS copy, resource field overlaid */ |
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434 | |||
435 | /* PCI control bits. Shares IORESOURCE_BITS with above PCI ROM. */ |
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436 | #define IORESOURCE_PCI_FIXED (1<<4) /* Do not move resource */ |
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437 | |||
438 | |||
1627 | serge | 439 | /* |
1408 | serge | 440 | * For PCI devices, the region numbers are assigned this way: |
441 | * |
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442 | * 0-5 standard PCI regions |
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443 | * 6 expansion ROM |
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444 | * 7-10 bridges: address space assigned to buses behind the bridge |
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445 | */ |
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446 | |||
447 | #define PCI_ROM_RESOURCE 6 |
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448 | #define PCI_BRIDGE_RESOURCES 7 |
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449 | #define PCI_NUM_RESOURCES 11 |
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450 | |||
451 | #ifndef PCI_BUS_NUM_RESOURCES |
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452 | #define PCI_BUS_NUM_RESOURCES 8 |
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453 | #endif |
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454 | |||
455 | #define DEVICE_COUNT_RESOURCE 12 |
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456 | |||
457 | /* |
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458 | * The pci_dev structure is used to describe PCI devices. |
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459 | */ |
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460 | struct pci_dev { |
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1964 | serge | 461 | // struct list_head bus_list; /* node in per-bus list */ |
462 | // struct pci_bus *bus; /* bus this device is on */ |
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463 | // struct pci_bus *subordinate; /* bus this device bridges to */ |
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1408 | serge | 464 | |
1964 | serge | 465 | // void *sysdata; /* hook for sys-specific extension */ |
1408 | serge | 466 | // struct proc_dir_entry *procent; /* device entry in /proc/bus/pci */ |
1964 | serge | 467 | // struct pci_slot *slot; /* Physical slot this device is in */ |
468 | u32_t bus; |
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469 | u32_t devfn; /* encoded device & function index */ |
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470 | u16_t vendor; |
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471 | u16_t device; |
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472 | u16_t subsystem_vendor; |
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473 | u16_t subsystem_device; |
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474 | u32_t class; /* 3 bytes: (base,sub,prog-if) */ |
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475 | uint8_t revision; /* PCI revision, low byte of class word */ |
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476 | uint8_t hdr_type; /* PCI header type (`multi' flag masked out) */ |
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477 | uint8_t pcie_type; /* PCI-E device/port type */ |
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478 | uint8_t rom_base_reg; /* which config register controls the ROM */ |
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479 | uint8_t pin; /* which interrupt pin this device uses */ |
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1408 | serge | 480 | |
481 | // struct pci_driver *driver; /* which driver has allocated this device */ |
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1964 | serge | 482 | uint64_t dma_mask; /* Mask of the bits of bus address this |
1408 | serge | 483 | device implements. Normally this is |
484 | 0xffffffff. You only need to change |
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485 | this if your device has broken DMA |
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486 | or supports 64-bit transfers. */ |
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487 | |||
488 | // struct device_dma_parameters dma_parms; |
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489 | |||
1964 | serge | 490 | // pci_power_t current_state; /* Current operating state. In ACPI-speak, |
491 | // this is D0-D3, D0 being fully functional, |
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492 | // and D3 being off. */ |
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493 | // int pm_cap; /* PM capability offset in the |
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494 | // configuration space */ |
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1408 | serge | 495 | unsigned int pme_support:5; /* Bitmask of states from which PME# |
496 | can be generated */ |
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497 | unsigned int d1_support:1; /* Low power state D1 is supported */ |
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498 | unsigned int d2_support:1; /* Low power state D2 is supported */ |
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499 | unsigned int no_d1d2:1; /* Only allow D0 and D3 */ |
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500 | |||
1964 | serge | 501 | // pci_channel_state_t error_state; /* current connectivity state */ |
1430 | serge | 502 | struct device dev; /* Generic device interface */ |
1408 | serge | 503 | |
1964 | serge | 504 | // int cfg_size; /* Size of configuration space */ |
1870 | serge | 505 | |
1408 | serge | 506 | /* |
507 | * Instead of touching interrupt line and base address registers |
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508 | * directly, use the values stored here. They might be different! |
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509 | */ |
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510 | unsigned int irq; |
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511 | struct resource resource[DEVICE_COUNT_RESOURCE]; /* I/O and memory regions + expansion ROMs */ |
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512 | |||
513 | /* These fields are used by common fixups */ |
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514 | unsigned int transparent:1; /* Transparent PCI bridge */ |
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515 | unsigned int multifunction:1;/* Part of multi-function device */ |
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516 | /* keep track of device state */ |
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517 | unsigned int is_added:1; |
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518 | unsigned int is_busmaster:1; /* device is busmaster */ |
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519 | unsigned int no_msi:1; /* device may not use msi */ |
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520 | unsigned int block_ucfg_access:1; /* userspace config space access is blocked */ |
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521 | unsigned int broken_parity_status:1; /* Device generates false positive parity */ |
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522 | unsigned int irq_reroute_variant:2; /* device needs IRQ rerouting variant */ |
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523 | unsigned int msi_enabled:1; |
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524 | unsigned int msix_enabled:1; |
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525 | unsigned int ari_enabled:1; /* ARI forwarding */ |
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526 | unsigned int is_managed:1; |
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1964 | serge | 527 | unsigned int is_pcie:1; |
1408 | serge | 528 | unsigned int state_saved:1; |
529 | unsigned int is_physfn:1; |
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530 | unsigned int is_virtfn:1; |
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1964 | serge | 531 | // pci_dev_flags_t dev_flags; |
532 | // atomic_t enable_cnt; /* pci_enable_device has been called */ |
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1408 | serge | 533 | |
534 | // u32 saved_config_space[16]; /* config space saved at suspend time */ |
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535 | // struct hlist_head saved_cap_space; |
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536 | // struct bin_attribute *rom_attr; /* attribute descriptor for sysfs ROM entry */ |
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1964 | serge | 537 | // int rom_attr_enabled; /* has display of the rom attribute been enabled? */ |
1408 | serge | 538 | // struct bin_attribute *res_attr[DEVICE_COUNT_RESOURCE]; /* sysfs file for resources */ |
539 | // struct bin_attribute *res_attr_wc[DEVICE_COUNT_RESOURCE]; /* sysfs file for WC mapping of resources */ |
||
540 | }; |
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541 | |||
542 | #define pci_resource_start(dev, bar) ((dev)->resource[(bar)].start) |
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543 | #define pci_resource_end(dev, bar) ((dev)->resource[(bar)].end) |
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544 | #define pci_resource_flags(dev, bar) ((dev)->resource[(bar)].flags) |
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545 | #define pci_resource_len(dev,bar) \ |
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546 | ((pci_resource_start((dev), (bar)) == 0 && \ |
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547 | pci_resource_end((dev), (bar)) == \ |
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548 | pci_resource_start((dev), (bar))) ? 0 : \ |
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549 | \ |
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550 | (pci_resource_end((dev), (bar)) - \ |
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551 | pci_resource_start((dev), (bar)) + 1)) |
||
552 | |||
553 | |||
1964 | serge | 554 | |
555 | |||
1408 | serge | 556 | typedef struct |
557 | { |
||
558 | struct list_head link; |
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559 | struct pci_dev pci_dev; |
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560 | }pci_dev_t; |
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561 | |||
562 | int enum_pci_devices(void); |
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563 | |||
564 | struct pci_device_id* |
||
565 | find_pci_device(pci_dev_t* pdev, struct pci_device_id *idlist); |
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566 | |||
567 | #define DMA_BIT_MASK(n) (((n) == 64) ? ~0ULL : ((1ULL<<(n))-1)) |
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568 | |||
569 | int pci_set_dma_mask(struct pci_dev *dev, u64 mask); |
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570 | |||
571 | |||
1964 | serge | 572 | #define pci_name(x) "radeon" |
1631 | serge | 573 | |
1408 | serge | 574 | #endif //__PCI__H__(n))-1)) |
575 | |||
576 |