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Rev | Author | Line No. | Line |
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1408 | serge | 1 | |
1631 | serge | 2 | #define __PCI_H__ |
3 | |||
4 | |||
1408 | serge | 5 | #include |
6 | #include |
||
1631 | serge | 7 | #include |
1628 | serge | 8 | #include |
1631 | serge | 9 | |
1408 | serge | 10 | |
1628 | serge | 11 | struct pci_slot { |
12 | struct pci_bus *bus; /* The bus this slot is on */ |
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13 | struct list_head list; /* node in list of slots on this bus */ |
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14 | // struct hotplug_slot *hotplug; /* Hotplug info (migrate over time) */ |
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15 | unsigned char number; /* PCI_SLOT(pci_dev->devfn) */ |
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16 | // struct kobject kobj; |
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17 | }; |
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18 | |||
19 | |||
20 | |||
1408 | serge | 21 | |
22 | |||
23 | |||
24 | #define PCI_CLASS_NOT_DEFINED_VGA 0x0001 |
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25 | |||
26 | |||
27 | #define PCI_CLASS_STORAGE_SCSI 0x0100 |
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28 | #define PCI_CLASS_STORAGE_IDE 0x0101 |
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29 | #define PCI_CLASS_STORAGE_FLOPPY 0x0102 |
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30 | #define PCI_CLASS_STORAGE_IPI 0x0103 |
||
31 | #define PCI_CLASS_STORAGE_RAID 0x0104 |
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32 | #define PCI_CLASS_STORAGE_SATA 0x0106 |
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33 | #define PCI_CLASS_STORAGE_SATA_AHCI 0x010601 |
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34 | #define PCI_CLASS_STORAGE_SAS 0x0107 |
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35 | #define PCI_CLASS_STORAGE_OTHER 0x0180 |
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36 | |||
37 | |||
38 | #define PCI_CLASS_NETWORK_ETHERNET 0x0200 |
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39 | #define PCI_CLASS_NETWORK_TOKEN_RING 0x0201 |
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40 | #define PCI_CLASS_NETWORK_FDDI 0x0202 |
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41 | #define PCI_CLASS_NETWORK_ATM 0x0203 |
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42 | #define PCI_CLASS_NETWORK_OTHER 0x0280 |
||
43 | |||
44 | |||
45 | #define PCI_CLASS_DISPLAY_VGA 0x0300 |
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46 | #define PCI_CLASS_DISPLAY_XGA 0x0301 |
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47 | #define PCI_CLASS_DISPLAY_3D 0x0302 |
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48 | #define PCI_CLASS_DISPLAY_OTHER 0x0380 |
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49 | |||
50 | |||
51 | #define PCI_CLASS_MULTIMEDIA_VIDEO 0x0400 |
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52 | #define PCI_CLASS_MULTIMEDIA_AUDIO 0x0401 |
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53 | #define PCI_CLASS_MULTIMEDIA_PHONE 0x0402 |
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54 | #define PCI_CLASS_MULTIMEDIA_OTHER 0x0480 |
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55 | |||
56 | |||
57 | #define PCI_CLASS_MEMORY_RAM 0x0500 |
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58 | #define PCI_CLASS_MEMORY_FLASH 0x0501 |
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59 | #define PCI_CLASS_MEMORY_OTHER 0x0580 |
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60 | |||
61 | |||
62 | #define PCI_CLASS_BRIDGE_HOST 0x0600 |
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63 | #define PCI_CLASS_BRIDGE_ISA 0x0601 |
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64 | #define PCI_CLASS_BRIDGE_EISA 0x0602 |
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65 | #define PCI_CLASS_BRIDGE_MC 0x0603 |
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66 | #define PCI_CLASS_BRIDGE_PCI 0x0604 |
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67 | #define PCI_CLASS_BRIDGE_PCMCIA 0x0605 |
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68 | #define PCI_CLASS_BRIDGE_NUBUS 0x0606 |
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69 | #define PCI_CLASS_BRIDGE_CARDBUS 0x0607 |
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70 | #define PCI_CLASS_BRIDGE_RACEWAY 0x0608 |
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71 | #define PCI_CLASS_BRIDGE_OTHER 0x0680 |
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72 | |||
73 | |||
74 | #define PCI_CLASS_COMMUNICATION_SERIAL 0x0700 |
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75 | #define PCI_CLASS_COMMUNICATION_PARALLEL 0x0701 |
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76 | #define PCI_CLASS_COMMUNICATION_MULTISERIAL 0x0702 |
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77 | #define PCI_CLASS_COMMUNICATION_MODEM 0x0703 |
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78 | #define PCI_CLASS_COMMUNICATION_OTHER 0x0780 |
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79 | |||
80 | |||
81 | #define PCI_CLASS_SYSTEM_PIC 0x0800 |
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82 | #define PCI_CLASS_SYSTEM_PIC_IOAPIC 0x080010 |
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83 | #define PCI_CLASS_SYSTEM_PIC_IOXAPIC 0x080020 |
||
84 | #define PCI_CLASS_SYSTEM_DMA 0x0801 |
||
85 | #define PCI_CLASS_SYSTEM_TIMER 0x0802 |
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86 | #define PCI_CLASS_SYSTEM_RTC 0x0803 |
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87 | #define PCI_CLASS_SYSTEM_PCI_HOTPLUG 0x0804 |
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88 | #define PCI_CLASS_SYSTEM_SDHCI 0x0805 |
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89 | #define PCI_CLASS_SYSTEM_OTHER 0x0880 |
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90 | |||
91 | |||
92 | #define PCI_CLASS_INPUT_KEYBOARD 0x0900 |
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93 | #define PCI_CLASS_INPUT_PEN 0x0901 |
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94 | #define PCI_CLASS_INPUT_MOUSE 0x0902 |
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95 | #define PCI_CLASS_INPUT_SCANNER 0x0903 |
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96 | #define PCI_CLASS_INPUT_GAMEPORT 0x0904 |
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97 | #define PCI_CLASS_INPUT_OTHER 0x0980 |
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98 | |||
99 | |||
100 | #define PCI_CLASS_DOCKING_GENERIC 0x0a00 |
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101 | #define PCI_CLASS_DOCKING_OTHER 0x0a80 |
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102 | |||
103 | |||
104 | #define PCI_CLASS_PROCESSOR_386 0x0b00 |
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105 | #define PCI_CLASS_PROCESSOR_486 0x0b01 |
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106 | #define PCI_CLASS_PROCESSOR_PENTIUM 0x0b02 |
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107 | #define PCI_CLASS_PROCESSOR_ALPHA 0x0b10 |
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108 | #define PCI_CLASS_PROCESSOR_POWERPC 0x0b20 |
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109 | #define PCI_CLASS_PROCESSOR_MIPS 0x0b30 |
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110 | #define PCI_CLASS_PROCESSOR_CO 0x0b40 |
||
111 | |||
112 | |||
113 | #define PCI_CLASS_SERIAL_FIREWIRE 0x0c00 |
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114 | #define PCI_CLASS_SERIAL_FIREWIRE_OHCI 0x0c0010 |
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115 | #define PCI_CLASS_SERIAL_ACCESS 0x0c01 |
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116 | #define PCI_CLASS_SERIAL_SSA 0x0c02 |
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117 | #define PCI_CLASS_SERIAL_USB 0x0c03 |
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118 | #define PCI_CLASS_SERIAL_USB_UHCI 0x0c0300 |
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119 | #define PCI_CLASS_SERIAL_USB_OHCI 0x0c0310 |
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120 | #define PCI_CLASS_SERIAL_USB_EHCI 0x0c0320 |
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121 | #define PCI_CLASS_SERIAL_FIBER 0x0c04 |
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122 | #define PCI_CLASS_SERIAL_SMBUS 0x0c05 |
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123 | |||
124 | |||
125 | #define PCI_CLASS_WIRELESS_RF_CONTROLLER 0x0d10 |
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126 | #define PCI_CLASS_WIRELESS_WHCI 0x0d1010 |
||
127 | |||
128 | |||
129 | #define PCI_CLASS_INTELLIGENT_I2O 0x0e00 |
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130 | |||
131 | |||
132 | #define PCI_CLASS_SATELLITE_TV 0x0f00 |
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133 | #define PCI_CLASS_SATELLITE_AUDIO 0x0f01 |
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134 | #define PCI_CLASS_SATELLITE_VOICE 0x0f03 |
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135 | #define PCI_CLASS_SATELLITE_DATA 0x0f04 |
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136 | |||
137 | |||
138 | #define PCI_CLASS_CRYPT_NETWORK 0x1000 |
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139 | #define PCI_CLASS_CRYPT_ENTERTAINMENT 0x1001 |
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140 | #define PCI_CLASS_CRYPT_OTHER 0x1080 |
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141 | |||
142 | |||
143 | #define PCI_CLASS_SP_DPIO 0x1100 |
||
144 | #define PCI_CLASS_SP_OTHER 0x1180 |
||
145 | |||
146 | |||
147 | |||
148 | |||
149 | |||
150 | |||
151 | #define PCI_MAP_REG_END 0x28 |
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152 | #define PCI_MAP_ROM_REG 0x30 |
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153 | |||
154 | |||
155 | #define PCI_MAP_IO 0x00000001 |
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156 | |||
157 | |||
158 | #define PCI_MAP_IO_TYPE 0x00000003 |
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159 | |||
160 | |||
161 | #define PCI_MAP_MEMORY_TYPE_32BIT_1M 0x00000002 |
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162 | #define PCI_MAP_MEMORY_TYPE_64BIT 0x00000004 |
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163 | #define PCI_MAP_MEMORY_TYPE_MASK 0x00000006 |
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164 | #define PCI_MAP_MEMORY_CACHABLE 0x00000008 |
||
165 | #define PCI_MAP_MEMORY_ATTR_MASK 0x0000000e |
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166 | #define PCI_MAP_MEMORY_ADDRESS_MASK 0xfffffff0 |
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167 | |||
168 | |||
169 | |||
170 | |||
171 | |||
172 | |||
173 | #define PCI_MAP_IS_MEM(b) (!PCI_MAP_IS_IO(b)) |
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174 | |||
175 | |||
176 | (((b) & PCI_MAP_MEMORY_TYPE_MASK) == PCI_MAP_MEMORY_TYPE_64BIT) |
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177 | |||
178 | |||
179 | #define PCIGETMEMORY64HIGH(b) (*((CARD32*)&b + 1)) |
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180 | #define PCIGETMEMORY64(b) \ |
||
181 | (PCIGETMEMORY(b) | ((CARD64)PCIGETMEMORY64HIGH(b) << 32)) |
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182 | |||
183 | |||
184 | |||
185 | |||
186 | |||
187 | |||
188 | #define PCI_MAP_ROM_ADDRESS_MASK 0xfffff800 |
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189 | |||
190 | |||
191 | |||
192 | |||
193 | |||
194 | # define PCI_DOM_MASK 0x0ffu |
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195 | #endif |
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196 | #define PCI_DOMBUS_MASK (((PCI_DOM_MASK) << 8) | 0x0ffu) |
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197 | |||
198 | |||
199 | (((d) & 0x00001fu) << 11) | \ |
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200 | (((f) & 0x000007u) << 8)) |
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201 | |||
202 | |||
203 | #define PCI_DEV_FROM_TAG(tag) (((tag) & 0x0000f800u) >> 11) |
||
204 | #define PCI_FUNC_FROM_TAG(tag) (((tag) & 0x00000700u) >> 8) |
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205 | #define PCI_DFN_FROM_TAG(tag) (((tag) & 0x0000ff00u) >> 8) |
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206 | |||
207 | |||
208 | #define PCI_SLOT(devfn) (((devfn) >> 3) & 0x1f) |
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209 | #define PCI_FUNC(devfn) ((devfn) & 0x07) |
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210 | |||
211 | |||
1628 | serge | 212 | #define PCIIOC_BASE ('P' << 24 | 'C' << 16 | 'I' << 8) |
213 | #define PCIIOC_CONTROLLER (PCIIOC_BASE | 0x00) /* Get controller for PCI device. */ |
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214 | #define PCIIOC_MMAP_IS_IO (PCIIOC_BASE | 0x01) /* Set mmap state to I/O space. */ |
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215 | #define PCIIOC_MMAP_IS_MEM (PCIIOC_BASE | 0x02) /* Set mmap state to MEM space. */ |
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216 | #define PCIIOC_WRITE_COMBINE (PCIIOC_BASE | 0x03) /* Enable/disable write-combining. */ |
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217 | |||
1408 | serge | 218 | |
219 | |||
1628 | serge | 220 | |
221 | |||
222 | /* I/O channel is in normal state */ |
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223 | pci_channel_io_normal = (__force pci_channel_state_t) 1, |
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224 | |||
225 | |||
226 | pci_channel_io_frozen = (__force pci_channel_state_t) 2, |
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227 | |||
228 | |||
229 | pci_channel_io_perm_failure = (__force pci_channel_state_t) 3, |
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230 | }; |
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231 | |||
232 | |||
233 | |||
1408 | serge | 234 | |
235 | |||
236 | pciTag(int busnum, int devnum, int funcnum) |
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237 | { |
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238 | return(PCI_MAKE_TAG(busnum,devnum,funcnum)); |
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239 | } |
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240 | |||
241 | |||
1628 | serge | 242 | #define PCI_DMA_BIDIRECTIONAL 0 |
243 | #define PCI_DMA_TODEVICE 1 |
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244 | #define PCI_DMA_FROMDEVICE 2 |
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245 | #define PCI_DMA_NONE 3 |
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246 | |||
1627 | serge | 247 | |
1408 | serge | 248 | * For PCI devices, the region numbers are assigned this way: |
1627 | serge | 249 | */ |
250 | enum { |
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251 | /* #0-5: standard PCI resources */ |
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252 | PCI_STD_RESOURCES, |
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253 | PCI_STD_RESOURCE_END = 5, |
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254 | |||
255 | |||
256 | PCI_ROM_RESOURCE, |
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257 | |||
258 | |||
259 | #ifdef CONFIG_PCI_IOV |
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260 | PCI_IOV_RESOURCES, |
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261 | PCI_IOV_RESOURCE_END = PCI_IOV_RESOURCES + PCI_SRIOV_NUM_BARS - 1, |
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262 | #endif |
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263 | |||
264 | |||
265 | #define PCI_BRIDGE_RESOURCE_NUM 4 |
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266 | |||
267 | |||
268 | PCI_BRIDGE_RESOURCE_END = PCI_BRIDGE_RESOURCES + |
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269 | PCI_BRIDGE_RESOURCE_NUM - 1, |
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270 | |||
271 | |||
272 | PCI_NUM_RESOURCES, |
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273 | |||
274 | |||
275 | DEVICE_COUNT_RESOURCE |
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276 | }; |
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277 | |||
278 | |||
279 | |||
280 | * For PCI devices, the region numbers are assigned this way: |
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1408 | serge | 281 | * |
282 | * 0-5 standard PCI regions |
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283 | * 6 expansion ROM |
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284 | * 7-10 bridges: address space assigned to buses behind the bridge |
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285 | */ |
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286 | |||
287 | |||
288 | #define PCI_BRIDGE_RESOURCES 7 |
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289 | #define PCI_NUM_RESOURCES 11 |
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290 | |||
291 | |||
292 | #define PCI_BUS_NUM_RESOURCES 8 |
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293 | #endif |
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294 | |||
295 | |||
296 | |||
297 | |||
1628 | serge | 298 | |
299 | #define PCI_CFG_SPACE_EXP_SIZE 4096 |
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300 | |||
301 | |||
302 | |||
303 | |||
304 | |||
305 | #define PCI_D1 ((pci_power_t __force) 1) |
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306 | #define PCI_D2 ((pci_power_t __force) 2) |
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307 | #define PCI_D3hot ((pci_power_t __force) 3) |
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308 | #define PCI_D3cold ((pci_power_t __force) 4) |
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309 | #define PCI_UNKNOWN ((pci_power_t __force) 5) |
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310 | #define PCI_POWER_ERROR ((pci_power_t __force) -1) |
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311 | |||
312 | |||
1631 | serge | 313 | |
314 | pci_bar_unknown, /* Standard PCI BAR probe */ |
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315 | pci_bar_io, /* An io port BAR */ |
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316 | pci_bar_mem32, /* A 32-bit memory BAR */ |
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317 | pci_bar_mem64, /* A 64-bit memory BAR */ |
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318 | }; |
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319 | |||
320 | |||
1408 | serge | 321 | * The pci_dev structure is used to describe PCI devices. |
322 | */ |
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323 | struct pci_dev { |
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324 | struct list_head bus_list; /* node in per-bus list */ |
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1628 | serge | 325 | struct pci_bus *bus; /* bus this device is on */ |
326 | struct pci_bus *subordinate; /* bus this device bridges to */ |
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327 | |||
1408 | serge | 328 | |
1628 | serge | 329 | // struct proc_dir_entry *procent; /* device entry in /proc/bus/pci */ |
1408 | serge | 330 | struct pci_slot *slot; /* Physical slot this device is in */ |
1628 | serge | 331 | u32_t busnr; |
332 | unsigned int devfn; /* encoded device & function index */ |
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333 | unsigned short vendor; |
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334 | unsigned short device; |
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335 | unsigned short subsystem_vendor; |
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336 | unsigned short subsystem_device; |
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337 | unsigned int class; /* 3 bytes: (base,sub,prog-if) */ |
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338 | u8 revision; /* PCI revision, low byte of class word */ |
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339 | u8 hdr_type; /* PCI header type (`multi' flag masked out) */ |
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340 | u8 pcie_cap; /* PCI-E capability offset */ |
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341 | u8 pcie_type; /* PCI-E device/port type */ |
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342 | u8 rom_base_reg; /* which config register controls the ROM */ |
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343 | u8 pin; /* which interrupt pin this device uses */ |
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344 | |||
1408 | serge | 345 | |
346 | u64 dma_mask; /* Mask of the bits of bus address this |
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1628 | serge | 347 | device implements. Normally this is |
1408 | serge | 348 | 0xffffffff. You only need to change |
349 | this if your device has broken DMA |
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350 | or supports 64-bit transfers. */ |
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351 | |||
352 | |||
353 | |||
354 | |||
1628 | serge | 355 | this is D0-D3, D0 being fully functional, |
356 | and D3 being off. */ |
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357 | int pm_cap; /* PM capability offset in the |
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358 | configuration space */ |
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359 | unsigned int pme_support:5; /* Bitmask of states from which PME# |
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1408 | serge | 360 | can be generated */ |
361 | unsigned int pme_interrupt:1; |
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1628 | serge | 362 | unsigned int d1_support:1; /* Low power state D1 is supported */ |
1408 | serge | 363 | unsigned int d2_support:1; /* Low power state D2 is supported */ |
364 | unsigned int no_d1d2:1; /* Only allow D0 and D3 */ |
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365 | unsigned int mmio_always_on:1; /* disallow turning off io/mem |
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1628 | serge | 366 | decoding during bar sizing */ |
367 | unsigned int wakeup_prepared:1; |
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368 | unsigned int d3_delay; /* D3->D0 transition time in ms */ |
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369 | |||
1408 | serge | 370 | |
1628 | serge | 371 | struct device dev; /* Generic device interface */ |
1430 | serge | 372 | |
1408 | serge | 373 | |
1628 | serge | 374 | |
1408 | serge | 375 | |
376 | * Instead of touching interrupt line and base address registers |
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377 | * directly, use the values stored here. They might be different! |
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378 | */ |
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379 | unsigned int irq; |
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380 | struct resource resource[DEVICE_COUNT_RESOURCE]; /* I/O and memory regions + expansion ROMs */ |
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381 | |||
382 | |||
383 | unsigned int transparent:1; /* Transparent PCI bridge */ |
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384 | unsigned int multifunction:1;/* Part of multi-function device */ |
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385 | /* keep track of device state */ |
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386 | unsigned int is_added:1; |
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387 | unsigned int is_busmaster:1; /* device is busmaster */ |
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388 | unsigned int no_msi:1; /* device may not use msi */ |
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389 | unsigned int block_ucfg_access:1; /* userspace config space access is blocked */ |
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390 | unsigned int broken_parity_status:1; /* Device generates false positive parity */ |
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391 | unsigned int irq_reroute_variant:2; /* device needs IRQ rerouting variant */ |
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392 | unsigned int msi_enabled:1; |
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393 | unsigned int msix_enabled:1; |
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394 | unsigned int ari_enabled:1; /* ARI forwarding */ |
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395 | unsigned int is_managed:1; |
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396 | unsigned int is_pcie:1; /* Obsolete. Will be removed. |
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1628 | serge | 397 | Use pci_is_pcie() instead */ |
398 | unsigned int needs_freset:1; /* Dev requires fundamental reset */ |
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399 | unsigned int state_saved:1; |
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1408 | serge | 400 | unsigned int is_physfn:1; |
401 | unsigned int is_virtfn:1; |
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402 | unsigned int reset_fn:1; |
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1628 | serge | 403 | unsigned int is_hotplug_bridge:1; |
404 | unsigned int __aer_firmware_first_valid:1; |
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405 | unsigned int __aer_firmware_first:1; |
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406 | |||
1408 | serge | 407 | |
1628 | serge | 408 | |
1408 | serge | 409 | // struct hlist_head saved_cap_space; |
410 | // struct bin_attribute *rom_attr; /* attribute descriptor for sysfs ROM entry */ |
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411 | int rom_attr_enabled; /* has display of the rom attribute been enabled? */ |
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1631 | serge | 412 | // struct bin_attribute *res_attr[DEVICE_COUNT_RESOURCE]; /* sysfs file for resources */ |
1408 | serge | 413 | // struct bin_attribute *res_attr_wc[DEVICE_COUNT_RESOURCE]; /* sysfs file for WC mapping of resources */ |
414 | }; |
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415 | |||
416 | |||
417 | #define pci_resource_end(dev, bar) ((dev)->resource[(bar)].end) |
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418 | #define pci_resource_flags(dev, bar) ((dev)->resource[(bar)].flags) |
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419 | #define pci_resource_len(dev,bar) \ |
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420 | ((pci_resource_start((dev), (bar)) == 0 && \ |
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421 | pci_resource_end((dev), (bar)) == \ |
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422 | pci_resource_start((dev), (bar))) ? 0 : \ |
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423 | \ |
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424 | (pci_resource_end((dev), (bar)) - \ |
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425 | pci_resource_start((dev), (bar)) + 1)) |
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426 | |||
427 | |||
428 | { |
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429 | u16_t vendor, device; /* Vendor and device ID or PCI_ANY_ID*/ |
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430 | u16_t subvendor, subdevice; /* Subsystem ID's or PCI_ANY_ID */ |
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431 | u32_t class, class_mask; /* (class,subclass,prog-if) triplet */ |
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432 | u32_t driver_data; /* Data private to the driver */ |
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433 | }; |
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434 | |||
435 | |||
436 | { |
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437 | struct list_head link; |
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438 | struct pci_dev pci_dev; |
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439 | }pci_dev_t; |
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440 | |||
441 | |||
1627 | serge | 442 | |
443 | enum pci_bus_flags { |
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444 | PCI_BUS_FLAGS_NO_MSI = (__force pci_bus_flags_t) 1, |
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445 | PCI_BUS_FLAGS_NO_MMRBC = (__force pci_bus_flags_t) 2, |
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446 | }; |
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447 | |||
448 | |||
449 | { |
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450 | int domain; /* PCI domain */ |
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451 | int node; /* NUMA node */ |
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452 | #ifdef CONFIG_X86_64 |
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453 | void *iommu; /* IOMMU private data */ |
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454 | #endif |
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455 | }; |
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456 | |||
457 | |||
458 | |||
459 | |||
460 | { |
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461 | int (*read)(struct pci_bus *bus, unsigned int devfn, int where, int size, u32 *val); |
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462 | int (*write)(struct pci_bus *bus, unsigned int devfn, int where, int size, u32 val); |
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463 | }; |
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464 | |||
465 | |||
1628 | serge | 466 | * The first PCI_BRIDGE_RESOURCE_NUM PCI bus resources (those that correspond |
467 | * to P2P or CardBus bridge windows) go in a table. Additional ones (for |
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468 | * buses below host bridges or subtractive decode bridges) go in the list. |
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469 | * Use pci_bus_for_each_resource() to iterate through all the resources. |
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470 | */ |
||
471 | |||
1627 | serge | 472 | |
1628 | serge | 473 | * PCI_SUBTRACTIVE_DECODE means the bridge forwards the window implicitly |
474 | * and there's no way to program the bridge with the details of the window. |
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475 | * This does not apply to ACPI _CRS windows, even with the _DEC subtractive- |
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476 | * decode bit set, because they are explicit and can be programmed with _SRS. |
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477 | */ |
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478 | #define PCI_SUBTRACTIVE_DECODE 0x1 |
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479 | |||
480 | |||
481 | struct list_head list; |
||
482 | struct resource *res; |
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483 | unsigned int flags; |
||
484 | }; |
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485 | |||
486 | |||
487 | |||
488 | |||
1627 | serge | 489 | struct list_head node; /* node in list of buses */ |
490 | struct pci_bus *parent; /* parent bus this bridge is on */ |
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491 | struct list_head children; /* list of child buses */ |
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492 | struct list_head devices; /* list of devices on this bus */ |
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493 | struct pci_dev *self; /* bridge device as seen by parent */ |
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494 | struct list_head slots; /* list of slots on this bus */ |
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495 | struct resource *resource[PCI_BRIDGE_RESOURCE_NUM]; |
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496 | struct list_head resources; /* address space routed to this bus */ |
||
497 | |||
498 | |||
499 | void *sysdata; /* hook for sys-specific extension */ |
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500 | |||
501 | |||
502 | unsigned char primary; /* number of primary bridge */ |
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503 | unsigned char secondary; /* number of secondary bridge */ |
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504 | unsigned char subordinate; /* max number of subordinate buses */ |
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505 | |||
506 | |||
507 | |||
508 | |||
509 | pci_bus_flags_t bus_flags; /* Inherited by child busses */ |
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510 | // struct device *bridge; |
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511 | // struct device dev; |
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512 | // struct bin_attribute *legacy_io; /* legacy I/O for this bus */ |
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513 | // struct bin_attribute *legacy_mem; /* legacy mem */ |
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514 | unsigned int is_added:1; |
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515 | }; |
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516 | |||
517 | |||
518 | #define to_pci_bus(n) container_of(n, struct pci_bus, dev) |
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519 | #define pci_dev_b(n) list_entry(n, struct pci_dev, bus_list) |
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1628 | serge | 520 | #define to_pci_dev(n) container_of(n, struct pci_dev, dev) |
521 | #define for_each_pci_dev(d) while ((d = pci_get_device(PCI_ANY_ID, PCI_ANY_ID, d)) != NULL) |
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522 | |||
1627 | serge | 523 | |
524 | |||
525 | { |
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526 | struct pci_sysdata *sd = bus->sysdata; |
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527 | return sd->domain; |
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528 | } |
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529 | static inline bool pci_dev_msi_enabled(struct pci_dev *pci_dev) { return false; } |
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1628 | serge | 530 | |
1627 | serge | 531 | |
1628 | serge | 532 | * Error values that may be returned by PCI functions. |
533 | */ |
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534 | #define PCIBIOS_SUCCESSFUL 0x00 |
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535 | #define PCIBIOS_FUNC_NOT_SUPPORTED 0x81 |
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536 | #define PCIBIOS_BAD_VENDOR_ID 0x83 |
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537 | #define PCIBIOS_DEVICE_NOT_FOUND 0x86 |
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538 | #define PCIBIOS_BAD_REGISTER_NUMBER 0x87 |
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539 | #define PCIBIOS_SET_FAILED 0x88 |
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540 | #define PCIBIOS_BUFFER_TOO_SMALL 0x89 |
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541 | |||
1627 | serge | 542 | |
1628 | serge | 543 | |
544 | |||
545 | resource_size_t start; |
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546 | resource_size_t end; |
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547 | }; |
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548 | |||
549 | |||
550 | |||
551 | |||
552 | |||
553 | |||
554 | |||
1631 | serge | 555 | |
1628 | serge | 556 | |
557 | |||
1408 | serge | 558 | |
559 | |||
560 | find_pci_device(pci_dev_t* pdev, struct pci_device_id *idlist); |
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561 | |||
562 | |||
563 | |||
564 | |||
565 | |||
566 | |||
1627 | serge | 567 | struct pci_bus * pci_find_bus(int domain, int busnr); |
568 | int pci_find_capability(struct pci_dev *dev, int cap); |
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1628 | serge | 569 | int pci_find_next_capability(struct pci_dev *dev, u8 pos, int cap); |
570 | int pci_find_ext_capability(struct pci_dev *dev, int cap); |
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571 | int pci_bus_find_ext_capability(struct pci_bus *bus, unsigned int devfn, |
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572 | int cap); |
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573 | int pci_find_next_ht_capability(struct pci_dev *dev, int pos, int ht_cap); |
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574 | struct pci_bus * pci_find_next_bus(const struct pci_bus *from); |
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1627 | serge | 575 | unsigned int pci_scan_child_bus(struct pci_bus *bus); |
1631 | serge | 576 | void pcibios_fixup_bus(struct pci_bus *b); |
577 | |||
1408 | serge | 578 | |
1631 | serge | 579 | |
1628 | serge | 580 | { |
581 | return !(pbus->parent); |
||
582 | } |
||
583 | |||
1627 | serge | 584 | |
1628 | serge | 585 | * pci_pcie_cap - get the saved PCIe capability offset |
586 | * @dev: PCI device |
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587 | * |
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588 | * PCIe capability offset is calculated at PCI device initialization |
||
589 | * time and saved in the data structure. This function returns saved |
||
590 | * PCIe capability offset. Using this instead of pci_find_capability() |
||
591 | * reduces unnecessary search in the PCI configuration space. If you |
||
592 | * need to calculate PCIe capability offset from raw device for some |
||
593 | * reasons, please use pci_find_capability() instead. |
||
594 | */ |
||
595 | static inline int pci_pcie_cap(struct pci_dev *dev) |
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596 | { |
||
597 | return dev->pcie_cap; |
||
598 | } |
||
599 | |||
1627 | serge | 600 | |
1628 | serge | 601 | * pci_is_pcie - check if the PCI device is PCI Express capable |
602 | * @dev: PCI device |
||
603 | * |
||
604 | * Retrun true if the PCI device is PCI Express capable, false otherwise. |
||
605 | */ |
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606 | static inline bool pci_is_pcie(struct pci_dev *dev) |
||
607 | { |
||
608 | return !!pci_pcie_cap(dev); |
||
609 | } |
||
610 | |||
611 | |||
1631 | serge | 612 | |
613 | int pci_read_config_word(struct pci_dev *dev, int where, u16 *val); |
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614 | int pci_read_config_dword(struct pci_dev *dev, int where, u32 *val); |
||
615 | |||
616 | |||
617 | |||
618 | { |
||
619 | return -ENODEV; |
||
620 | } |
||
621 | static inline void pci_iov_release(struct pci_dev *dev) |
||
622 | |||
623 | |||
624 | } |
||
625 | static inline int pci_iov_resource_bar(struct pci_dev *dev, int resno, |
||
626 | enum pci_bar_type *type) |
||
627 | { |
||
628 | return 0; |
||
629 | } |
||
630 | static inline void pci_restore_iov_state(struct pci_dev *dev) |
||
631 | { |
||
632 | } |
||
633 | static inline int pci_iov_bus_range(struct pci_bus *bus) |
||
634 | { |
||
635 | return 0; |
||
636 | } |
||
637 | |||
638 | |||
639 | { |
||
640 | return -ENODEV; |
||
641 | } |
||
642 | static inline void pci_disable_ats(struct pci_dev *dev) |
||
643 | { |
||
644 | } |
||
645 | static inline int pci_ats_queue_depth(struct pci_dev *dev) |
||
646 | { |
||
647 | return -ENODEV; |
||
648 | } |
||
649 | static inline int pci_ats_enabled(struct pci_dev *dev) |
||
650 | { |
||
651 | return 0; |
||
652 | } |
||
653 | |||
654 | |||
1408 | serge | 655 | |
656 | |||
657 | |||
658 | |||
659 |