Rev 1408 | Rev 1627 | Go to most recent revision | Details | Compare with Previous | Last modification | View Log | RSS feed
Rev | Author | Line No. | Line |
---|---|---|---|
1408 | serge | 1 | |
2 | #include |
||
3 | |||
4 | |||
5 | #define __PCI_H__ |
||
6 | |||
7 | |||
8 | |||
9 | |||
10 | |||
11 | #define PCI_CLASS_NOT_DEFINED_VGA 0x0001 |
||
12 | |||
13 | |||
14 | #define PCI_CLASS_STORAGE_SCSI 0x0100 |
||
15 | #define PCI_CLASS_STORAGE_IDE 0x0101 |
||
16 | #define PCI_CLASS_STORAGE_FLOPPY 0x0102 |
||
17 | #define PCI_CLASS_STORAGE_IPI 0x0103 |
||
18 | #define PCI_CLASS_STORAGE_RAID 0x0104 |
||
19 | #define PCI_CLASS_STORAGE_SATA 0x0106 |
||
20 | #define PCI_CLASS_STORAGE_SATA_AHCI 0x010601 |
||
21 | #define PCI_CLASS_STORAGE_SAS 0x0107 |
||
22 | #define PCI_CLASS_STORAGE_OTHER 0x0180 |
||
23 | |||
24 | |||
25 | #define PCI_CLASS_NETWORK_ETHERNET 0x0200 |
||
26 | #define PCI_CLASS_NETWORK_TOKEN_RING 0x0201 |
||
27 | #define PCI_CLASS_NETWORK_FDDI 0x0202 |
||
28 | #define PCI_CLASS_NETWORK_ATM 0x0203 |
||
29 | #define PCI_CLASS_NETWORK_OTHER 0x0280 |
||
30 | |||
31 | |||
32 | #define PCI_CLASS_DISPLAY_VGA 0x0300 |
||
33 | #define PCI_CLASS_DISPLAY_XGA 0x0301 |
||
34 | #define PCI_CLASS_DISPLAY_3D 0x0302 |
||
35 | #define PCI_CLASS_DISPLAY_OTHER 0x0380 |
||
36 | |||
37 | |||
38 | #define PCI_CLASS_MULTIMEDIA_VIDEO 0x0400 |
||
39 | #define PCI_CLASS_MULTIMEDIA_AUDIO 0x0401 |
||
40 | #define PCI_CLASS_MULTIMEDIA_PHONE 0x0402 |
||
41 | #define PCI_CLASS_MULTIMEDIA_OTHER 0x0480 |
||
42 | |||
43 | |||
44 | #define PCI_CLASS_MEMORY_RAM 0x0500 |
||
45 | #define PCI_CLASS_MEMORY_FLASH 0x0501 |
||
46 | #define PCI_CLASS_MEMORY_OTHER 0x0580 |
||
47 | |||
48 | |||
49 | #define PCI_CLASS_BRIDGE_HOST 0x0600 |
||
50 | #define PCI_CLASS_BRIDGE_ISA 0x0601 |
||
51 | #define PCI_CLASS_BRIDGE_EISA 0x0602 |
||
52 | #define PCI_CLASS_BRIDGE_MC 0x0603 |
||
53 | #define PCI_CLASS_BRIDGE_PCI 0x0604 |
||
54 | #define PCI_CLASS_BRIDGE_PCMCIA 0x0605 |
||
55 | #define PCI_CLASS_BRIDGE_NUBUS 0x0606 |
||
56 | #define PCI_CLASS_BRIDGE_CARDBUS 0x0607 |
||
57 | #define PCI_CLASS_BRIDGE_RACEWAY 0x0608 |
||
58 | #define PCI_CLASS_BRIDGE_OTHER 0x0680 |
||
59 | |||
60 | |||
61 | #define PCI_CLASS_COMMUNICATION_SERIAL 0x0700 |
||
62 | #define PCI_CLASS_COMMUNICATION_PARALLEL 0x0701 |
||
63 | #define PCI_CLASS_COMMUNICATION_MULTISERIAL 0x0702 |
||
64 | #define PCI_CLASS_COMMUNICATION_MODEM 0x0703 |
||
65 | #define PCI_CLASS_COMMUNICATION_OTHER 0x0780 |
||
66 | |||
67 | |||
68 | #define PCI_CLASS_SYSTEM_PIC 0x0800 |
||
69 | #define PCI_CLASS_SYSTEM_PIC_IOAPIC 0x080010 |
||
70 | #define PCI_CLASS_SYSTEM_PIC_IOXAPIC 0x080020 |
||
71 | #define PCI_CLASS_SYSTEM_DMA 0x0801 |
||
72 | #define PCI_CLASS_SYSTEM_TIMER 0x0802 |
||
73 | #define PCI_CLASS_SYSTEM_RTC 0x0803 |
||
74 | #define PCI_CLASS_SYSTEM_PCI_HOTPLUG 0x0804 |
||
75 | #define PCI_CLASS_SYSTEM_SDHCI 0x0805 |
||
76 | #define PCI_CLASS_SYSTEM_OTHER 0x0880 |
||
77 | |||
78 | |||
79 | #define PCI_CLASS_INPUT_KEYBOARD 0x0900 |
||
80 | #define PCI_CLASS_INPUT_PEN 0x0901 |
||
81 | #define PCI_CLASS_INPUT_MOUSE 0x0902 |
||
82 | #define PCI_CLASS_INPUT_SCANNER 0x0903 |
||
83 | #define PCI_CLASS_INPUT_GAMEPORT 0x0904 |
||
84 | #define PCI_CLASS_INPUT_OTHER 0x0980 |
||
85 | |||
86 | |||
87 | #define PCI_CLASS_DOCKING_GENERIC 0x0a00 |
||
88 | #define PCI_CLASS_DOCKING_OTHER 0x0a80 |
||
89 | |||
90 | |||
91 | #define PCI_CLASS_PROCESSOR_386 0x0b00 |
||
92 | #define PCI_CLASS_PROCESSOR_486 0x0b01 |
||
93 | #define PCI_CLASS_PROCESSOR_PENTIUM 0x0b02 |
||
94 | #define PCI_CLASS_PROCESSOR_ALPHA 0x0b10 |
||
95 | #define PCI_CLASS_PROCESSOR_POWERPC 0x0b20 |
||
96 | #define PCI_CLASS_PROCESSOR_MIPS 0x0b30 |
||
97 | #define PCI_CLASS_PROCESSOR_CO 0x0b40 |
||
98 | |||
99 | |||
100 | #define PCI_CLASS_SERIAL_FIREWIRE 0x0c00 |
||
101 | #define PCI_CLASS_SERIAL_FIREWIRE_OHCI 0x0c0010 |
||
102 | #define PCI_CLASS_SERIAL_ACCESS 0x0c01 |
||
103 | #define PCI_CLASS_SERIAL_SSA 0x0c02 |
||
104 | #define PCI_CLASS_SERIAL_USB 0x0c03 |
||
105 | #define PCI_CLASS_SERIAL_USB_UHCI 0x0c0300 |
||
106 | #define PCI_CLASS_SERIAL_USB_OHCI 0x0c0310 |
||
107 | #define PCI_CLASS_SERIAL_USB_EHCI 0x0c0320 |
||
108 | #define PCI_CLASS_SERIAL_FIBER 0x0c04 |
||
109 | #define PCI_CLASS_SERIAL_SMBUS 0x0c05 |
||
110 | |||
111 | |||
112 | #define PCI_CLASS_WIRELESS_RF_CONTROLLER 0x0d10 |
||
113 | #define PCI_CLASS_WIRELESS_WHCI 0x0d1010 |
||
114 | |||
115 | |||
116 | #define PCI_CLASS_INTELLIGENT_I2O 0x0e00 |
||
117 | |||
118 | |||
119 | #define PCI_CLASS_SATELLITE_TV 0x0f00 |
||
120 | #define PCI_CLASS_SATELLITE_AUDIO 0x0f01 |
||
121 | #define PCI_CLASS_SATELLITE_VOICE 0x0f03 |
||
122 | #define PCI_CLASS_SATELLITE_DATA 0x0f04 |
||
123 | |||
124 | |||
125 | #define PCI_CLASS_CRYPT_NETWORK 0x1000 |
||
126 | #define PCI_CLASS_CRYPT_ENTERTAINMENT 0x1001 |
||
127 | #define PCI_CLASS_CRYPT_OTHER 0x1080 |
||
128 | |||
129 | |||
130 | #define PCI_CLASS_SP_DPIO 0x1100 |
||
131 | #define PCI_CLASS_SP_OTHER 0x1180 |
||
132 | |||
133 | |||
134 | |||
135 | |||
136 | |||
137 | * Under PCI, each device has 256 bytes of configuration address space, |
||
138 | * of which the first 64 bytes are standardized as follows: |
||
139 | */ |
||
140 | #define PCI_VENDOR_ID 0x000 /* 16 bits */ |
||
141 | #define PCI_DEVICE_ID 0x002 /* 16 bits */ |
||
142 | #define PCI_COMMAND 0x004 /* 16 bits */ |
||
143 | #define PCI_COMMAND_IO 0x001 /* Enable response in I/O space */ |
||
144 | #define PCI_COMMAND_MEMORY 0x002 /* Enable response in Memory space */ |
||
145 | #define PCI_COMMAND_MASTER 0x004 /* Enable bus mastering */ |
||
146 | #define PCI_COMMAND_SPECIAL 0x008 /* Enable response to special cycles */ |
||
147 | #define PCI_COMMAND_INVALIDATE 0x010 /* Use memory write and invalidate */ |
||
148 | #define PCI_COMMAND_VGA_PALETTE 0x020 /* Enable palette snooping */ |
||
149 | #define PCI_COMMAND_PARITY 0x040 /* Enable parity checking */ |
||
150 | #define PCI_COMMAND_WAIT 0x080 /* Enable address/data stepping */ |
||
151 | #define PCI_COMMAND_SERR 0x100 /* Enable SERR */ |
||
152 | #define PCI_COMMAND_FAST_BACK 0x200 /* Enable back-to-back writes */ |
||
153 | #define PCI_COMMAND_INTX_DISABLE 0x400 /* INTx Emulation Disable */ |
||
154 | |||
155 | |||
156 | #define PCI_STATUS_CAP_LIST 0x010 /* Support Capability List */ |
||
157 | #define PCI_STATUS_66MHZ 0x020 /* Support 66 Mhz PCI 2.1 bus */ |
||
158 | #define PCI_STATUS_UDF 0x040 /* Support User Definable Features [obsolete] */ |
||
159 | #define PCI_STATUS_FAST_BACK 0x080 /* Accept fast-back to back */ |
||
160 | #define PCI_STATUS_PARITY 0x100 /* Detected parity error */ |
||
161 | #define PCI_STATUS_DEVSEL_MASK 0x600 /* DEVSEL timing */ |
||
162 | #define PCI_STATUS_DEVSEL_FAST 0x000 |
||
163 | #define PCI_STATUS_DEVSEL_MEDIUM 0x200 |
||
164 | #define PCI_STATUS_DEVSEL_SLOW 0x400 |
||
165 | #define PCI_STATUS_SIG_TARGET_ABORT 0x800 /* Set on target abort */ |
||
166 | #define PCI_STATUS_REC_TARGET_ABORT 0x1000 /* Master ack of " */ |
||
167 | #define PCI_STATUS_REC_MASTER_ABORT 0x2000 /* Set on master abort */ |
||
168 | #define PCI_STATUS_SIG_SYSTEM_ERROR 0x4000 /* Set when we drive SERR */ |
||
169 | #define PCI_STATUS_DETECTED_PARITY 0x8000 /* Set on parity error */ |
||
170 | |||
171 | |||
172 | #define PCI_REVISION_ID 0x08 /* Revision ID */ |
||
173 | #define PCI_CLASS_PROG 0x09 /* Reg. Level Programming Interface */ |
||
174 | #define PCI_CLASS_DEVICE 0x0a /* Device class */ |
||
175 | |||
176 | |||
177 | #define PCI_LATENCY_TIMER 0x0d /* 8 bits */ |
||
178 | #define PCI_HEADER_TYPE 0x0e /* 8 bits */ |
||
179 | #define PCI_HEADER_TYPE_NORMAL 0 |
||
180 | #define PCI_HEADER_TYPE_BRIDGE 1 |
||
181 | #define PCI_HEADER_TYPE_CARDBUS 2 |
||
182 | |||
183 | |||
184 | #define PCI_BIST_CODE_MASK 0x0f /* Return result */ |
||
185 | #define PCI_BIST_START 0x40 /* 1 to start BIST, 2 secs or less */ |
||
186 | #define PCI_BIST_CAPABLE 0x80 /* 1 if BIST capable */ |
||
187 | |||
188 | |||
189 | * Base addresses specify locations in memory or I/O space. |
||
190 | * Decoded size can be determined by writing a value of |
||
191 | * 0xffffffff to the register, and reading it back. Only |
||
192 | * 1 bits are decoded. |
||
193 | */ |
||
194 | #define PCI_BASE_ADDRESS_0 0x10 /* 32 bits */ |
||
195 | #define PCI_BASE_ADDRESS_1 0x14 /* 32 bits [htype 0,1 only] */ |
||
196 | #define PCI_BASE_ADDRESS_2 0x18 /* 32 bits [htype 0 only] */ |
||
197 | #define PCI_BASE_ADDRESS_3 0x1c /* 32 bits */ |
||
198 | #define PCI_BASE_ADDRESS_4 0x20 /* 32 bits */ |
||
199 | #define PCI_BASE_ADDRESS_5 0x24 /* 32 bits */ |
||
200 | #define PCI_BASE_ADDRESS_SPACE 0x01 /* 0 = memory, 1 = I/O */ |
||
201 | #define PCI_BASE_ADDRESS_SPACE_IO 0x01 |
||
202 | #define PCI_BASE_ADDRESS_SPACE_MEMORY 0x00 |
||
203 | #define PCI_BASE_ADDRESS_MEM_TYPE_MASK 0x06 |
||
204 | #define PCI_BASE_ADDRESS_MEM_TYPE_32 0x00 /* 32 bit address */ |
||
205 | #define PCI_BASE_ADDRESS_MEM_TYPE_1M 0x02 /* Below 1M [obsolete] */ |
||
206 | #define PCI_BASE_ADDRESS_MEM_TYPE_64 0x04 /* 64 bit address */ |
||
207 | #define PCI_BASE_ADDRESS_MEM_PREFETCH 0x08 /* prefetchable? */ |
||
208 | #define PCI_BASE_ADDRESS_MEM_MASK (~0x0fUL) |
||
209 | #define PCI_BASE_ADDRESS_IO_MASK (~0x03UL) |
||
210 | /* bit 1 is reserved if address_space = 1 */ |
||
211 | |||
212 | |||
213 | |||
214 | |||
215 | #define PCI_CARDBUS_CIS 0x28 |
||
216 | #define PCI_SUBSYSTEM_VENDOR_ID 0x2c |
||
217 | #define PCI_SUBSYSTEM_ID 0x2e |
||
218 | #define PCI_ROM_ADDRESS 0x30 /* Bits 31..11 are address, 10..1 reserved */ |
||
219 | #define PCI_ROM_ADDRESS_ENABLE 0x01 |
||
220 | #define PCI_ROM_ADDRESS_MASK (~0x7ffUL) |
||
221 | |||
222 | |||
223 | #define PCI_INTERRUPT_PIN 0x3d /* 8 bits */ |
||
224 | |||
225 | |||
226 | |||
227 | #define PCI_CB_SUBSYSTEM_ID 0x42 |
||
228 | |||
229 | |||
230 | #define PCI_CB_CAPABILITY_LIST 0x14 |
||
231 | /* Capability lists */ |
||
232 | |||
233 | |||
234 | #define PCI_CAP_ID_PM 0x01 /* Power Management */ |
||
235 | #define PCI_CAP_ID_AGP 0x02 /* Accelerated Graphics Port */ |
||
236 | #define PCI_CAP_ID_VPD 0x03 /* Vital Product Data */ |
||
237 | #define PCI_CAP_ID_SLOTID 0x04 /* Slot Identification */ |
||
238 | #define PCI_CAP_ID_MSI 0x05 /* Message Signalled Interrupts */ |
||
239 | #define PCI_CAP_ID_CHSWP 0x06 /* CompactPCI HotSwap */ |
||
240 | #define PCI_CAP_ID_PCIX 0x07 /* PCI-X */ |
||
241 | #define PCI_CAP_ID_HT 0x08 /* HyperTransport */ |
||
242 | #define PCI_CAP_ID_VNDR 0x09 /* Vendor specific capability */ |
||
243 | #define PCI_CAP_ID_SHPC 0x0C /* PCI Standard Hot-Plug Controller */ |
||
244 | #define PCI_CAP_ID_EXP 0x10 /* PCI Express */ |
||
245 | #define PCI_CAP_ID_MSIX 0x11 /* MSI-X */ |
||
246 | #define PCI_CAP_LIST_NEXT 1 /* Next capability in the list */ |
||
247 | #define PCI_CAP_FLAGS 2 /* Capability defined flags (16 bits) */ |
||
248 | #define PCI_CAP_SIZEOF 4 |
||
249 | |||
250 | |||
251 | |||
252 | |||
253 | |||
254 | #define PCI_AGP_RFU 3 /* Rest of capability flags */ |
||
255 | #define PCI_AGP_STATUS 4 /* Status register */ |
||
256 | #define PCI_AGP_STATUS_RQ_MASK 0xff000000 /* Maximum number of requests - 1 */ |
||
257 | #define PCI_AGP_STATUS_SBA 0x0200 /* Sideband addressing supported */ |
||
258 | #define PCI_AGP_STATUS_64BIT 0x0020 /* 64-bit addressing supported */ |
||
259 | #define PCI_AGP_STATUS_FW 0x0010 /* FW transfers supported */ |
||
260 | #define PCI_AGP_STATUS_RATE4 0x0004 /* 4x transfer rate supported */ |
||
261 | #define PCI_AGP_STATUS_RATE2 0x0002 /* 2x transfer rate supported */ |
||
262 | #define PCI_AGP_STATUS_RATE1 0x0001 /* 1x transfer rate supported */ |
||
263 | #define PCI_AGP_COMMAND 8 /* Control register */ |
||
264 | #define PCI_AGP_COMMAND_RQ_MASK 0xff000000 /* Master: Maximum number of requests */ |
||
265 | #define PCI_AGP_COMMAND_SBA 0x0200 /* Sideband addressing enabled */ |
||
266 | #define PCI_AGP_COMMAND_AGP 0x0100 /* Allow processing of AGP transactions */ |
||
267 | #define PCI_AGP_COMMAND_64BIT 0x0020 /* Allow processing of 64-bit addresses */ |
||
268 | #define PCI_AGP_COMMAND_FW 0x0010 /* Force FW transfers */ |
||
269 | #define PCI_AGP_COMMAND_RATE4 0x0004 /* Use 4x rate */ |
||
270 | #define PCI_AGP_COMMAND_RATE2 0x0002 /* Use 2x rate */ |
||
271 | #define PCI_AGP_COMMAND_RATE1 0x0001 /* Use 1x rate */ |
||
272 | #define PCI_AGP_SIZEOF 12 |
||
273 | |||
274 | |||
275 | |||
276 | #define PCI_MAP_REG_END 0x28 |
||
277 | #define PCI_MAP_ROM_REG 0x30 |
||
278 | |||
279 | |||
280 | #define PCI_MAP_IO 0x00000001 |
||
281 | |||
282 | |||
283 | #define PCI_MAP_IO_TYPE 0x00000003 |
||
284 | |||
285 | |||
286 | #define PCI_MAP_MEMORY_TYPE_32BIT_1M 0x00000002 |
||
287 | #define PCI_MAP_MEMORY_TYPE_64BIT 0x00000004 |
||
288 | #define PCI_MAP_MEMORY_TYPE_MASK 0x00000006 |
||
289 | #define PCI_MAP_MEMORY_CACHABLE 0x00000008 |
||
290 | #define PCI_MAP_MEMORY_ATTR_MASK 0x0000000e |
||
291 | #define PCI_MAP_MEMORY_ADDRESS_MASK 0xfffffff0 |
||
292 | |||
293 | |||
294 | |||
295 | |||
296 | |||
297 | |||
298 | #define PCI_MAP_IS_MEM(b) (!PCI_MAP_IS_IO(b)) |
||
299 | |||
300 | |||
301 | (((b) & PCI_MAP_MEMORY_TYPE_MASK) == PCI_MAP_MEMORY_TYPE_64BIT) |
||
302 | |||
303 | |||
304 | #define PCIGETMEMORY64HIGH(b) (*((CARD32*)&b + 1)) |
||
305 | #define PCIGETMEMORY64(b) \ |
||
306 | (PCIGETMEMORY(b) | ((CARD64)PCIGETMEMORY64HIGH(b) << 32)) |
||
307 | |||
308 | |||
309 | |||
310 | |||
311 | |||
312 | |||
313 | #define PCI_MAP_ROM_ADDRESS_MASK 0xfffff800 |
||
314 | |||
315 | |||
316 | |||
317 | |||
318 | |||
319 | # define PCI_DOM_MASK 0x0ffu |
||
320 | #endif |
||
321 | #define PCI_DOMBUS_MASK (((PCI_DOM_MASK) << 8) | 0x0ffu) |
||
322 | |||
323 | |||
324 | (((d) & 0x00001fu) << 11) | \ |
||
325 | (((f) & 0x000007u) << 8)) |
||
326 | |||
327 | |||
328 | #define PCI_DEV_FROM_TAG(tag) (((tag) & 0x0000f800u) >> 11) |
||
329 | #define PCI_FUNC_FROM_TAG(tag) (((tag) & 0x00000700u) >> 8) |
||
330 | #define PCI_DFN_FROM_TAG(tag) (((tag) & 0x0000ff00u) >> 8) |
||
331 | |||
332 | |||
333 | #define PCI_SLOT(devfn) (((devfn) >> 3) & 0x1f) |
||
334 | #define PCI_FUNC(devfn) ((devfn) & 0x07) |
||
335 | |||
336 | |||
337 | |||
338 | |||
339 | |||
340 | |||
341 | pciTag(int busnum, int devnum, int funcnum) |
||
342 | { |
||
343 | return(PCI_MAKE_TAG(busnum,devnum,funcnum)); |
||
344 | } |
||
345 | |||
346 | |||
347 | |||
348 | { |
||
349 | resource_size_t start; |
||
350 | resource_size_t end; |
||
351 | // const char *name; |
||
352 | unsigned long flags; |
||
353 | // struct resource *parent, *sibling, *child; |
||
354 | }; |
||
355 | |||
356 | |||
357 | * IO resources have these defined flags. |
||
358 | */ |
||
359 | #define IORESOURCE_BITS 0x000000ff /* Bus-specific bits */ |
||
360 | |||
361 | |||
362 | #define IORESOURCE_MEM 0x00000200 |
||
363 | #define IORESOURCE_IRQ 0x00000400 |
||
364 | #define IORESOURCE_DMA 0x00000800 |
||
365 | |||
366 | |||
367 | #define IORESOURCE_READONLY 0x00002000 |
||
368 | #define IORESOURCE_CACHEABLE 0x00004000 |
||
369 | #define IORESOURCE_RANGELENGTH 0x00008000 |
||
370 | #define IORESOURCE_SHADOWABLE 0x00010000 |
||
371 | #define IORESOURCE_BUS_HAS_VGA 0x00080000 |
||
372 | |||
373 | |||
374 | #define IORESOURCE_UNSET 0x20000000 |
||
375 | #define IORESOURCE_AUTO 0x40000000 |
||
376 | #define IORESOURCE_BUSY 0x80000000 /* Driver has marked this resource busy */ |
||
377 | |||
378 | |||
379 | #define IORESOURCE_IRQ_HIGHEDGE (1<<0) |
||
380 | #define IORESOURCE_IRQ_LOWEDGE (1<<1) |
||
381 | #define IORESOURCE_IRQ_HIGHLEVEL (1<<2) |
||
382 | #define IORESOURCE_IRQ_LOWLEVEL (1<<3) |
||
383 | #define IORESOURCE_IRQ_SHAREABLE (1<<4) |
||
384 | |||
385 | |||
386 | #define IORESOURCE_DMA_TYPE_MASK (3<<0) |
||
387 | #define IORESOURCE_DMA_8BIT (0<<0) |
||
388 | #define IORESOURCE_DMA_8AND16BIT (1<<0) |
||
389 | #define IORESOURCE_DMA_16BIT (2<<0) |
||
390 | |||
391 | |||
392 | #define IORESOURCE_DMA_BYTE (1<<3) |
||
393 | #define IORESOURCE_DMA_WORD (1<<4) |
||
394 | |||
395 | |||
396 | #define IORESOURCE_DMA_COMPATIBLE (0<<6) |
||
397 | #define IORESOURCE_DMA_TYPEA (1<<6) |
||
398 | #define IORESOURCE_DMA_TYPEB (2<<6) |
||
399 | #define IORESOURCE_DMA_TYPEF (3<<6) |
||
400 | |||
401 | |||
402 | #define IORESOURCE_MEM_WRITEABLE (1<<0) /* dup: IORESOURCE_READONLY */ |
||
403 | #define IORESOURCE_MEM_CACHEABLE (1<<1) /* dup: IORESOURCE_CACHEABLE */ |
||
404 | #define IORESOURCE_MEM_RANGELENGTH (1<<2) /* dup: IORESOURCE_RANGELENGTH */ |
||
405 | #define IORESOURCE_MEM_TYPE_MASK (3<<3) |
||
406 | #define IORESOURCE_MEM_8BIT (0<<3) |
||
407 | #define IORESOURCE_MEM_16BIT (1<<3) |
||
408 | #define IORESOURCE_MEM_8AND16BIT (2<<3) |
||
409 | #define IORESOURCE_MEM_32BIT (3<<3) |
||
410 | #define IORESOURCE_MEM_SHADOWABLE (1<<5) /* dup: IORESOURCE_SHADOWABLE */ |
||
411 | #define IORESOURCE_MEM_EXPANSIONROM (1<<6) |
||
412 | |||
413 | |||
414 | #define IORESOURCE_ROM_ENABLE (1<<0) /* ROM is enabled, same as PCI_ROM_ADDRESS_ENABLE */ |
||
415 | #define IORESOURCE_ROM_SHADOW (1<<1) /* ROM is copy at C000:0 */ |
||
416 | #define IORESOURCE_ROM_COPY (1<<2) /* ROM is alloc'd copy, resource field overlaid */ |
||
417 | #define IORESOURCE_ROM_BIOS_COPY (1<<3) /* ROM is BIOS copy, resource field overlaid */ |
||
418 | |||
419 | |||
420 | #define IORESOURCE_PCI_FIXED (1<<4) /* Do not move resource */ |
||
421 | |||
422 | |||
423 | |||
424 | * For PCI devices, the region numbers are assigned this way: |
||
425 | * |
||
426 | * 0-5 standard PCI regions |
||
427 | * 6 expansion ROM |
||
428 | * 7-10 bridges: address space assigned to buses behind the bridge |
||
429 | */ |
||
430 | |||
431 | |||
432 | #define PCI_BRIDGE_RESOURCES 7 |
||
433 | #define PCI_NUM_RESOURCES 11 |
||
434 | |||
435 | |||
436 | #define PCI_BUS_NUM_RESOURCES 8 |
||
437 | #endif |
||
438 | |||
439 | |||
440 | |||
441 | |||
442 | * The pci_dev structure is used to describe PCI devices. |
||
443 | */ |
||
444 | struct pci_dev { |
||
445 | // struct list_head bus_list; /* node in per-bus list */ |
||
446 | // struct pci_bus *bus; /* bus this device is on */ |
||
447 | // struct pci_bus *subordinate; /* bus this device bridges to */ |
||
448 | |||
449 | |||
450 | // struct proc_dir_entry *procent; /* device entry in /proc/bus/pci */ |
||
451 | // struct pci_slot *slot; /* Physical slot this device is in */ |
||
452 | u32_t bus; |
||
453 | u32_t devfn; /* encoded device & function index */ |
||
454 | u16_t vendor; |
||
455 | u16_t device; |
||
456 | u16_t subsystem_vendor; |
||
457 | u16_t subsystem_device; |
||
458 | u32_t class; /* 3 bytes: (base,sub,prog-if) */ |
||
459 | uint8_t revision; /* PCI revision, low byte of class word */ |
||
460 | uint8_t hdr_type; /* PCI header type (`multi' flag masked out) */ |
||
461 | uint8_t pcie_type; /* PCI-E device/port type */ |
||
462 | uint8_t rom_base_reg; /* which config register controls the ROM */ |
||
463 | uint8_t pin; /* which interrupt pin this device uses */ |
||
464 | |||
465 | |||
466 | uint64_t dma_mask; /* Mask of the bits of bus address this |
||
467 | device implements. Normally this is |
||
468 | 0xffffffff. You only need to change |
||
469 | this if your device has broken DMA |
||
470 | or supports 64-bit transfers. */ |
||
471 | |||
472 | |||
473 | |||
474 | |||
475 | // this is D0-D3, D0 being fully functional, |
||
476 | // and D3 being off. */ |
||
477 | // int pm_cap; /* PM capability offset in the |
||
478 | // configuration space */ |
||
479 | unsigned int pme_support:5; /* Bitmask of states from which PME# |
||
480 | can be generated */ |
||
481 | unsigned int d1_support:1; /* Low power state D1 is supported */ |
||
482 | unsigned int d2_support:1; /* Low power state D2 is supported */ |
||
483 | unsigned int no_d1d2:1; /* Only allow D0 and D3 */ |
||
484 | |||
485 | |||
486 | struct device dev; /* Generic device interface */ |
||
1430 | serge | 487 | |
1408 | serge | 488 | |
489 | |||
490 | |||
491 | * Instead of touching interrupt line and base address registers |
||
492 | * directly, use the values stored here. They might be different! |
||
493 | */ |
||
494 | unsigned int irq; |
||
495 | struct resource resource[DEVICE_COUNT_RESOURCE]; /* I/O and memory regions + expansion ROMs */ |
||
496 | |||
497 | |||
498 | unsigned int transparent:1; /* Transparent PCI bridge */ |
||
499 | unsigned int multifunction:1;/* Part of multi-function device */ |
||
500 | /* keep track of device state */ |
||
501 | unsigned int is_added:1; |
||
502 | unsigned int is_busmaster:1; /* device is busmaster */ |
||
503 | unsigned int no_msi:1; /* device may not use msi */ |
||
504 | unsigned int block_ucfg_access:1; /* userspace config space access is blocked */ |
||
505 | unsigned int broken_parity_status:1; /* Device generates false positive parity */ |
||
506 | unsigned int irq_reroute_variant:2; /* device needs IRQ rerouting variant */ |
||
507 | unsigned int msi_enabled:1; |
||
508 | unsigned int msix_enabled:1; |
||
509 | unsigned int ari_enabled:1; /* ARI forwarding */ |
||
510 | unsigned int is_managed:1; |
||
511 | unsigned int is_pcie:1; |
||
512 | unsigned int state_saved:1; |
||
513 | unsigned int is_physfn:1; |
||
514 | unsigned int is_virtfn:1; |
||
515 | // pci_dev_flags_t dev_flags; |
||
516 | // atomic_t enable_cnt; /* pci_enable_device has been called */ |
||
517 | |||
518 | |||
519 | // struct hlist_head saved_cap_space; |
||
520 | // struct bin_attribute *rom_attr; /* attribute descriptor for sysfs ROM entry */ |
||
521 | // int rom_attr_enabled; /* has display of the rom attribute been enabled? */ |
||
522 | // struct bin_attribute *res_attr[DEVICE_COUNT_RESOURCE]; /* sysfs file for resources */ |
||
523 | // struct bin_attribute *res_attr_wc[DEVICE_COUNT_RESOURCE]; /* sysfs file for WC mapping of resources */ |
||
524 | }; |
||
525 | |||
526 | |||
527 | #define pci_resource_end(dev, bar) ((dev)->resource[(bar)].end) |
||
528 | #define pci_resource_flags(dev, bar) ((dev)->resource[(bar)].flags) |
||
529 | #define pci_resource_len(dev,bar) \ |
||
530 | ((pci_resource_start((dev), (bar)) == 0 && \ |
||
531 | pci_resource_end((dev), (bar)) == \ |
||
532 | pci_resource_start((dev), (bar))) ? 0 : \ |
||
533 | \ |
||
534 | (pci_resource_end((dev), (bar)) - \ |
||
535 | pci_resource_start((dev), (bar)) + 1)) |
||
536 | |||
537 | |||
538 | { |
||
539 | u16_t vendor, device; /* Vendor and device ID or PCI_ANY_ID*/ |
||
540 | u16_t subvendor, subdevice; /* Subsystem ID's or PCI_ANY_ID */ |
||
541 | u32_t class, class_mask; /* (class,subclass,prog-if) triplet */ |
||
542 | u32_t driver_data; /* Data private to the driver */ |
||
543 | }; |
||
544 | |||
545 | |||
546 | { |
||
547 | struct list_head link; |
||
548 | struct pci_dev pci_dev; |
||
549 | }pci_dev_t; |
||
550 | |||
551 | |||
552 | |||
553 | |||
554 | find_pci_device(pci_dev_t* pdev, struct pci_device_id *idlist); |
||
555 | |||
556 | |||
557 | |||
558 | |||
559 | |||
560 | |||
561 | |||
562 | |||
563 | |||
564 | |||
565 | |||
566 |