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1408 | serge | 1 | #ifndef _ASM_X86_BITOPS_H |
2 | #define _ASM_X86_BITOPS_H |
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3 | |||
4 | /* |
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5 | * Copyright 1992, Linus Torvalds. |
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6 | * |
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7 | * Note: inlines with more than a single statement should be marked |
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8 | * __always_inline to avoid problems with older gcc's inlining heuristics. |
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9 | */ |
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10 | |||
11 | #ifndef _LINUX_BITOPS_H |
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12 | #error only |
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13 | #endif |
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14 | |||
15 | #include |
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16 | #include |
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17 | |||
3031 | serge | 18 | #define BIT_64(n) (U64_C(1) << (n)) |
19 | |||
1408 | serge | 20 | /* |
21 | * These have to be done with inline assembly: that way the bit-setting |
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22 | * is guaranteed to be atomic. All bit operations return 0 if the bit |
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23 | * was cleared before the operation and != 0 if it was not. |
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24 | * |
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25 | * bit 0 is the LSB of addr; bit 32 is the LSB of (addr+1). |
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26 | */ |
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27 | |||
28 | #if __GNUC__ < 4 || (__GNUC__ == 4 && __GNUC_MINOR__ < 1) |
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29 | /* Technically wrong, but this avoids compilation errors on some gcc |
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30 | versions. */ |
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31 | #define BITOP_ADDR(x) "=m" (*(volatile long *) (x)) |
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32 | #else |
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33 | #define BITOP_ADDR(x) "+m" (*(volatile long *) (x)) |
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34 | #endif |
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35 | |||
36 | #define ADDR BITOP_ADDR(addr) |
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37 | |||
38 | /* |
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39 | * We do the locked ops that don't return the old value as |
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40 | * a mask operation on a byte. |
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41 | */ |
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42 | #define IS_IMMEDIATE(nr) (__builtin_constant_p(nr)) |
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43 | #define CONST_MASK_ADDR(nr, addr) BITOP_ADDR((void *)(addr) + ((nr)>>3)) |
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44 | #define CONST_MASK(nr) (1 << ((nr) & 7)) |
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45 | |||
46 | /** |
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47 | * set_bit - Atomically set a bit in memory |
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48 | * @nr: the bit to set |
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49 | * @addr: the address to start counting from |
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50 | * |
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51 | * This function is atomic and may not be reordered. See __set_bit() |
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52 | * if you do not require the atomic guarantees. |
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53 | * |
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54 | * Note: there are no guarantees that this function will not be reordered |
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55 | * on non x86 architectures, so if you are writing portable code, |
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56 | * make sure not to rely on its reordering guarantees. |
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57 | * |
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58 | * Note that @nr may be almost arbitrarily large; this function is not |
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59 | * restricted to acting on a single-word quantity. |
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60 | */ |
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61 | static __always_inline void |
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62 | set_bit(unsigned int nr, volatile unsigned long *addr) |
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63 | { |
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64 | if (IS_IMMEDIATE(nr)) { |
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65 | asm volatile(LOCK_PREFIX "orb %1,%0" |
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66 | : CONST_MASK_ADDR(nr, addr) |
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67 | : "iq" ((u8)CONST_MASK(nr)) |
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68 | : "memory"); |
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69 | } else { |
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70 | asm volatile(LOCK_PREFIX "bts %1,%0" |
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71 | : BITOP_ADDR(addr) : "Ir" (nr) : "memory"); |
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72 | } |
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73 | } |
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74 | |||
75 | /** |
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76 | * __set_bit - Set a bit in memory |
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77 | * @nr: the bit to set |
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78 | * @addr: the address to start counting from |
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79 | * |
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80 | * Unlike set_bit(), this function is non-atomic and may be reordered. |
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81 | * If it's called on the same region of memory simultaneously, the effect |
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82 | * may be that only one operation succeeds. |
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83 | */ |
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84 | static inline void __set_bit(int nr, volatile unsigned long *addr) |
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85 | { |
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86 | asm volatile("bts %1,%0" : ADDR : "Ir" (nr) : "memory"); |
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87 | } |
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88 | |||
89 | /** |
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90 | * clear_bit - Clears a bit in memory |
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91 | * @nr: Bit to clear |
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92 | * @addr: Address to start counting from |
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93 | * |
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94 | * clear_bit() is atomic and may not be reordered. However, it does |
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95 | * not contain a memory barrier, so if it is used for locking purposes, |
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96 | * you should call smp_mb__before_clear_bit() and/or smp_mb__after_clear_bit() |
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97 | * in order to ensure changes are visible on other processors. |
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98 | */ |
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99 | static __always_inline void |
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100 | clear_bit(int nr, volatile unsigned long *addr) |
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101 | { |
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102 | if (IS_IMMEDIATE(nr)) { |
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103 | asm volatile(LOCK_PREFIX "andb %1,%0" |
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104 | : CONST_MASK_ADDR(nr, addr) |
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105 | : "iq" ((u8)~CONST_MASK(nr))); |
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106 | } else { |
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107 | asm volatile(LOCK_PREFIX "btr %1,%0" |
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108 | : BITOP_ADDR(addr) |
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109 | : "Ir" (nr)); |
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110 | } |
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111 | } |
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112 | |||
113 | /* |
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114 | * clear_bit_unlock - Clears a bit in memory |
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115 | * @nr: Bit to clear |
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116 | * @addr: Address to start counting from |
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117 | * |
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118 | * clear_bit() is atomic and implies release semantics before the memory |
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119 | * operation. It can be used for an unlock. |
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120 | */ |
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121 | static inline void clear_bit_unlock(unsigned nr, volatile unsigned long *addr) |
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122 | { |
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123 | barrier(); |
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124 | clear_bit(nr, addr); |
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125 | } |
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126 | |||
127 | static inline void __clear_bit(int nr, volatile unsigned long *addr) |
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128 | { |
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129 | asm volatile("btr %1,%0" : ADDR : "Ir" (nr)); |
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130 | } |
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131 | |||
132 | /* |
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133 | * __clear_bit_unlock - Clears a bit in memory |
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134 | * @nr: Bit to clear |
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135 | * @addr: Address to start counting from |
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136 | * |
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137 | * __clear_bit() is non-atomic and implies release semantics before the memory |
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138 | * operation. It can be used for an unlock if no other CPUs can concurrently |
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139 | * modify other bits in the word. |
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140 | * |
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141 | * No memory barrier is required here, because x86 cannot reorder stores past |
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142 | * older loads. Same principle as spin_unlock. |
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143 | */ |
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144 | static inline void __clear_bit_unlock(unsigned nr, volatile unsigned long *addr) |
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145 | { |
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146 | barrier(); |
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147 | __clear_bit(nr, addr); |
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148 | } |
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149 | |||
150 | #define smp_mb__before_clear_bit() barrier() |
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151 | #define smp_mb__after_clear_bit() barrier() |
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152 | |||
153 | /** |
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154 | * __change_bit - Toggle a bit in memory |
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155 | * @nr: the bit to change |
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156 | * @addr: the address to start counting from |
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157 | * |
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158 | * Unlike change_bit(), this function is non-atomic and may be reordered. |
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159 | * If it's called on the same region of memory simultaneously, the effect |
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160 | * may be that only one operation succeeds. |
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161 | */ |
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162 | static inline void __change_bit(int nr, volatile unsigned long *addr) |
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163 | { |
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164 | asm volatile("btc %1,%0" : ADDR : "Ir" (nr)); |
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165 | } |
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166 | |||
167 | /** |
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168 | * change_bit - Toggle a bit in memory |
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169 | * @nr: Bit to change |
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170 | * @addr: Address to start counting from |
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171 | * |
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172 | * change_bit() is atomic and may not be reordered. |
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173 | * Note that @nr may be almost arbitrarily large; this function is not |
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174 | * restricted to acting on a single-word quantity. |
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175 | */ |
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176 | static inline void change_bit(int nr, volatile unsigned long *addr) |
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177 | { |
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178 | if (IS_IMMEDIATE(nr)) { |
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179 | asm volatile(LOCK_PREFIX "xorb %1,%0" |
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180 | : CONST_MASK_ADDR(nr, addr) |
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181 | : "iq" ((u8)CONST_MASK(nr))); |
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182 | } else { |
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183 | asm volatile(LOCK_PREFIX "btc %1,%0" |
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184 | : BITOP_ADDR(addr) |
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185 | : "Ir" (nr)); |
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186 | } |
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187 | } |
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188 | |||
189 | /** |
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190 | * test_and_set_bit - Set a bit and return its old value |
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191 | * @nr: Bit to set |
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192 | * @addr: Address to count from |
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193 | * |
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194 | * This operation is atomic and cannot be reordered. |
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195 | * It also implies a memory barrier. |
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196 | */ |
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197 | static inline int test_and_set_bit(int nr, volatile unsigned long *addr) |
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198 | { |
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199 | int oldbit; |
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200 | |||
201 | asm volatile(LOCK_PREFIX "bts %2,%1\n\t" |
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202 | "sbb %0,%0" : "=r" (oldbit), ADDR : "Ir" (nr) : "memory"); |
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203 | |||
204 | return oldbit; |
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205 | } |
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206 | |||
207 | /** |
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208 | * test_and_set_bit_lock - Set a bit and return its old value for lock |
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209 | * @nr: Bit to set |
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210 | * @addr: Address to count from |
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211 | * |
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212 | * This is the same as test_and_set_bit on x86. |
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213 | */ |
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214 | static __always_inline int |
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215 | test_and_set_bit_lock(int nr, volatile unsigned long *addr) |
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216 | { |
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217 | return test_and_set_bit(nr, addr); |
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218 | } |
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219 | |||
220 | /** |
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221 | * __test_and_set_bit - Set a bit and return its old value |
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222 | * @nr: Bit to set |
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223 | * @addr: Address to count from |
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224 | * |
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225 | * This operation is non-atomic and can be reordered. |
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226 | * If two examples of this operation race, one can appear to succeed |
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227 | * but actually fail. You must protect multiple accesses with a lock. |
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228 | */ |
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229 | static inline int __test_and_set_bit(int nr, volatile unsigned long *addr) |
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230 | { |
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231 | int oldbit; |
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232 | |||
233 | asm("bts %2,%1\n\t" |
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234 | "sbb %0,%0" |
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235 | : "=r" (oldbit), ADDR |
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236 | : "Ir" (nr)); |
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237 | return oldbit; |
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238 | } |
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239 | |||
240 | /** |
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241 | * test_and_clear_bit - Clear a bit and return its old value |
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242 | * @nr: Bit to clear |
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243 | * @addr: Address to count from |
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244 | * |
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245 | * This operation is atomic and cannot be reordered. |
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246 | * It also implies a memory barrier. |
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247 | */ |
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248 | static inline int test_and_clear_bit(int nr, volatile unsigned long *addr) |
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249 | { |
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250 | int oldbit; |
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251 | |||
252 | asm volatile(LOCK_PREFIX "btr %2,%1\n\t" |
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253 | "sbb %0,%0" |
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254 | : "=r" (oldbit), ADDR : "Ir" (nr) : "memory"); |
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255 | |||
256 | return oldbit; |
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257 | } |
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258 | |||
259 | /** |
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260 | * __test_and_clear_bit - Clear a bit and return its old value |
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261 | * @nr: Bit to clear |
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262 | * @addr: Address to count from |
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263 | * |
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264 | * This operation is non-atomic and can be reordered. |
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265 | * If two examples of this operation race, one can appear to succeed |
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266 | * but actually fail. You must protect multiple accesses with a lock. |
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3031 | serge | 267 | * |
268 | * Note: the operation is performed atomically with respect to |
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269 | * the local CPU, but not other CPUs. Portable code should not |
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270 | * rely on this behaviour. |
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271 | * KVM relies on this behaviour on x86 for modifying memory that is also |
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272 | * accessed from a hypervisor on the same CPU if running in a VM: don't change |
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273 | * this without also updating arch/x86/kernel/kvm.c |
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1408 | serge | 274 | */ |
275 | static inline int __test_and_clear_bit(int nr, volatile unsigned long *addr) |
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276 | { |
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277 | int oldbit; |
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278 | |||
279 | asm volatile("btr %2,%1\n\t" |
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280 | "sbb %0,%0" |
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281 | : "=r" (oldbit), ADDR |
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282 | : "Ir" (nr)); |
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283 | return oldbit; |
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284 | } |
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285 | |||
286 | /* WARNING: non atomic and it can be reordered! */ |
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287 | static inline int __test_and_change_bit(int nr, volatile unsigned long *addr) |
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288 | { |
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289 | int oldbit; |
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290 | |||
291 | asm volatile("btc %2,%1\n\t" |
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292 | "sbb %0,%0" |
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293 | : "=r" (oldbit), ADDR |
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294 | : "Ir" (nr) : "memory"); |
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295 | |||
296 | return oldbit; |
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297 | } |
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298 | |||
299 | /** |
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300 | * test_and_change_bit - Change a bit and return its old value |
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301 | * @nr: Bit to change |
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302 | * @addr: Address to count from |
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303 | * |
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304 | * This operation is atomic and cannot be reordered. |
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305 | * It also implies a memory barrier. |
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306 | */ |
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307 | static inline int test_and_change_bit(int nr, volatile unsigned long *addr) |
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308 | { |
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309 | int oldbit; |
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310 | |||
311 | asm volatile(LOCK_PREFIX "btc %2,%1\n\t" |
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312 | "sbb %0,%0" |
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313 | : "=r" (oldbit), ADDR : "Ir" (nr) : "memory"); |
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314 | |||
315 | return oldbit; |
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316 | } |
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317 | |||
318 | static __always_inline int constant_test_bit(unsigned int nr, const volatile unsigned long *addr) |
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319 | { |
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320 | return ((1UL << (nr % BITS_PER_LONG)) & |
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3031 | serge | 321 | (addr[nr / BITS_PER_LONG])) != 0; |
1408 | serge | 322 | } |
323 | |||
324 | static inline int variable_test_bit(int nr, volatile const unsigned long *addr) |
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325 | { |
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326 | int oldbit; |
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327 | |||
328 | asm volatile("bt %2,%1\n\t" |
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329 | "sbb %0,%0" |
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330 | : "=r" (oldbit) |
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331 | : "m" (*(unsigned long *)addr), "Ir" (nr)); |
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332 | |||
333 | return oldbit; |
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334 | } |
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335 | |||
336 | #if 0 /* Fool kernel-doc since it doesn't do macros yet */ |
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337 | /** |
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338 | * test_bit - Determine whether a bit is set |
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339 | * @nr: bit number to test |
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340 | * @addr: Address to start counting from |
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341 | */ |
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342 | static int test_bit(int nr, const volatile unsigned long *addr); |
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343 | #endif |
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344 | |||
345 | #define test_bit(nr, addr) \ |
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346 | (__builtin_constant_p((nr)) \ |
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347 | ? constant_test_bit((nr), (addr)) \ |
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348 | : variable_test_bit((nr), (addr))) |
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349 | |||
350 | /** |
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351 | * __ffs - find first set bit in word |
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352 | * @word: The word to search |
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353 | * |
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354 | * Undefined if no bit exists, so code should check against 0 first. |
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355 | */ |
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356 | static inline unsigned long __ffs(unsigned long word) |
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357 | { |
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3031 | serge | 358 | asm("rep; bsf %1,%0" |
1408 | serge | 359 | : "=r" (word) |
360 | : "rm" (word)); |
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361 | return word; |
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362 | } |
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363 | |||
364 | /** |
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365 | * ffz - find first zero bit in word |
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366 | * @word: The word to search |
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367 | * |
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368 | * Undefined if no zero exists, so code should check against ~0UL first. |
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369 | */ |
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370 | static inline unsigned long ffz(unsigned long word) |
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371 | { |
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3031 | serge | 372 | asm("rep; bsf %1,%0" |
1408 | serge | 373 | : "=r" (word) |
374 | : "r" (~word)); |
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375 | return word; |
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376 | } |
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377 | |||
378 | /* |
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379 | * __fls: find last set bit in word |
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380 | * @word: The word to search |
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381 | * |
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382 | * Undefined if no set bit exists, so code should check against 0 first. |
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383 | */ |
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384 | static inline unsigned long __fls(unsigned long word) |
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385 | { |
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386 | asm("bsr %1,%0" |
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387 | : "=r" (word) |
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388 | : "rm" (word)); |
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389 | return word; |
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390 | } |
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391 | |||
3031 | serge | 392 | #undef ADDR |
393 | |||
1408 | serge | 394 | #ifdef __KERNEL__ |
395 | /** |
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396 | * ffs - find first set bit in word |
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397 | * @x: the word to search |
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398 | * |
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399 | * This is defined the same way as the libc and compiler builtin ffs |
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400 | * routines, therefore differs in spirit from the other bitops. |
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401 | * |
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402 | * ffs(value) returns 0 if value is 0 or the position of the first |
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403 | * set bit if value is nonzero. The first (least significant) bit |
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404 | * is at position 1. |
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405 | */ |
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406 | static inline int ffs(int x) |
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407 | { |
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408 | int r; |
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409 | #ifdef CONFIG_X86_CMOV |
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410 | asm("bsfl %1,%0\n\t" |
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411 | "cmovzl %2,%0" |
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3031 | serge | 412 | : "=&r" (r) : "rm" (x), "r" (-1)); |
1408 | serge | 413 | #else |
414 | asm("bsfl %1,%0\n\t" |
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415 | "jnz 1f\n\t" |
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416 | "movl $-1,%0\n" |
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417 | "1:" : "=r" (r) : "rm" (x)); |
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418 | #endif |
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419 | return r + 1; |
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420 | } |
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421 | |||
422 | /** |
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423 | * fls - find last set bit in word |
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424 | * @x: the word to search |
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425 | * |
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426 | * This is defined in a similar way as the libc and compiler builtin |
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427 | * ffs, but returns the position of the most significant set bit. |
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428 | * |
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429 | * fls(value) returns 0 if value is 0 or the position of the last |
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430 | * set bit if value is nonzero. The last (most significant) bit is |
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431 | * at position 32. |
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432 | */ |
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433 | static inline int fls(int x) |
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434 | { |
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435 | int r; |
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436 | #ifdef CONFIG_X86_CMOV |
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437 | asm("bsrl %1,%0\n\t" |
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438 | "cmovzl %2,%0" |
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439 | : "=&r" (r) : "rm" (x), "rm" (-1)); |
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440 | #else |
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441 | asm("bsrl %1,%0\n\t" |
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442 | "jnz 1f\n\t" |
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443 | "movl $-1,%0\n" |
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444 | "1:" : "=r" (r) : "rm" (x)); |
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445 | #endif |
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446 | return r + 1; |
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447 | } |
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448 | #endif /* __KERNEL__ */ |
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449 | |||
450 | #undef ADDR |
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451 | |||
452 | #ifdef __KERNEL__ |
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453 | |||
454 | #include |
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455 | |||
456 | #define ARCH_HAS_FAST_MULTIPLIER 1 |
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457 | |||
458 | #include |
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459 | |||
460 | #endif /* __KERNEL__ */ |
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461 | |||
462 | #include |
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463 | |||
464 | #ifdef __KERNEL__ |
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465 | |||
466 | #include |
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467 | |||
468 | #define ext2_set_bit_atomic(lock, nr, addr) \ |
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469 | test_and_set_bit((nr), (unsigned long *)(addr)) |
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470 | #define ext2_clear_bit_atomic(lock, nr, addr) \ |
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471 | test_and_clear_bit((nr), (unsigned long *)(addr)) |
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472 | |||
473 | #include |
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474 | |||
475 | #endif /* __KERNEL__ */ |
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476 | #endif /* _ASM_X86_BITOPS_H */><>><>>>><> |