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1408 serge 1
/**
2
 * \file drm.h
3
 * Header for the Direct Rendering Manager
4
 *
5
 * \author Rickard E. (Rik) Faith 
6
 *
7
 * \par Acknowledgments:
8
 * Dec 1999, Richard Henderson , move to generic \c cmpxchg.
9
 */
10
 
11
/*
12
 * Copyright 1999 Precision Insight, Inc., Cedar Park, Texas.
13
 * Copyright 2000 VA Linux Systems, Inc., Sunnyvale, California.
14
 * All rights reserved.
15
 *
16
 * Permission is hereby granted, free of charge, to any person obtaining a
17
 * copy of this software and associated documentation files (the "Software"),
18
 * to deal in the Software without restriction, including without limitation
19
 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
20
 * and/or sell copies of the Software, and to permit persons to whom the
21
 * Software is furnished to do so, subject to the following conditions:
22
 *
23
 * The above copyright notice and this permission notice (including the next
24
 * paragraph) shall be included in all copies or substantial portions of the
25
 * Software.
26
 *
27
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
28
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
29
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
30
 * VA LINUX SYSTEMS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
31
 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
32
 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
33
 * OTHER DEALINGS IN THE SOFTWARE.
34
 */
35
 
36
#ifndef _DRM_H_
37
#define _DRM_H_
38
 
39
#include 
40
#include 
41
typedef unsigned int drm_handle_t;
42
 
43
//#include      /* For _IO* macros */
44
 
45
#define DRM_MAJOR       226
46
#define DRM_MAX_MINOR   15
47
 
48
#define DRM_NAME	"drm"	  /**< Name in kernel, /dev, and /proc */
49
#define DRM_MIN_ORDER	5	  /**< At least 2^5 bytes = 32 bytes */
50
#define DRM_MAX_ORDER	22	  /**< Up to 2^22 bytes = 4MB */
51
#define DRM_RAM_PERCENT 10	  /**< How much system ram can we lock? */
52
 
53
#define _DRM_LOCK_HELD	0x80000000U /**< Hardware lock is held */
54
#define _DRM_LOCK_CONT	0x40000000U /**< Hardware lock is contended */
55
#define _DRM_LOCK_IS_HELD(lock)	   ((lock) & _DRM_LOCK_HELD)
56
#define _DRM_LOCK_IS_CONT(lock)	   ((lock) & _DRM_LOCK_CONT)
57
#define _DRM_LOCKING_CONTEXT(lock) ((lock) & ~(_DRM_LOCK_HELD|_DRM_LOCK_CONT))
58
 
59
typedef unsigned int drm_context_t;
60
typedef unsigned int drm_drawable_t;
61
typedef unsigned int drm_magic_t;
62
 
63
/**
64
 * Cliprect.
65
 *
66
 * \warning: If you change this structure, make sure you change
67
 * XF86DRIClipRectRec in the server as well
68
 *
69
 * \note KW: Actually it's illegal to change either for
70
 * backwards-compatibility reasons.
71
 */
72
struct drm_clip_rect {
73
	unsigned short x1;
74
	unsigned short y1;
75
	unsigned short x2;
76
	unsigned short y2;
77
};
78
 
79
/**
80
 * Drawable information.
81
 */
82
struct drm_drawable_info {
83
	unsigned int num_rects;
84
	struct drm_clip_rect *rects;
85
};
86
 
87
/**
88
 * Texture region,
89
 */
90
struct drm_tex_region {
91
	unsigned char next;
92
	unsigned char prev;
93
	unsigned char in_use;
94
	unsigned char padding;
95
	unsigned int age;
96
};
97
 
98
/**
99
 * Hardware lock.
100
 *
101
 * The lock structure is a simple cache-line aligned integer.  To avoid
102
 * processor bus contention on a multiprocessor system, there should not be any
103
 * other data stored in the same cache line.
104
 */
105
struct drm_hw_lock {
106
	__volatile__ unsigned int lock;		/**< lock variable */
107
	char padding[60];			/**< Pad to cache line */
108
};
109
 
110
/**
111
 * DRM_IOCTL_VERSION ioctl argument type.
112
 *
113
 * \sa drmGetVersion().
114
 */
115
struct drm_version {
116
	int version_major;	  /**< Major version */
117
	int version_minor;	  /**< Minor version */
118
	int version_patchlevel;	  /**< Patch level */
119
	size_t name_len;	  /**< Length of name buffer */
120
	char __user *name;	  /**< Name of driver */
121
	size_t date_len;	  /**< Length of date buffer */
122
	char __user *date;	  /**< User-space buffer to hold date */
123
	size_t desc_len;	  /**< Length of desc buffer */
124
	char __user *desc;	  /**< User-space buffer to hold desc */
125
};
126
 
127
/**
128
 * DRM_IOCTL_GET_UNIQUE ioctl argument type.
129
 *
130
 * \sa drmGetBusid() and drmSetBusId().
131
 */
132
struct drm_unique {
133
	size_t unique_len;	  /**< Length of unique */
134
	char __user *unique;	  /**< Unique name for driver instantiation */
135
};
136
 
137
struct drm_list {
138
	int count;		  /**< Length of user-space structures */
139
	struct drm_version __user *version;
140
};
141
 
142
struct drm_block {
143
	int unused;
144
};
145
 
146
/**
147
 * DRM_IOCTL_CONTROL ioctl argument type.
148
 *
149
 * \sa drmCtlInstHandler() and drmCtlUninstHandler().
150
 */
151
struct drm_control {
152
	enum {
153
		DRM_ADD_COMMAND,
154
		DRM_RM_COMMAND,
155
		DRM_INST_HANDLER,
156
		DRM_UNINST_HANDLER
157
	} func;
158
	int irq;
159
};
160
 
161
/**
162
 * Type of memory to map.
163
 */
164
enum drm_map_type {
165
	_DRM_FRAME_BUFFER = 0,	  /**< WC (no caching), no core dump */
166
	_DRM_REGISTERS = 1,	  /**< no caching, no core dump */
167
	_DRM_SHM = 2,		  /**< shared, cached */
168
	_DRM_AGP = 3,		  /**< AGP/GART */
169
	_DRM_SCATTER_GATHER = 4,  /**< Scatter/gather memory for PCI DMA */
170
	_DRM_CONSISTENT = 5,	  /**< Consistent memory for PCI DMA */
171
	_DRM_GEM = 6,		  /**< GEM object */
172
};
173
 
174
/**
175
 * Memory mapping flags.
176
 */
177
enum drm_map_flags {
178
	_DRM_RESTRICTED = 0x01,	     /**< Cannot be mapped to user-virtual */
179
	_DRM_READ_ONLY = 0x02,
180
	_DRM_LOCKED = 0x04,	     /**< shared, cached, locked */
181
	_DRM_KERNEL = 0x08,	     /**< kernel requires access */
182
	_DRM_WRITE_COMBINING = 0x10, /**< use write-combining if available */
183
	_DRM_CONTAINS_LOCK = 0x20,   /**< SHM page that contains lock */
184
	_DRM_REMOVABLE = 0x40,	     /**< Removable mapping */
185
	_DRM_DRIVER = 0x80	     /**< Managed by driver */
186
};
187
 
188
struct drm_ctx_priv_map {
189
	unsigned int ctx_id;	 /**< Context requesting private mapping */
190
	void *handle;		 /**< Handle of map */
191
};
192
 
193
/**
194
 * DRM_IOCTL_GET_MAP, DRM_IOCTL_ADD_MAP and DRM_IOCTL_RM_MAP ioctls
195
 * argument type.
196
 *
197
 * \sa drmAddMap().
198
 */
199
struct drm_map {
200
	unsigned long offset;	 /**< Requested physical address (0 for SAREA)*/
201
	unsigned long size;	 /**< Requested physical size (bytes) */
202
	enum drm_map_type type;	 /**< Type of memory to map */
203
	enum drm_map_flags flags;	 /**< Flags */
204
	void *handle;		 /**< User-space: "Handle" to pass to mmap() */
205
				 /**< Kernel-space: kernel-virtual address */
206
	int mtrr;		 /**< MTRR slot used */
207
	/*   Private data */
208
};
209
 
210
/**
211
 * DRM_IOCTL_GET_CLIENT ioctl argument type.
212
 */
213
struct drm_client {
214
	int idx;		/**< Which client desired? */
215
	int auth;		/**< Is client authenticated? */
216
	unsigned long pid;	/**< Process ID */
217
	unsigned long uid;	/**< User ID */
218
	unsigned long magic;	/**< Magic */
219
	unsigned long iocs;	/**< Ioctl count */
220
};
221
 
222
enum drm_stat_type {
223
	_DRM_STAT_LOCK,
224
	_DRM_STAT_OPENS,
225
	_DRM_STAT_CLOSES,
226
	_DRM_STAT_IOCTLS,
227
	_DRM_STAT_LOCKS,
228
	_DRM_STAT_UNLOCKS,
229
	_DRM_STAT_VALUE,	/**< Generic value */
230
	_DRM_STAT_BYTE,		/**< Generic byte counter (1024bytes/K) */
231
	_DRM_STAT_COUNT,	/**< Generic non-byte counter (1000/k) */
232
 
233
	_DRM_STAT_IRQ,		/**< IRQ */
234
	_DRM_STAT_PRIMARY,	/**< Primary DMA bytes */
235
	_DRM_STAT_SECONDARY,	/**< Secondary DMA bytes */
236
	_DRM_STAT_DMA,		/**< DMA */
237
	_DRM_STAT_SPECIAL,	/**< Special DMA (e.g., priority or polled) */
238
	_DRM_STAT_MISSED	/**< Missed DMA opportunity */
239
	    /* Add to the *END* of the list */
240
};
241
 
242
/**
243
 * DRM_IOCTL_GET_STATS ioctl argument type.
244
 */
245
struct drm_stats {
246
	unsigned long count;
247
	struct {
248
		unsigned long value;
249
		enum drm_stat_type type;
250
	} data[15];
251
};
252
 
253
/**
254
 * Hardware locking flags.
255
 */
256
enum drm_lock_flags {
257
	_DRM_LOCK_READY = 0x01,	     /**< Wait until hardware is ready for DMA */
258
	_DRM_LOCK_QUIESCENT = 0x02,  /**< Wait until hardware quiescent */
259
	_DRM_LOCK_FLUSH = 0x04,	     /**< Flush this context's DMA queue first */
260
	_DRM_LOCK_FLUSH_ALL = 0x08,  /**< Flush all DMA queues first */
261
	/* These *HALT* flags aren't supported yet
262
	   -- they will be used to support the
263
	   full-screen DGA-like mode. */
264
	_DRM_HALT_ALL_QUEUES = 0x10, /**< Halt all current and future queues */
265
	_DRM_HALT_CUR_QUEUES = 0x20  /**< Halt all current queues */
266
};
267
 
268
/**
269
 * DRM_IOCTL_LOCK, DRM_IOCTL_UNLOCK and DRM_IOCTL_FINISH ioctl argument type.
270
 *
271
 * \sa drmGetLock() and drmUnlock().
272
 */
273
struct drm_lock {
274
	int context;
275
	enum drm_lock_flags flags;
276
};
277
 
278
/**
279
 * DMA flags
280
 *
281
 * \warning
282
 * These values \e must match xf86drm.h.
283
 *
284
 * \sa drm_dma.
285
 */
286
enum drm_dma_flags {
287
	/* Flags for DMA buffer dispatch */
288
	_DRM_DMA_BLOCK = 0x01,	      /**<
289
				       * Block until buffer dispatched.
290
				       *
291
				       * \note The buffer may not yet have
292
				       * been processed by the hardware --
293
				       * getting a hardware lock with the
294
				       * hardware quiescent will ensure
295
				       * that the buffer has been
296
				       * processed.
297
				       */
298
	_DRM_DMA_WHILE_LOCKED = 0x02, /**< Dispatch while lock held */
299
	_DRM_DMA_PRIORITY = 0x04,     /**< High priority dispatch */
300
 
301
	/* Flags for DMA buffer request */
302
	_DRM_DMA_WAIT = 0x10,	      /**< Wait for free buffers */
303
	_DRM_DMA_SMALLER_OK = 0x20,   /**< Smaller-than-requested buffers OK */
304
	_DRM_DMA_LARGER_OK = 0x40     /**< Larger-than-requested buffers OK */
305
};
306
 
307
/**
308
 * DRM_IOCTL_ADD_BUFS and DRM_IOCTL_MARK_BUFS ioctl argument type.
309
 *
310
 * \sa drmAddBufs().
311
 */
312
struct drm_buf_desc {
313
	int count;		 /**< Number of buffers of this size */
314
	int size;		 /**< Size in bytes */
315
	int low_mark;		 /**< Low water mark */
316
	int high_mark;		 /**< High water mark */
317
	enum {
318
		_DRM_PAGE_ALIGN = 0x01,	/**< Align on page boundaries for DMA */
319
		_DRM_AGP_BUFFER = 0x02,	/**< Buffer is in AGP space */
320
		_DRM_SG_BUFFER = 0x04,	/**< Scatter/gather memory buffer */
321
		_DRM_FB_BUFFER = 0x08,	/**< Buffer is in frame buffer */
322
		_DRM_PCI_BUFFER_RO = 0x10 /**< Map PCI DMA buffer read-only */
323
	} flags;
324
	unsigned long agp_start; /**<
325
				  * Start address of where the AGP buffers are
326
				  * in the AGP aperture
327
				  */
328
};
329
 
330
/**
331
 * DRM_IOCTL_INFO_BUFS ioctl argument type.
332
 */
333
struct drm_buf_info {
334
	int count;		/**< Entries in list */
335
	struct drm_buf_desc __user *list;
336
};
337
 
338
/**
339
 * DRM_IOCTL_FREE_BUFS ioctl argument type.
340
 */
341
struct drm_buf_free {
342
	int count;
343
	int __user *list;
344
};
345
 
346
/**
347
 * Buffer information
348
 *
349
 * \sa drm_buf_map.
350
 */
351
struct drm_buf_pub {
352
	int idx;		       /**< Index into the master buffer list */
353
	int total;		       /**< Buffer size */
354
	int used;		       /**< Amount of buffer in use (for DMA) */
355
	void __user *address;	       /**< Address of buffer */
356
};
357
 
358
/**
359
 * DRM_IOCTL_MAP_BUFS ioctl argument type.
360
 */
361
struct drm_buf_map {
362
	int count;		/**< Length of the buffer list */
363
	void __user *virtual;		/**< Mmap'd area in user-virtual */
364
	struct drm_buf_pub __user *list;	/**< Buffer information */
365
};
366
 
367
/**
368
 * DRM_IOCTL_DMA ioctl argument type.
369
 *
370
 * Indices here refer to the offset into the buffer list in drm_buf_get.
371
 *
372
 * \sa drmDMA().
373
 */
374
struct drm_dma {
375
	int context;			  /**< Context handle */
376
	int send_count;			  /**< Number of buffers to send */
377
	int __user *send_indices;	  /**< List of handles to buffers */
378
	int __user *send_sizes;		  /**< Lengths of data to send */
379
	enum drm_dma_flags flags;	  /**< Flags */
380
	int request_count;		  /**< Number of buffers requested */
381
	int request_size;		  /**< Desired size for buffers */
382
	int __user *request_indices;	  /**< Buffer information */
383
	int __user *request_sizes;
384
	int granted_count;		  /**< Number of buffers granted */
385
};
386
 
387
enum drm_ctx_flags {
388
	_DRM_CONTEXT_PRESERVED = 0x01,
389
	_DRM_CONTEXT_2DONLY = 0x02
390
};
391
 
392
/**
393
 * DRM_IOCTL_ADD_CTX ioctl argument type.
394
 *
395
 * \sa drmCreateContext() and drmDestroyContext().
396
 */
397
struct drm_ctx {
398
	drm_context_t handle;
399
	enum drm_ctx_flags flags;
400
};
401
 
402
/**
403
 * DRM_IOCTL_RES_CTX ioctl argument type.
404
 */
405
struct drm_ctx_res {
406
	int count;
407
	struct drm_ctx __user *contexts;
408
};
409
 
410
/**
411
 * DRM_IOCTL_ADD_DRAW and DRM_IOCTL_RM_DRAW ioctl argument type.
412
 */
413
struct drm_draw {
414
	drm_drawable_t handle;
415
};
416
 
417
/**
418
 * DRM_IOCTL_UPDATE_DRAW ioctl argument type.
419
 */
420
typedef enum {
421
	DRM_DRAWABLE_CLIPRECTS,
422
} drm_drawable_info_type_t;
423
 
424
struct drm_update_draw {
425
	drm_drawable_t handle;
426
	unsigned int type;
427
	unsigned int num;
428
	unsigned long long data;
429
};
430
 
431
/**
432
 * DRM_IOCTL_GET_MAGIC and DRM_IOCTL_AUTH_MAGIC ioctl argument type.
433
 */
434
struct drm_auth {
435
	drm_magic_t magic;
436
};
437
 
438
/**
439
 * DRM_IOCTL_IRQ_BUSID ioctl argument type.
440
 *
441
 * \sa drmGetInterruptFromBusID().
442
 */
443
struct drm_irq_busid {
444
	int irq;	/**< IRQ number */
445
	int busnum;	/**< bus number */
446
	int devnum;	/**< device number */
447
	int funcnum;	/**< function number */
448
};
449
 
450
enum drm_vblank_seq_type {
451
	_DRM_VBLANK_ABSOLUTE = 0x0,	/**< Wait for specific vblank sequence number */
452
	_DRM_VBLANK_RELATIVE = 0x1,	/**< Wait for given number of vblanks */
1964 serge 453
	/* bits 1-6 are reserved for high crtcs */
454
	_DRM_VBLANK_HIGH_CRTC_MASK = 0x0000003e,
1408 serge 455
	_DRM_VBLANK_EVENT = 0x4000000,   /**< Send event instead of blocking */
456
	_DRM_VBLANK_FLIP = 0x8000000,   /**< Scheduled buffer swap should flip */
457
	_DRM_VBLANK_NEXTONMISS = 0x10000000,	/**< If missed, wait for next vblank */
458
	_DRM_VBLANK_SECONDARY = 0x20000000,	/**< Secondary display controller */
459
	_DRM_VBLANK_SIGNAL = 0x40000000	/**< Send signal instead of blocking, unsupported */
460
};
1964 serge 461
#define _DRM_VBLANK_HIGH_CRTC_SHIFT 1
1408 serge 462
 
463
#define _DRM_VBLANK_TYPES_MASK (_DRM_VBLANK_ABSOLUTE | _DRM_VBLANK_RELATIVE)
464
#define _DRM_VBLANK_FLAGS_MASK (_DRM_VBLANK_EVENT | _DRM_VBLANK_SIGNAL | \
465
				_DRM_VBLANK_SECONDARY | _DRM_VBLANK_NEXTONMISS)
466
 
467
struct drm_wait_vblank_request {
468
	enum drm_vblank_seq_type type;
469
	unsigned int sequence;
470
	unsigned long signal;
471
};
472
 
473
struct drm_wait_vblank_reply {
474
	enum drm_vblank_seq_type type;
475
	unsigned int sequence;
476
	long tval_sec;
477
	long tval_usec;
478
};
479
 
480
/**
481
 * DRM_IOCTL_WAIT_VBLANK ioctl argument type.
482
 *
483
 * \sa drmWaitVBlank().
484
 */
485
union drm_wait_vblank {
486
	struct drm_wait_vblank_request request;
487
	struct drm_wait_vblank_reply reply;
488
};
489
 
490
#define _DRM_PRE_MODESET 1
491
#define _DRM_POST_MODESET 2
492
 
493
/**
494
 * DRM_IOCTL_MODESET_CTL ioctl argument type
495
 *
496
 * \sa drmModesetCtl().
497
 */
498
struct drm_modeset_ctl {
499
	__u32 crtc;
500
	__u32 cmd;
501
};
502
 
503
/**
504
 * DRM_IOCTL_AGP_ENABLE ioctl argument type.
505
 *
506
 * \sa drmAgpEnable().
507
 */
508
struct drm_agp_mode {
509
	unsigned long mode;	/**< AGP mode */
510
};
511
 
512
/**
513
 * DRM_IOCTL_AGP_ALLOC and DRM_IOCTL_AGP_FREE ioctls argument type.
514
 *
515
 * \sa drmAgpAlloc() and drmAgpFree().
516
 */
517
struct drm_agp_buffer {
518
	unsigned long size;	/**< In bytes -- will round to page boundary */
519
	unsigned long handle;	/**< Used for binding / unbinding */
520
	unsigned long type;	/**< Type of memory to allocate */
521
	unsigned long physical;	/**< Physical used by i810 */
522
};
523
 
524
/**
525
 * DRM_IOCTL_AGP_BIND and DRM_IOCTL_AGP_UNBIND ioctls argument type.
526
 *
527
 * \sa drmAgpBind() and drmAgpUnbind().
528
 */
529
struct drm_agp_binding {
530
	unsigned long handle;	/**< From drm_agp_buffer */
531
	unsigned long offset;	/**< In bytes -- will round to page boundary */
532
};
533
 
534
/**
535
 * DRM_IOCTL_AGP_INFO ioctl argument type.
536
 *
537
 * \sa drmAgpVersionMajor(), drmAgpVersionMinor(), drmAgpGetMode(),
538
 * drmAgpBase(), drmAgpSize(), drmAgpMemoryUsed(), drmAgpMemoryAvail(),
539
 * drmAgpVendorId() and drmAgpDeviceId().
540
 */
541
struct drm_agp_info {
542
	int agp_version_major;
543
	int agp_version_minor;
544
	unsigned long mode;
545
	unsigned long aperture_base;	/* physical address */
546
	unsigned long aperture_size;	/* bytes */
547
	unsigned long memory_allowed;	/* bytes */
548
	unsigned long memory_used;
549
 
550
	/* PCI information */
551
	unsigned short id_vendor;
552
	unsigned short id_device;
553
};
554
 
555
/**
556
 * DRM_IOCTL_SG_ALLOC ioctl argument type.
557
 */
558
struct drm_scatter_gather {
559
	unsigned long size;	/**< In bytes -- will round to page boundary */
560
	unsigned long handle;	/**< Used for mapping / unmapping */
561
};
562
 
563
/**
564
 * DRM_IOCTL_SET_VERSION ioctl argument type.
565
 */
566
struct drm_set_version {
567
	int drm_di_major;
568
	int drm_di_minor;
569
	int drm_dd_major;
570
	int drm_dd_minor;
571
};
572
 
573
/** DRM_IOCTL_GEM_CLOSE ioctl argument type */
574
struct drm_gem_close {
575
	/** Handle of the object to be closed. */
576
	__u32 handle;
577
	__u32 pad;
578
};
579
 
580
/** DRM_IOCTL_GEM_FLINK ioctl argument type */
581
struct drm_gem_flink {
582
	/** Handle for the object being named */
583
	__u32 handle;
584
 
585
	/** Returned global name */
586
	__u32 name;
587
};
588
 
589
/** DRM_IOCTL_GEM_OPEN ioctl argument type */
590
struct drm_gem_open {
591
	/** Name of object being opened */
592
	__u32 name;
593
 
594
	/** Returned handle for the object */
595
	__u32 handle;
596
 
597
	/** Returned size of the object */
598
	__u64 size;
599
};
600
 
1964 serge 601
/** DRM_IOCTL_GET_CAP ioctl argument type */
602
struct drm_get_cap {
603
	__u64 capability;
604
	__u64 value;
605
};
606
 
1408 serge 607
#include "drm_mode.h"
608
 
609
/*
610
#define DRM_IOCTL_BASE			'd'
611
#define DRM_IO(nr)			_IO(DRM_IOCTL_BASE,nr)
612
#define DRM_IOR(nr,type)		_IOR(DRM_IOCTL_BASE,nr,type)
613
#define DRM_IOW(nr,type)		_IOW(DRM_IOCTL_BASE,nr,type)
614
#define DRM_IOWR(nr,type)		_IOWR(DRM_IOCTL_BASE,nr,type)
615
 
616
#define DRM_IOCTL_VERSION		DRM_IOWR(0x00, struct drm_version)
617
#define DRM_IOCTL_GET_UNIQUE		DRM_IOWR(0x01, struct drm_unique)
618
#define DRM_IOCTL_GET_MAGIC		DRM_IOR( 0x02, struct drm_auth)
619
#define DRM_IOCTL_IRQ_BUSID		DRM_IOWR(0x03, struct drm_irq_busid)
620
#define DRM_IOCTL_GET_MAP               DRM_IOWR(0x04, struct drm_map)
621
#define DRM_IOCTL_GET_CLIENT            DRM_IOWR(0x05, struct drm_client)
622
#define DRM_IOCTL_GET_STATS             DRM_IOR( 0x06, struct drm_stats)
623
#define DRM_IOCTL_SET_VERSION		DRM_IOWR(0x07, struct drm_set_version)
624
#define DRM_IOCTL_MODESET_CTL           DRM_IOW(0x08, struct drm_modeset_ctl)
625
#define DRM_IOCTL_GEM_CLOSE		DRM_IOW (0x09, struct drm_gem_close)
626
#define DRM_IOCTL_GEM_FLINK		DRM_IOWR(0x0a, struct drm_gem_flink)
627
#define DRM_IOCTL_GEM_OPEN		DRM_IOWR(0x0b, struct drm_gem_open)
1964 serge 628
#define DRM_IOCTL_GET_CAP		DRM_IOWR(0x0c, struct drm_get_cap)
1408 serge 629
 
630
#define DRM_IOCTL_SET_UNIQUE		DRM_IOW( 0x10, struct drm_unique)
631
#define DRM_IOCTL_AUTH_MAGIC		DRM_IOW( 0x11, struct drm_auth)
632
#define DRM_IOCTL_BLOCK			DRM_IOWR(0x12, struct drm_block)
633
#define DRM_IOCTL_UNBLOCK		DRM_IOWR(0x13, struct drm_block)
634
#define DRM_IOCTL_CONTROL		DRM_IOW( 0x14, struct drm_control)
635
#define DRM_IOCTL_ADD_MAP		DRM_IOWR(0x15, struct drm_map)
636
#define DRM_IOCTL_ADD_BUFS		DRM_IOWR(0x16, struct drm_buf_desc)
637
#define DRM_IOCTL_MARK_BUFS		DRM_IOW( 0x17, struct drm_buf_desc)
638
#define DRM_IOCTL_INFO_BUFS		DRM_IOWR(0x18, struct drm_buf_info)
639
#define DRM_IOCTL_MAP_BUFS		DRM_IOWR(0x19, struct drm_buf_map)
640
#define DRM_IOCTL_FREE_BUFS		DRM_IOW( 0x1a, struct drm_buf_free)
641
 
642
#define DRM_IOCTL_RM_MAP		DRM_IOW( 0x1b, struct drm_map)
643
 
644
#define DRM_IOCTL_SET_SAREA_CTX		DRM_IOW( 0x1c, struct drm_ctx_priv_map)
645
#define DRM_IOCTL_GET_SAREA_CTX 	DRM_IOWR(0x1d, struct drm_ctx_priv_map)
646
 
647
#define DRM_IOCTL_SET_MASTER            DRM_IO(0x1e)
648
#define DRM_IOCTL_DROP_MASTER           DRM_IO(0x1f)
649
 
650
#define DRM_IOCTL_ADD_CTX		DRM_IOWR(0x20, struct drm_ctx)
651
#define DRM_IOCTL_RM_CTX		DRM_IOWR(0x21, struct drm_ctx)
652
#define DRM_IOCTL_MOD_CTX		DRM_IOW( 0x22, struct drm_ctx)
653
#define DRM_IOCTL_GET_CTX		DRM_IOWR(0x23, struct drm_ctx)
654
#define DRM_IOCTL_SWITCH_CTX		DRM_IOW( 0x24, struct drm_ctx)
655
#define DRM_IOCTL_NEW_CTX		DRM_IOW( 0x25, struct drm_ctx)
656
#define DRM_IOCTL_RES_CTX		DRM_IOWR(0x26, struct drm_ctx_res)
657
#define DRM_IOCTL_ADD_DRAW		DRM_IOWR(0x27, struct drm_draw)
658
#define DRM_IOCTL_RM_DRAW		DRM_IOWR(0x28, struct drm_draw)
659
#define DRM_IOCTL_DMA			DRM_IOWR(0x29, struct drm_dma)
660
#define DRM_IOCTL_LOCK			DRM_IOW( 0x2a, struct drm_lock)
661
#define DRM_IOCTL_UNLOCK		DRM_IOW( 0x2b, struct drm_lock)
662
#define DRM_IOCTL_FINISH		DRM_IOW( 0x2c, struct drm_lock)
663
 
1964 serge 664
#define DRM_IOCTL_GEM_PRIME_OPEN        DRM_IOWR(0x2e, struct drm_gem_open)
665
 
1408 serge 666
#define DRM_IOCTL_AGP_ACQUIRE		DRM_IO(  0x30)
667
#define DRM_IOCTL_AGP_RELEASE		DRM_IO(  0x31)
668
#define DRM_IOCTL_AGP_ENABLE		DRM_IOW( 0x32, struct drm_agp_mode)
669
#define DRM_IOCTL_AGP_INFO		DRM_IOR( 0x33, struct drm_agp_info)
670
#define DRM_IOCTL_AGP_ALLOC		DRM_IOWR(0x34, struct drm_agp_buffer)
671
#define DRM_IOCTL_AGP_FREE		DRM_IOW( 0x35, struct drm_agp_buffer)
672
#define DRM_IOCTL_AGP_BIND		DRM_IOW( 0x36, struct drm_agp_binding)
673
#define DRM_IOCTL_AGP_UNBIND		DRM_IOW( 0x37, struct drm_agp_binding)
674
 
675
#define DRM_IOCTL_SG_ALLOC		DRM_IOWR(0x38, struct drm_scatter_gather)
676
#define DRM_IOCTL_SG_FREE		DRM_IOW( 0x39, struct drm_scatter_gather)
677
 
678
#define DRM_IOCTL_WAIT_VBLANK		DRM_IOWR(0x3a, union drm_wait_vblank)
679
 
680
#define DRM_IOCTL_UPDATE_DRAW		DRM_IOW(0x3f, struct drm_update_draw)
681
 
682
#define DRM_IOCTL_MODE_GETRESOURCES	DRM_IOWR(0xA0, struct drm_mode_card_res)
683
#define DRM_IOCTL_MODE_GETCRTC		DRM_IOWR(0xA1, struct drm_mode_crtc)
684
#define DRM_IOCTL_MODE_SETCRTC		DRM_IOWR(0xA2, struct drm_mode_crtc)
685
#define DRM_IOCTL_MODE_CURSOR		DRM_IOWR(0xA3, struct drm_mode_cursor)
686
#define DRM_IOCTL_MODE_GETGAMMA		DRM_IOWR(0xA4, struct drm_mode_crtc_lut)
687
#define DRM_IOCTL_MODE_SETGAMMA		DRM_IOWR(0xA5, struct drm_mode_crtc_lut)
688
#define DRM_IOCTL_MODE_GETENCODER	DRM_IOWR(0xA6, struct drm_mode_get_encoder)
689
#define DRM_IOCTL_MODE_GETCONNECTOR	DRM_IOWR(0xA7, struct drm_mode_get_connector)
690
#define DRM_IOCTL_MODE_ATTACHMODE	DRM_IOWR(0xA8, struct drm_mode_mode_cmd)
691
#define DRM_IOCTL_MODE_DETACHMODE	DRM_IOWR(0xA9, struct drm_mode_mode_cmd)
692
 
693
#define DRM_IOCTL_MODE_GETPROPERTY	DRM_IOWR(0xAA, struct drm_mode_get_property)
694
#define DRM_IOCTL_MODE_SETPROPERTY	DRM_IOWR(0xAB, struct drm_mode_connector_set_property)
695
#define DRM_IOCTL_MODE_GETPROPBLOB	DRM_IOWR(0xAC, struct drm_mode_get_blob)
696
#define DRM_IOCTL_MODE_GETFB		DRM_IOWR(0xAD, struct drm_mode_fb_cmd)
697
#define DRM_IOCTL_MODE_ADDFB		DRM_IOWR(0xAE, struct drm_mode_fb_cmd)
698
#define DRM_IOCTL_MODE_RMFB		DRM_IOWR(0xAF, unsigned int)
699
#define DRM_IOCTL_MODE_PAGE_FLIP	DRM_IOWR(0xB0, struct drm_mode_crtc_page_flip)
1964 serge 700
#define DRM_IOCTL_MODE_DIRTYFB		DRM_IOWR(0xB1, struct drm_mode_fb_dirty_cmd)
1408 serge 701
*/
702
 
703
/**
704
 * Device specific ioctls should only be in their respective headers
705
 * The device specific ioctl range is from 0x40 to 0x99.
706
 * Generic IOCTLS restart at 0xA0.
707
 *
708
 * \sa drmCommandNone(), drmCommandRead(), drmCommandWrite(), and
709
 * drmCommandReadWrite().
710
 */
711
#define DRM_COMMAND_BASE                0x40
712
#define DRM_COMMAND_END			0xA0
713
 
714
/**
715
 * Header for events written back to userspace on the drm fd.  The
716
 * type defines the type of event, the length specifies the total
717
 * length of the event (including the header), and user_data is
718
 * typically a 64 bit value passed with the ioctl that triggered the
719
 * event.  A read on the drm fd will always only return complete
720
 * events, that is, if for example the read buffer is 100 bytes, and
721
 * there are two 64 byte events pending, only one will be returned.
722
 *
723
 * Event types 0 - 0x7fffffff are generic drm events, 0x80000000 and
724
 * up are chipset specific.
725
 */
726
struct drm_event {
727
	__u32 type;
728
	__u32 length;
729
};
730
 
731
#define DRM_EVENT_VBLANK 0x01
732
#define DRM_EVENT_FLIP_COMPLETE 0x02
733
 
734
struct drm_event_vblank {
735
	struct drm_event base;
736
	__u64 user_data;
737
	__u32 tv_sec;
738
	__u32 tv_usec;
739
	__u32 sequence;
740
	__u32 reserved;
741
};
742
 
1964 serge 743
#define DRM_CAP_DUMB_BUFFER 0x1
744
#define DRM_CAP_VBLANK_HIGH_CRTC 0x2
745
 
1408 serge 746
/* typedef area */
747
#ifndef __KERNEL__
748
typedef struct drm_clip_rect drm_clip_rect_t;
749
typedef struct drm_drawable_info drm_drawable_info_t;
750
typedef struct drm_tex_region drm_tex_region_t;
751
typedef struct drm_hw_lock drm_hw_lock_t;
752
typedef struct drm_version drm_version_t;
753
typedef struct drm_unique drm_unique_t;
754
typedef struct drm_list drm_list_t;
755
typedef struct drm_block drm_block_t;
756
typedef struct drm_control drm_control_t;
757
typedef enum drm_map_type drm_map_type_t;
758
typedef enum drm_map_flags drm_map_flags_t;
759
typedef struct drm_ctx_priv_map drm_ctx_priv_map_t;
760
typedef struct drm_map drm_map_t;
761
typedef struct drm_client drm_client_t;
762
typedef enum drm_stat_type drm_stat_type_t;
763
typedef struct drm_stats drm_stats_t;
764
typedef enum drm_lock_flags drm_lock_flags_t;
765
typedef struct drm_lock drm_lock_t;
766
typedef enum drm_dma_flags drm_dma_flags_t;
767
typedef struct drm_buf_desc drm_buf_desc_t;
768
typedef struct drm_buf_info drm_buf_info_t;
769
typedef struct drm_buf_free drm_buf_free_t;
770
typedef struct drm_buf_pub drm_buf_pub_t;
771
typedef struct drm_buf_map drm_buf_map_t;
772
typedef struct drm_dma drm_dma_t;
773
typedef union drm_wait_vblank drm_wait_vblank_t;
774
typedef struct drm_agp_mode drm_agp_mode_t;
775
typedef enum drm_ctx_flags drm_ctx_flags_t;
776
typedef struct drm_ctx drm_ctx_t;
777
typedef struct drm_ctx_res drm_ctx_res_t;
778
typedef struct drm_draw drm_draw_t;
779
typedef struct drm_update_draw drm_update_draw_t;
780
typedef struct drm_auth drm_auth_t;
781
typedef struct drm_irq_busid drm_irq_busid_t;
782
typedef enum drm_vblank_seq_type drm_vblank_seq_type_t;
783
 
784
typedef struct drm_agp_buffer drm_agp_buffer_t;
785
typedef struct drm_agp_binding drm_agp_binding_t;
786
typedef struct drm_agp_info drm_agp_info_t;
787
typedef struct drm_scatter_gather drm_scatter_gather_t;
788
typedef struct drm_set_version drm_set_version_t;
789
#endif
790
 
791
#endif