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| Rev | Author | Line No. | Line |
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| 6082 | serge | 1 | /* |
| 2 | * intel-mid.h: Intel MID specific setup code |
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| 3 | * |
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| 4 | * (C) Copyright 2009 Intel Corporation |
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| 5 | * |
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| 6 | * This program is free software; you can redistribute it and/or |
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| 7 | * modify it under the terms of the GNU General Public License |
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| 8 | * as published by the Free Software Foundation; version 2 |
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| 9 | * of the License. |
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| 10 | */ |
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| 11 | #ifndef _ASM_X86_INTEL_MID_H |
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| 12 | #define _ASM_X86_INTEL_MID_H |
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| 13 | |||
| 14 | #include |
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| 15 | //#include |
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| 16 | |||
| 17 | extern int intel_mid_pci_init(void); |
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| 18 | extern int get_gpio_by_name(const char *name); |
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| 19 | extern void intel_scu_device_register(struct platform_device *pdev); |
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| 20 | extern int __init sfi_parse_mrtc(struct sfi_table_header *table); |
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| 21 | extern int __init sfi_parse_mtmr(struct sfi_table_header *table); |
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| 22 | extern int sfi_mrtc_num; |
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| 23 | extern struct sfi_rtc_table_entry sfi_mrtc_array[]; |
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| 24 | |||
| 25 | /* |
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| 26 | * Here defines the array of devices platform data that IAFW would export |
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| 27 | * through SFI "DEVS" table, we use name and type to match the device and |
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| 28 | * its platform data. |
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| 29 | */ |
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| 30 | struct devs_id { |
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| 31 | char name[SFI_NAME_LEN + 1]; |
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| 32 | u8 type; |
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| 33 | u8 delay; |
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| 34 | void *(*get_platform_data)(void *info); |
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| 35 | /* Custom handler for devices */ |
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| 36 | void (*device_handler)(struct sfi_device_table_entry *pentry, |
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| 37 | struct devs_id *dev); |
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| 38 | }; |
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| 39 | |||
| 40 | #define sfi_device(i) \ |
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| 41 | static const struct devs_id *const __intel_mid_sfi_##i##_dev __used \ |
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| 42 | __attribute__((__section__(".x86_intel_mid_dev.init"))) = &i |
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| 43 | |||
| 44 | /* |
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| 45 | * Medfield is the follow-up of Moorestown, it combines two chip solution into |
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| 46 | * one. Other than that it also added always-on and constant tsc and lapic |
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| 47 | * timers. Medfield is the platform name, and the chip name is called Penwell |
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| 48 | * we treat Medfield/Penwell as a variant of Moorestown. Penwell can be |
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| 49 | * identified via MSRs. |
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| 50 | */ |
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| 51 | enum intel_mid_cpu_type { |
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| 52 | /* 1 was Moorestown */ |
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| 53 | INTEL_MID_CPU_CHIP_PENWELL = 2, |
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| 54 | INTEL_MID_CPU_CHIP_CLOVERVIEW, |
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| 55 | INTEL_MID_CPU_CHIP_TANGIER, |
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| 56 | }; |
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| 57 | |||
| 58 | extern enum intel_mid_cpu_type __intel_mid_cpu_chip; |
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| 59 | |||
| 60 | /** |
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| 61 | * struct intel_mid_ops - Interface between intel-mid & sub archs |
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| 62 | * @arch_setup: arch_setup function to re-initialize platform |
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| 63 | * structures (x86_init, x86_platform_init) |
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| 64 | * |
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| 65 | * This structure can be extended if any new interface is required |
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| 66 | * between intel-mid & its sub arch files. |
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| 67 | */ |
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| 68 | struct intel_mid_ops { |
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| 69 | void (*arch_setup)(void); |
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| 70 | }; |
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| 71 | |||
| 72 | /* Helper API's for INTEL_MID_OPS_INIT */ |
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| 73 | #define DECLARE_INTEL_MID_OPS_INIT(cpuname, cpuid) \ |
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| 74 | [cpuid] = get_##cpuname##_ops |
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| 75 | |||
| 76 | /* Maximum number of CPU ops */ |
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| 77 | #define MAX_CPU_OPS(a) (sizeof(a)/sizeof(void *)) |
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| 78 | |||
| 79 | /* |
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| 80 | * For every new cpu addition, a weak get_ |
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| 81 | * declared in arch/x86/platform/intel_mid/intel_mid_weak_decls.h. |
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| 82 | */ |
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| 83 | #define INTEL_MID_OPS_INIT {\ |
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| 84 | DECLARE_INTEL_MID_OPS_INIT(penwell, INTEL_MID_CPU_CHIP_PENWELL), \ |
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| 85 | DECLARE_INTEL_MID_OPS_INIT(cloverview, INTEL_MID_CPU_CHIP_CLOVERVIEW), \ |
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| 86 | DECLARE_INTEL_MID_OPS_INIT(tangier, INTEL_MID_CPU_CHIP_TANGIER) \ |
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| 87 | }; |
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| 88 | |||
| 89 | #ifdef CONFIG_X86_INTEL_MID |
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| 90 | |||
| 91 | static inline enum intel_mid_cpu_type intel_mid_identify_cpu(void) |
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| 92 | { |
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| 93 | return __intel_mid_cpu_chip; |
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| 94 | } |
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| 95 | |||
| 96 | static inline bool intel_mid_has_msic(void) |
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| 97 | { |
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| 98 | return (intel_mid_identify_cpu() == INTEL_MID_CPU_CHIP_PENWELL); |
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| 99 | } |
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| 100 | |||
| 101 | #else /* !CONFIG_X86_INTEL_MID */ |
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| 102 | |||
| 103 | #define intel_mid_identify_cpu() (0) |
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| 104 | #define intel_mid_has_msic() (0) |
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| 105 | |||
| 106 | #endif /* !CONFIG_X86_INTEL_MID */ |
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| 107 | |||
| 108 | enum intel_mid_timer_options { |
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| 109 | INTEL_MID_TIMER_DEFAULT, |
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| 110 | INTEL_MID_TIMER_APBT_ONLY, |
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| 111 | INTEL_MID_TIMER_LAPIC_APBT, |
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| 112 | }; |
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| 113 | |||
| 114 | extern enum intel_mid_timer_options intel_mid_timer_options; |
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| 115 | |||
| 116 | /* |
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| 117 | * Penwell uses spread spectrum clock, so the freq number is not exactly |
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| 118 | * the same as reported by MSR based on SDM. |
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| 119 | */ |
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| 120 | #define FSB_FREQ_83SKU 83200 |
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| 121 | #define FSB_FREQ_100SKU 99840 |
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| 122 | #define FSB_FREQ_133SKU 133000 |
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| 123 | |||
| 124 | #define FSB_FREQ_167SKU 167000 |
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| 125 | #define FSB_FREQ_200SKU 200000 |
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| 126 | #define FSB_FREQ_267SKU 267000 |
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| 127 | #define FSB_FREQ_333SKU 333000 |
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| 128 | #define FSB_FREQ_400SKU 400000 |
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| 129 | |||
| 130 | /* Bus Select SoC Fuse value */ |
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| 131 | #define BSEL_SOC_FUSE_MASK 0x7 |
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| 132 | #define BSEL_SOC_FUSE_001 0x1 /* FSB 133MHz */ |
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| 133 | #define BSEL_SOC_FUSE_101 0x5 /* FSB 100MHz */ |
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| 134 | #define BSEL_SOC_FUSE_111 0x7 /* FSB 83MHz */ |
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| 135 | |||
| 136 | #define SFI_MTMR_MAX_NUM 8 |
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| 137 | #define SFI_MRTC_MAX 8 |
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| 138 | |||
| 139 | extern void intel_scu_devices_create(void); |
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| 140 | extern void intel_scu_devices_destroy(void); |
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| 141 | |||
| 142 | /* VRTC timer */ |
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| 143 | #define MRST_VRTC_MAP_SZ (1024) |
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| 144 | /*#define MRST_VRTC_PGOFFSET (0xc00) */ |
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| 145 | |||
| 146 | extern void intel_mid_rtc_init(void); |
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| 147 | |||
| 148 | /* the offset for the mapping of global gpio pin to irq */ |
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| 149 | #define INTEL_MID_IRQ_OFFSET 0x100 |
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| 150 | |||
| 151 | #endif /* _ASM_X86_INTEL_MID_H */ |