Subversion Repositories Kolibri OS

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;;                                                                 ;;

;; Copyright (C) KolibriOS team 2004-2014. All rights reserved.    ;;

;; Distributed under terms of the GNU General Public License       ;;

;;                                                                 ;;

;;  i8254x driver for KolibriOS                                    ;;

;;                                                                 ;;

;;  based on i8254x.asm from baremetal os                          ;;

;;                                                                 ;;

;;    Written by hidnplayr (hidnplayr@gmail.com)                   ;;

;;                                                                 ;;

;;          GNU GENERAL PUBLIC LICENSE                             ;;

;;             Version 2, June 1991                                ;;

;;                                                                 ;;

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        ; TODO: make better use of the available descriptors

format MS COFF

        API_VERSION             = 0x01000100

        DRIVER_VERSION          = 5

        MAX_DEVICES             = 16

        DEBUG                   = 1

        __DEBUG__               = 1

        __DEBUG_LEVEL__         = 2             ; 1 = verbose, 2 = errors only

        MAX_PKT_SIZE            = 4096          ; Maximum packet size

        RX_RING_SIZE            = 8             ; Must be a multiple of 8

include '../struct.inc'

include '../macros.inc'

include '../proc32.inc'

include '../imports.inc'

include '../fdo.inc'

include '../netdrv.inc'

public START

public service_proc

public version

; Register list

REG_CTRL                = 0x0000 ; Control Register

REG_STATUS              = 0x0008 ; Device Status Register

REG_CTRLEXT             = 0x0018 ; Extended Control Register

REG_MDIC                = 0x0020 ; MDI Control Register

REG_FCAL                = 0x0028 ; Flow Control Address Low

REG_FCAH                = 0x002C ; Flow Control Address High

REG_FCT                 = 0x0030 ; Flow Control Type

REG_VET                 = 0x0038 ; VLAN Ether Type

REG_ICR                 = 0x00C0 ; Interrupt Cause Read

REG_ITR                 = 0x00C4 ; Interrupt Throttling Register

REG_ICS                 = 0x00C8 ; Interrupt Cause Set Register

REG_IMS                 = 0x00D0 ; Interrupt Mask Set/Read Register

REG_IMC                 = 0x00D8 ; Interrupt Mask Clear Register

REG_RCTL                = 0x0100 ; Receive Control Register

REG_FCTTV               = 0x0170 ; Flow Control Transmit Timer Value

REG_TXCW                = 0x0178 ; Transmit Configuration Word

REG_RXCW                = 0x0180 ; Receive Configuration Word

REG_TCTL                = 0x0400 ; Transmit Control Register

REG_TIPG                = 0x0410 ; Transmit Inter Packet Gap

REG_LEDCTL              = 0x0E00 ; LED Control

REG_PBA                 = 0x1000 ; Packet Buffer Allocation

REG_RDBAL               = 0x2800 ; RX Descriptor Base Address Low

REG_RDBAH               = 0x2804 ; RX Descriptor Base Address High

REG_RDLEN               = 0x2808 ; RX Descriptor Length

REG_RDH                 = 0x2810 ; RX Descriptor Head

REG_RDT                 = 0x2818 ; RX Descriptor Tail

REG_RDTR                = 0x2820 ; RX Delay Timer Register

REG_RXDCTL              = 0x3828 ; RX Descriptor Control

REG_RADV                = 0x282C ; RX Int. Absolute Delay Timer

REG_RSRPD               = 0x2C00 ; RX Small Packet Detect Interrupt

REG_TXDMAC              = 0x3000 ; TX DMA Control

REG_TDBAL               = 0x3800 ; TX Descriptor Base Address Low

REG_TDBAH               = 0x3804 ; TX Descriptor Base Address High

REG_TDLEN               = 0x3808 ; TX Descriptor Length

REG_TDH                 = 0x3810 ; TX Descriptor Head

REG_TDT                 = 0x3818 ; TX Descriptor Tail

REG_TIDV                = 0x3820 ; TX Interrupt Delay Value

REG_TXDCTL              = 0x3828 ; TX Descriptor Control

REG_TADV                = 0x382C ; TX Absolute Interrupt Delay Value

REG_TSPMT               = 0x3830 ; TCP Segmentation Pad & Min Threshold

REG_RXCSUM              = 0x5000 ; RX Checksum Control

; Register list for i8254x

I82542_REG_RDTR         = 0x0108 ; RX Delay Timer Register

I82542_REG_RDBAL        = 0x0110 ; RX Descriptor Base Address Low

I82542_REG_RDBAH        = 0x0114 ; RX Descriptor Base Address High

I82542_REG_RDLEN        = 0x0118 ; RX Descriptor Length

I82542_REG_RDH          = 0x0120 ; RDH for i82542

I82542_REG_RDT          = 0x0128 ; RDT for i82542

I82542_REG_TDBAL        = 0x0420 ; TX Descriptor Base Address Low

I82542_REG_TDBAH        = 0x0424 ; TX Descriptor Base Address Low

I82542_REG_TDLEN        = 0x0428 ; TX Descriptor Length

I82542_REG_TDH          = 0x0430 ; TDH for i82542

I82542_REG_TDT          = 0x0438 ; TDT for i82542

; CTRL - Control Register (0x0000)

CTRL_FD                 = 0x00000001 ; Full Duplex

CTRL_LRST               = 0x00000008 ; Link Reset

CTRL_ASDE               = 0x00000020 ; Auto-speed detection

CTRL_SLU                = 0x00000040 ; Set Link Up

CTRL_ILOS               = 0x00000080 ; Invert Loss of Signal

CTRL_SPEED_MASK         = 0x00000300 ; Speed selection

CTRL_SPEED_SHIFT        = 8

CTRL_FRCSPD             = 0x00000800 ; Force Speed

CTRL_FRCDPLX            = 0x00001000 ; Force Duplex

CTRL_SDP0_DATA          = 0x00040000 ; SDP0 data

CTRL_SDP1_DATA          = 0x00080000 ; SDP1 data

CTRL_SDP0_IODIR         = 0x00400000 ; SDP0 direction

CTRL_SDP1_IODIR         = 0x00800000 ; SDP1 direction

CTRL_RST                = 0x04000000 ; Device Reset

CTRL_RFCE               = 0x08000000 ; RX Flow Ctrl Enable

CTRL_TFCE               = 0x10000000 ; TX Flow Ctrl Enable

CTRL_VME                = 0x40000000 ; VLAN Mode Enable

CTRL_PHY_RST            = 0x80000000 ; PHY reset

; STATUS - Device Status Register (0x0008)

STATUS_FD               = 0x00000001 ; Full Duplex

STATUS_LU               = 0x00000002 ; Link Up

STATUS_TXOFF            = 0x00000010 ; Transmit paused

STATUS_TBIMODE          = 0x00000020 ; TBI Mode

STATUS_SPEED_MASK       = 0x000000C0 ; Link Speed setting

STATUS_SPEED_SHIFT      = 6

STATUS_ASDV_MASK        = 0x00000300 ; Auto Speed Detection

STATUS_ASDV_SHIFT       = 8

STATUS_PCI66            = 0x00000800 ; PCI bus speed

STATUS_BUS64            = 0x00001000 ; PCI bus width

STATUS_PCIX_MODE        = 0x00002000 ; PCI-X mode

STATUS_PCIXSPD_MASK     = 0x0000C000 ; PCI-X speed

STATUS_PCIXSPD_SHIFT    = 14

; CTRL_EXT - Extended Device Control Register (0x0018)

CTRLEXT_PHY_INT         = 0x00000020 ; PHY interrupt

CTRLEXT_SDP6_DATA       = 0x00000040 ; SDP6 data

CTRLEXT_SDP7_DATA       = 0x00000080 ; SDP7 data

CTRLEXT_SDP6_IODIR      = 0x00000400 ; SDP6 direction

CTRLEXT_SDP7_IODIR      = 0x00000800 ; SDP7 direction

CTRLEXT_ASDCHK          = 0x00001000 ; Auto-Speed Detect Chk

CTRLEXT_EE_RST          = 0x00002000 ; EEPROM reset

CTRLEXT_SPD_BYPS        = 0x00008000 ; Speed Select Bypass

CTRLEXT_RO_DIS          = 0x00020000 ; Relaxed Ordering Dis.

CTRLEXT_LNKMOD_MASK     = 0x00C00000 ; Link Mode

CTRLEXT_LNKMOD_SHIFT    = 22

; MDIC - MDI Control Register (0x0020)

MDIC_DATA_MASK          = 0x0000FFFF ; Data

MDIC_REG_MASK           = 0x001F0000 ; PHY Register

MDIC_REG_SHIFT          = 16

MDIC_PHY_MASK           = 0x03E00000 ; PHY Address

MDIC_PHY_SHIFT          = 21

MDIC_OP_MASK            = 0x0C000000 ; Opcode

MDIC_OP_SHIFT           = 26

MDIC_R                  = 0x10000000 ; Ready

MDIC_I                  = 0x20000000 ; Interrupt Enable

MDIC_E                  = 0x40000000 ; Error

; ICR - Interrupt Cause Read (0x00c0)

ICR_TXDW                = 0x00000001 ; TX Desc Written back

ICR_TXQE                = 0x00000002 ; TX Queue Empty

ICR_LSC                 = 0x00000004 ; Link Status Change

ICR_RXSEQ               = 0x00000008 ; RX Sence Error

ICR_RXDMT0              = 0x00000010 ; RX Desc min threshold reached

ICR_RXO                 = 0x00000040 ; RX Overrun

ICR_RXT0                = 0x00000080 ; RX Timer Interrupt

ICR_MDAC                = 0x00000200 ; MDIO Access Complete

ICR_RXCFG               = 0x00000400

ICR_PHY_INT             = 0x00001000 ; PHY Interrupt

ICR_GPI_SDP6            = 0x00002000 ; GPI on SDP6

ICR_GPI_SDP7            = 0x00004000 ; GPI on SDP7

ICR_TXD_LOW             = 0x00008000 ; TX Desc low threshold hit

ICR_SRPD                = 0x00010000 ; Small RX packet detected

; RCTL - Receive Control Register (0x0100)

RCTL_EN                 = 0x00000002 ; Receiver Enable

RCTL_SBP                = 0x00000004 ; Store Bad Packets

RCTL_UPE                = 0x00000008 ; Unicast Promiscuous Enabled

RCTL_MPE                = 0x00000010 ; Xcast Promiscuous Enabled

RCTL_LPE                = 0x00000020 ; Long Packet Reception Enable

RCTL_LBM_MASK           = 0x000000C0 ; Loopback Mode

RCTL_LBM_SHIFT          = 6

RCTL_RDMTS_MASK         = 0x00000300 ; RX Desc Min Threshold Size

RCTL_RDMTS_SHIFT        = 8

RCTL_MO_MASK            = 0x00003000 ; Multicast Offset

RCTL_MO_SHIFT           = 12

RCTL_BAM                = 0x00008000 ; Broadcast Accept Mode

RCTL_BSIZE_MASK         = 0x00030000 ; RX Buffer Size

RCTL_BSIZE_SHIFT        = 16

RCTL_VFE                = 0x00040000 ; VLAN Filter Enable

RCTL_CFIEN              = 0x00080000 ; CFI Enable

RCTL_CFI                = 0x00100000 ; Canonical Form Indicator Bit

RCTL_DPF                = 0x00400000 ; Discard Pause Frames

RCTL_PMCF               = 0x00800000 ; Pass MAC Control Frames

RCTL_BSEX               = 0x02000000 ; Buffer Size Extension

RCTL_SECRC              = 0x04000000 ; Strip Ethernet CRC

; TCTL - Transmit Control Register (0x0400)

TCTL_EN                 = 0x00000002 ; Transmit Enable

TCTL_PSP                = 0x00000008 ; Pad short packets

TCTL_SWXOFF             = 0x00400000 ; Software XOFF Transmission

; PBA - Packet Buffer Allocation (0x1000)

PBA_RXA_MASK            = 0x0000FFFF ; RX Packet Buffer

PBA_RXA_SHIFT           = 0

PBA_TXA_MASK            = 0xFFFF0000 ; TX Packet Buffer

PBA_TXA_SHIFT           = 16

; Flow Control Type

FCT_TYPE_DEFAULT        = 0x8808

; === TX Descriptor fields ===

; TX Packet Length (word 2)

TXDESC_LEN_MASK         = 0x0000ffff

; TX Descriptor CMD field (word 2)

TXDESC_IDE              = 0x80000000 ; Interrupt Delay Enable

TXDESC_VLE              = 0x40000000 ; VLAN Packet Enable

TXDESC_DEXT             = 0x20000000 ; Extension

TXDESC_RPS              = 0x10000000 ; Report Packet Sent

TXDESC_RS               = 0x08000000 ; Report Status

TXDESC_IC               = 0x04000000 ; Insert Checksum

TXDESC_IFCS             = 0x02000000 ; Insert FCS

TXDESC_EOP              = 0x01000000 ; End Of Packet

; TX Descriptor STA field (word 3)

TXDESC_TU               = 0x00000008 ; Transmit Underrun

TXDESC_LC               = 0x00000004 ; Late Collision

TXDESC_EC               = 0x00000002 ; Excess Collisions

TXDESC_DD               = 0x00000001 ; Descriptor Done

; === RX Descriptor fields ===

; RX Packet Length (word 2)

RXDESC_LEN_MASK         = 0x0000ffff