WebSVN – Kolibri OS – Blame – /drivers/ethernet/RTL8169.asm

Rev	Author	Line No.	Line
3545	hidnplayr	1	;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
		2	;; ;;
5363	yogev_ezra	3	;; Copyright (C) KolibriOS team 2004-2015. All rights reserved. ;;
3545	hidnplayr	4	;; Distributed under terms of the GNU General Public License ;;
		5	;; ;;
		6	;; RTL8169 driver for KolibriOS ;;
		7	;; ;;
		8	;; Copyright 2007 mike.dld, ;;
		9	;; mike.dld@gmail.com ;;
		10	;; ;;
		11	;; port to net branch by hidnplayr ;;
		12	;; ;;
		13	;; References: ;;
		14	;; r8169.c - linux driver (etherboot project) ;;
		15	;; ;;
		16	;; GNU GENERAL PUBLIC LICENSE ;;
		17	;; Version 2, June 1991 ;;
		18	;; ;;
		19	;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
		20
5050	hidnplayr	21	format PE DLL native
		22	entry START
3545	hidnplayr	23
5050	hidnplayr	24	CURRENT_API = 0x0200
		25	COMPATIBLE_API = 0x0100
		26	API_VERSION = (COMPATIBLE_API shl 16) + CURRENT_API
3545	hidnplayr	27
		28	MAX_DEVICES = 16
		29
		30	__DEBUG__ = 1
5050	hidnplayr	31	__DEBUG_LEVEL__ = 2 ; 1 = verbose, 2 = errors only
3545	hidnplayr	32
		33	NUM_TX_DESC = 4
		34	NUM_RX_DESC = 4
		35
5050	hidnplayr	36	section '.flat' readable writable executable
		37
		38	include '../proc32.inc'
4467	hidnplayr	39	include '../struct.inc'
		40	include '../macros.inc'
3545	hidnplayr	41	include '../fdo.inc'
5074	hidnplayr	42	include '../netdrv.inc'
3545	hidnplayr	43
		44	REG_MAC0 = 0x0 ; Ethernet hardware address
		45	REG_MAR0 = 0x8 ; Multicast filter
		46	REG_TxDescStartAddr = 0x20
		47	REG_TxHDescStartAddr = 0x28
		48	REG_FLASH = 0x30
		49	REG_ERSR = 0x36
		50	REG_ChipCmd = 0x37
		51	REG_TxPoll = 0x38
		52	REG_IntrMask = 0x3C
		53	REG_IntrStatus = 0x3E
		54	REG_TxConfig = 0x40
		55	REG_RxConfig = 0x44
		56	REG_RxMissed = 0x4C
		57	REG_Cfg9346 = 0x50
		58	REG_Config0 = 0x51
		59	REG_Config1 = 0x52
		60	REG_Config2 = 0x53
		61	REG_Config3 = 0x54
		62	REG_Config4 = 0x55
		63	REG_Config5 = 0x56
		64	REG_MultiIntr = 0x5C
		65	REG_PHYAR = 0x60
		66	REG_TBICSR = 0x64
		67	REG_TBI_ANAR = 0x68
		68	REG_TBI_LPAR = 0x6A
		69	REG_PHYstatus = 0x6C
		70	REG_RxMaxSize = 0xDA
		71	REG_CPlusCmd = 0xE0
		72	REG_RxDescStartAddr = 0xE4
		73	REG_ETThReg = 0xEC
		74	REG_FuncEvent = 0xF0
		75	REG_FuncEventMask = 0xF4
		76	REG_FuncPresetState = 0xF8
		77	REG_FuncForceEvent = 0xFC
		78
		79	; InterruptStatusBits
		80	ISB_SYSErr = 0x8000
		81	ISB_PCSTimeout = 0x4000
		82	ISB_SWInt = 0x0100
		83	ISB_TxDescUnavail = 0x80
		84	ISB_RxFIFOOver = 0x40
		85	ISB_LinkChg = 0x20
		86	ISB_RxOverflow = 0x10
		87	ISB_TxErr = 0x08
		88	ISB_TxOK = 0x04
		89	ISB_RxErr = 0x02
		90	ISB_RxOK = 0x01
		91
		92	; RxStatusDesc
		93	SD_RxRES = 0x00200000
		94	SD_RxCRC = 0x00080000
		95	SD_RxRUNT = 0x00100000
		96	SD_RxRWT = 0x00400000
		97
		98	; ChipCmdBits
		99	CMD_Reset = 0x10
		100	CMD_RxEnb = 0x08
		101	CMD_TxEnb = 0x04
		102	CMD_RxBufEmpty = 0x01
		103
		104	; Cfg9346Bits
		105	CFG_9346_Lock = 0x00
		106	CFG_9346_Unlock = 0xC0
		107
		108	; rx_mode_bits
		109	RXM_AcceptErr = 0x20
		110	RXM_AcceptRunt = 0x10
		111	RXM_AcceptBroadcast = 0x08
		112	RXM_AcceptMulticast = 0x04
		113	RXM_AcceptMyPhys = 0x02
		114	RXM_AcceptAllPhys = 0x01
		115
		116	; RxConfigBits
		117	RXC_FIFOShift = 13
		118	RXC_DMAShift = 8
		119
		120	; TxConfigBits
		121	TXC_InterFrameGapShift = 24
		122	TXC_DMAShift = 8 ; DMA burst value (0-7) is shift this many bits
		123
		124	; PHYstatus
		125	PHYS_TBI_Enable = 0x80
		126	PHYS_TxFlowCtrl = 0x40
		127	PHYS_RxFlowCtrl = 0x20
		128	PHYS_1000bpsF = 0x10
		129	PHYS_100bps = 0x08
		130	PHYS_10bps = 0x04
		131	PHYS_LinkStatus = 0x02
		132	PHYS_FullDup = 0x01
		133
		134	; GIGABIT_PHY_registers
		135	PHY_CTRL_REG = 0
		136	PHY_STAT_REG = 1
		137	PHY_AUTO_NEGO_REG = 4
		138	PHY_1000_CTRL_REG = 9
		139
		140	; GIGABIT_PHY_REG_BIT
		141	PHY_Restart_Auto_Nego = 0x0200
		142	PHY_Enable_Auto_Nego = 0x1000
		143
		144	; PHY_STAT_REG = 1
		145	PHY_Auto_Neco_Comp = 0x0020
		146
		147	; PHY_AUTO_NEGO_REG = 4
		148	PHY_Cap_10_Half = 0x0020
		149	PHY_Cap_10_Full = 0x0040
		150	PHY_Cap_100_Half = 0x0080
		151	PHY_Cap_100_Full = 0x0100
		152
		153	; PHY_1000_CTRL_REG = 9
		154	PHY_Cap_1000_Full = 0x0200
		155	PHY_Cap_1000_Half = 0x0100
		156
		157	PHY_Cap_PAUSE = 0x0400
		158	PHY_Cap_ASYM_PAUSE = 0x0800
		159
		160	PHY_Cap_Null = 0x0
		161
		162	; _MediaType
		163	MT_10_Half = 0x01
		164	MT_10_Full = 0x02
		165	MT_100_Half = 0x04
		166	MT_100_Full = 0x08
		167	MT_1000_Full = 0x10
		168
		169	; _TBICSRBit
		170	TBI_LinkOK = 0x02000000
		171
		172	; _DescStatusBit
		173	DSB_OWNbit = 0x80000000
		174	DSB_EORbit = 0x40000000
		175	DSB_FSbit = 0x20000000
		176	DSB_LSbit = 0x10000000
		177
		178	RX_BUF_SIZE = 1536 ; Rx Buffer size
		179
		180	; max supported gigabit ethernet frame size -- must be at least (dev->mtu+14+4)
		181	MAX_ETH_FRAME_SIZE = 1536
		182
		183	TX_FIFO_THRESH = 256 ; In bytes
		184
		185	RX_FIFO_THRESH = 7 ; 7 means NO threshold, Rx buffer level before first PCI xfer
		186	RX_DMA_BURST = 7 ; Maximum PCI burst, '6' is 1024
		187	TX_DMA_BURST = 7 ; Maximum PCI burst, '6' is 1024
		188	ETTh = 0x3F ; 0x3F means NO threshold
		189
		190	EarlyTxThld = 0x3F ; 0x3F means NO early transmit
		191	RxPacketMaxSize = 0x0800 ; Maximum size supported is 16K-1
		192	InterFrameGap = 0x03 ; 3 means InterFrameGap = the shortest one
		193
		194	HZ = 1000
		195
		196	RTL_MIN_IO_SIZE = 0x80
		197	TX_TIMEOUT = (6*HZ)
		198
		199	TIMER_EXPIRE_TIME = 100
		200
		201	ETH_HDR_LEN = 14
		202	DEFAULT_MTU = 1500
		203	DEFAULT_RX_BUF_LEN = 1536
		204
		205
		206	;ifdef JUMBO_FRAME_SUPPORT
		207	; MAX_JUMBO_FRAME_MTU = 10000
		208	; MAX_RX_SKBDATA_SIZE = (MAX_JUMBO_FRAME_MTU + ETH_HDR_LEN )
		209	;else
		210	MAX_RX_SKBDATA_SIZE = 1600
		211	;end if
		212
		213	MCFG_METHOD_01 = 0x01
		214	MCFG_METHOD_02 = 0x02
		215	MCFG_METHOD_03 = 0x03
		216	MCFG_METHOD_04 = 0x04
		217	MCFG_METHOD_05 = 0x05
		218	MCFG_METHOD_11 = 0x0b
		219	MCFG_METHOD_12 = 0x0c
		220	MCFG_METHOD_13 = 0x0d
		221	MCFG_METHOD_14 = 0x0e
		222	MCFG_METHOD_15 = 0x0f
		223
		224	PCFG_METHOD_1 = 0x01 ; PHY Reg 0x03 bit0-3 == 0x0000
		225	PCFG_METHOD_2 = 0x02 ; PHY Reg 0x03 bit0-3 == 0x0001
		226	PCFG_METHOD_3 = 0x03 ; PHY Reg 0x03 bit0-3 == 0x0002
		227
5050	hidnplayr	228	struct tx_desc
		229	status dd ?
		230	vlan_tag dd ?
		231	buf_addr dq ?
		232	ends
		233	tx_desc.buf_soft_addr = NUM_TX_DESC*sizeof.tx_desc
3545	hidnplayr	234
5050	hidnplayr	235	struct rx_desc
		236	status dd ?
		237	vlan_tag dd ?
		238	buf_addr dq ?
		239	ends
		240	rx_desc.buf_soft_addr = NUM_RX_DESC*sizeof.rx_desc
3545	hidnplayr	241
5050	hidnplayr	242	struct device ETH_DEVICE
3545	hidnplayr	243
5050	hidnplayr	244	io_addr dd ?
		245	pci_bus dd ?
		246	pci_dev dd ?
		247	irq_line db ?
		248	rb 3 ; align 4
		249	mmio_addr dd ? ; memory map physical address
		250	pcfg dd ?
		251	mcfg dd ?
		252	cur_rx dd ? ; Index into the Rx descriptor buffer of next Rx pkt
		253	cur_tx dd ? ; Index into the Tx descriptor buffer of next Rx pkt
		254	TxDescArrays dd ? ; Index of Tx Descriptor buffer
		255	RxDescArrays dd ? ; Index of Rx Descriptor buffer
		256	TxDescArray dd ? ; Index of 256-alignment Tx Descriptor buffer
		257	RxDescArray dd ? ; Index of 256-alignment Rx Descriptor buffer
5494	hidnplayr	258	mac_version dd ?
3545	hidnplayr	259
5050	hidnplayr	260	rb 0x100-($ and 0xff) ; align 256
		261	tx_ring rb NUM_TX_DESC * sizeof.tx_desc * 2
3545	hidnplayr	262
5050	hidnplayr	263	rb 0x100-($ and 0xff) ; align 256
		264	rx_ring rb NUM_RX_DESC * sizeof.rx_desc * 2
3545	hidnplayr	265
5050	hidnplayr	266	ends
3545	hidnplayr	267
		268	intr_mask = ISB_LinkChg or ISB_RxOverflow or ISB_RxFIFOOver or ISB_TxErr or ISB_TxOK or ISB_RxErr or ISB_RxOK
		269	rx_config = (RX_FIFO_THRESH shl RXC_FIFOShift) or (RX_DMA_BURST shl RXC_DMAShift) or 0x0000000E
		270
		271
		272	macro udelay msec {
		273
4803	hidnplayr	274	push esi ecx
3545	hidnplayr	275	mov esi, msec
5050	hidnplayr	276	invoke Sleep
4803	hidnplayr	277	pop ecx esi
3545	hidnplayr	278
		279	}
		280
		281	macro WRITE_GMII_REG RegAddr, value {
		282
5050	hidnplayr	283	set_io [ebx + device.io_addr], REG_PHYAR
3545	hidnplayr	284	if value eq ax
		285	and eax, 0x0000ffff
		286	or eax, 0x80000000 + (RegAddr shl 16)
		287	else
		288	mov eax, 0x80000000 + (RegAddr shl 16) + value
		289	end if
		290	out dx, eax
		291
		292	call PHY_WAIT_WRITE
		293	}
		294
		295	macro READ_GMII_REG RegAddr {
		296
		297	local .error, .done
		298
5050	hidnplayr	299	set_io [ebx + device.io_addr], REG_PHYAR
3545	hidnplayr	300	mov eax, RegAddr shl 16
		301	out dx, eax
		302
		303	call PHY_WAIT_READ
		304	jz .error
		305
		306	in eax, dx
		307	and eax, 0xFFFF
		308	jmp .done
		309
		310	.error:
		311	or eax, -1
		312	.done:
		313	}
		314
		315	align 4
		316	PHY_WAIT_READ: ; io addr must already be set to REG_PHYAR
		317
		318	udelay 1 ;;;1000
		319
		320	push ecx
		321	mov ecx, 2000
		322	; Check if the RTL8169 has completed writing/reading to the specified MII register
		323	@@:
		324	in eax, dx
		325	test eax, 0x80000000
		326	jnz .exit
		327	udelay 1 ;;;100
		328	loop @b
		329	.exit:
		330	pop ecx
		331	ret
		332
		333	align 4
		334	PHY_WAIT_WRITE: ; io addr must already be set to REG_PHYAR
		335
		336	udelay 1 ;;;1000
		337
		338	push ecx
		339	mov ecx, 2000
		340	; Check if the RTL8169 has completed writing/reading to the specified MII register
		341	@@:
		342	in eax, dx
		343	test eax, 0x80000000
		344	jz .exit
		345	udelay 1 ;;;100
		346	loop @b
		347	.exit:
		348	pop ecx
		349	ret
		350
		351
		352
		353	;;;;;;;;;;;;;;;;;;;;;;;;;;;;
		354	;; ;;
		355	;; proc START ;;
		356	;; ;;
		357	;; (standard driver proc) ;;
		358	;;;;;;;;;;;;;;;;;;;;;;;;;;;;
		359
5050	hidnplayr	360	proc START c, reason:dword, cmdline:dword
3545	hidnplayr	361
5050	hidnplayr	362	cmp [reason], DRV_ENTRY
		363	jne .fail
3545	hidnplayr	364
5050	hidnplayr	365	DEBUGF 2,"Loading driver\n"
		366	invoke RegService, my_service, service_proc
3545	hidnplayr	367	ret
		368
		369	.fail:
5050	hidnplayr	370	xor eax, eax
3545	hidnplayr	371	ret
		372
		373	endp
		374
		375
		376	;;;;;;;;;;;;;;;;;;;;;;;;;;;;
		377	;; ;;
		378	;; proc SERVICE_PROC ;;
		379	;; ;;
		380	;; (standard driver proc) ;;
		381	;;;;;;;;;;;;;;;;;;;;;;;;;;;;
		382
		383	proc service_proc stdcall, ioctl:dword
		384
		385	mov edx, [ioctl]
4470	hidnplayr	386	mov eax, [edx + IOCTL.io_code]
3545	hidnplayr	387
		388	;------------------------------------------------------
		389
		390	cmp eax, 0 ;SRV_GETVERSION
		391	jne @F
		392
4470	hidnplayr	393	cmp [edx + IOCTL.out_size], 4
3545	hidnplayr	394	jb .fail
4470	hidnplayr	395	mov eax, [edx + IOCTL.output]
3545	hidnplayr	396	mov [eax], dword API_VERSION
		397
		398	xor eax, eax
		399	ret
		400
		401	;------------------------------------------------------
		402	@@:
		403	cmp eax, 1 ;SRV_HOOK
		404	jne .fail
		405
4470	hidnplayr	406	cmp [edx + IOCTL.inp_size], 3 ; Data input must be at least 3 bytes
3545	hidnplayr	407	jb .fail
		408
4470	hidnplayr	409	mov eax, [edx + IOCTL.input]
3545	hidnplayr	410	cmp byte [eax], 1 ; 1 means device number and bus number (pci) are given
		411	jne .fail ; other types arent supported for this card yet
		412
		413	; check if the device is already listed
		414
		415	mov esi, device_list
		416	mov ecx, [devices]
		417	test ecx, ecx
		418	jz .firstdevice
		419
4470	hidnplayr	420	; mov eax, [edx + IOCTL.input] ; get the pci bus and device numbers
		421	mov ax, [eax+1] ;
3545	hidnplayr	422	.nextdevice:
		423	mov ebx, [esi]
5050	hidnplayr	424	cmp al, byte[ebx + device.pci_bus]
3545	hidnplayr	425	jne @f
5050	hidnplayr	426	cmp ah, byte[ebx + device.pci_dev]
3545	hidnplayr	427	je .find_devicenum ; Device is already loaded, let's find it's device number
		428	@@:
		429	add esi, 4
		430	loop .nextdevice
		431
		432
		433	; This device doesnt have its own eth_device structure yet, lets create one
		434	.firstdevice:
		435	cmp [devices], MAX_DEVICES ; First check if the driver can handle one more card
		436	jae .fail
		437
5050	hidnplayr	438	allocate_and_clear ebx, sizeof.device, .fail ; Allocate memory to put the device structure in
3545	hidnplayr	439
		440	; Fill in the direct call addresses into the struct
		441
5050	hidnplayr	442	mov [ebx + device.reset], reset
		443	mov [ebx + device.transmit], transmit
		444	mov [ebx + device.unload], unload
		445	mov [ebx + device.name], my_service
3545	hidnplayr	446
		447	; save the pci bus and device numbers
		448
4470	hidnplayr	449	mov eax, [edx + IOCTL.input]
3545	hidnplayr	450	movzx ecx, byte[eax+1]
5050	hidnplayr	451	mov [ebx + device.pci_bus], ecx
3545	hidnplayr	452	movzx ecx, byte[eax+2]
5050	hidnplayr	453	mov [ebx + device.pci_dev], ecx
3545	hidnplayr	454
		455	; Now, it's time to find the base io addres of the PCI device
		456
5050	hidnplayr	457	stdcall PCI_find_io, [ebx + device.pci_bus], [ebx + device.pci_dev]
		458	mov [ebx + device.io_addr], eax
3545	hidnplayr	459
		460	; We've found the io address, find IRQ now
		461
5050	hidnplayr	462	invoke PciRead8, [ebx + device.pci_bus], [ebx + device.pci_dev], PCI_header00.interrupt_line
		463	mov [ebx + device.irq_line], al
3545	hidnplayr	464
		465	DEBUGF 2,"Hooking into device, dev:%x, bus:%x, irq:%x, addr:%x\n",\
5050	hidnplayr	466	[ebx + device.pci_dev]:1,[ebx + device.pci_bus]:1,[ebx + device.irq_line]:1,[ebx + device.io_addr]:8
3545	hidnplayr	467
		468	; Ok, the eth_device structure is ready, let's probe the device
		469	; Because initialization fires IRQ, IRQ handler must be aware of this device
		470	mov eax, [devices] ; Add the device structure to our device list
		471	mov [device_list + 4*eax], ebx ; (IRQ handler uses this list to find device)
		472	inc [devices] ;
		473
		474	call probe ; this function will output in eax
		475	test eax, eax
		476	jnz .err2 ; If an error occured, exit
		477
5050	hidnplayr	478	mov [ebx + device.type], NET_TYPE_ETH
		479	invoke NetRegDev
3545	hidnplayr	480
		481	cmp eax, -1
		482	je .destroy
		483
		484	ret
		485
		486	; If the device was already loaded, find the device number and return it in eax
		487
		488	.find_devicenum:
		489	DEBUGF 2,"Trying to find device number of already registered device\n"
5050	hidnplayr	490	invoke NetPtrToNum ; This kernel procedure converts a pointer to device struct in ebx
3545	hidnplayr	491	; into a device number in edi
		492	mov eax, edi ; Application wants it in eax instead
		493	DEBUGF 2,"Kernel says: %u\n", eax
		494	ret
		495
		496	; If an error occured, remove all allocated data and exit (returning -1 in eax)
		497
		498	.destroy:
		499	; todo: reset device into virgin state
		500
		501	.err2:
		502	dec [devices]
		503	.err:
		504	DEBUGF 2,"removing device structure\n"
5050	hidnplayr	505	invoke KernelFree, ebx
3545	hidnplayr	506	.fail:
		507	or eax, -1
		508	ret
		509
		510	;------------------------------------------------------
		511	endp
		512
		513
		514	align 4
		515	unload:
		516
		517	ret
		518
		519
		520	align 4
		521	init_board:
		522
		523	DEBUGF 1,"init_board\n"
		524
5050	hidnplayr	525	; Make the device a bus master
		526	invoke PciRead32, [ebx + device.pci_bus], [ebx + device.pci_dev], PCI_header00.command
		527	or al, PCI_CMD_MASTER
		528	invoke PciWrite32, [ebx + device.pci_bus], [ebx + device.pci_dev], PCI_header00.command, eax
3545	hidnplayr	529
		530	; Soft reset the chip
5050	hidnplayr	531	set_io [ebx + device.io_addr], 0
		532	set_io [ebx + device.io_addr], REG_ChipCmd
3545	hidnplayr	533	mov al, CMD_Reset
		534	out dx, al
		535
		536	; Check that the chip has finished the reset
		537	mov ecx, 1000
5050	hidnplayr	538	set_io [ebx + device.io_addr], REG_ChipCmd
5494	hidnplayr	539	@@:
		540	in al, dx
3545	hidnplayr	541	test al, CMD_Reset
		542	jz @f
		543	udelay 10
		544	loop @b
5494	hidnplayr	545	@@:
3545	hidnplayr	546
		547
5050	hidnplayr	548	set_io [ebx + device.io_addr], REG_TxConfig
3545	hidnplayr	549	in eax, dx
5494	hidnplayr	550	mov esi, MAC_VERSION_LIST
		551	@@:
		552	mov ecx, eax
		553	and ecx, dword[esi]
		554	cmp ecx, dword[esi+4]
		555	je @f
		556	add esi, 4*4
		557	jmp @r
		558	@@:
3545	hidnplayr	559
5494	hidnplayr	560	mov eax, [esi+8]
		561	mov [ebx + device.mac_version], eax
		562	mov eax, [esi+12]
		563	mov [ebx + device.name], eax
3545	hidnplayr	564
		565	xor eax, eax
		566	ret
		567
		568
		569
		570	;***************************************************************************
		571	; Function
		572	; probe
		573	; Description
		574	; Searches for an ethernet card, enables it and clears the rx buffer
		575	; If a card was found, it enables the ethernet -> TCPIP link
		576	; Destroyed registers
		577	; eax, ebx, ecx, edx
		578	;
		579	;***************************************************************************
		580	align 4
		581	probe:
		582
		583	DEBUGF 1,"probe\n"
		584
		585	call init_board
		586	call read_mac
		587	call PHY_config
		588
4334	hidnplayr	589	DEBUGF 1,"Set MAC Reg C+CR Offset 0x82h = 0x01h\n"
5050	hidnplayr	590	set_io [ebx + device.io_addr], 0
		591	set_io [ebx + device.io_addr], 0x82
3545	hidnplayr	592	mov al, 0x01
		593	out dx, al
5050	hidnplayr	594	cmp [ebx + device.mcfg], MCFG_METHOD_03
3545	hidnplayr	595	jae @f
4334	hidnplayr	596	DEBUGF 1,"Set PCI Latency=0x40\n"
5050	hidnplayr	597	; Adjust PCI latency to be at least 64
		598	invoke PciRead8, [ebx + device.pci_bus], [ebx + device.pci_dev], PCI_header00.max_latency
		599	cmp al, 64
		600	jae @f
		601	mov al, 64
		602	invoke PciWrite8, [ebx + device.pci_bus], [ebx + device.pci_dev], PCI_header00.max_latency, eax
		603	@@:
		604	cmp [ebx + device.mcfg], MCFG_METHOD_02
3545	hidnplayr	605	jne @f
4334	hidnplayr	606	DEBUGF 1,"Set MAC Reg C+CR Offset 0x82h = 0x01h\n"
5050	hidnplayr	607	set_io [ebx + device.io_addr], 0
		608	set_io [ebx + device.io_addr], 0x82
3545	hidnplayr	609	mov al, 0x01
		610	out dx, al
4334	hidnplayr	611	DEBUGF 1,"Set PHY Reg 0x0bh = 0x00h\n"
3545	hidnplayr	612	WRITE_GMII_REG 0x0b, 0x0000 ; w 0x0b 15 0 0
		613	@@:
		614	; if TBI is not enabled
5050	hidnplayr	615	set_io [ebx + device.io_addr], 0
		616	set_io [ebx + device.io_addr], REG_PHYstatus
3545	hidnplayr	617	in al, dx
		618	test al, PHYS_TBI_Enable
		619	jz .tbi_dis
		620	READ_GMII_REG PHY_AUTO_NEGO_REG
		621
		622	; enable 10/100 Full/Half Mode, leave PHY_AUTO_NEGO_REG bit4:0 unchanged
		623	and eax, 0x0C1F
		624	or eax, PHY_Cap_10_Half or PHY_Cap_10_Full or PHY_Cap_100_Half or PHY_Cap_100_Full
		625	WRITE_GMII_REG PHY_AUTO_NEGO_REG, ax
		626
		627	; enable 1000 Full Mode
		628	WRITE_GMII_REG PHY_1000_CTRL_REG, PHY_Cap_1000_Full or PHY_Cap_1000_Half ; rtl8168
		629
		630	; Enable auto-negotiation and restart auto-nigotiation
		631	WRITE_GMII_REG PHY_CTRL_REG, PHY_Enable_Auto_Nego or PHY_Restart_Auto_Nego
		632
4803	hidnplayr	633	udelay 1 ; 100
		634	mov ecx, 200 ; 10000
		635	DEBUGF 1, "Waiting for auto-negotiation to complete\n"
3545	hidnplayr	636	; wait for auto-negotiation process
		637	@@: dec ecx
		638	jz @f
5050	hidnplayr	639	set_io [ebx + device.io_addr], 0
3545	hidnplayr	640	READ_GMII_REG PHY_STAT_REG
4803	hidnplayr	641	udelay 1 ; 100
3545	hidnplayr	642	test eax, PHY_Auto_Neco_Comp
		643	jz @b
5050	hidnplayr	644	set_io [ebx + device.io_addr], REG_PHYstatus
3545	hidnplayr	645	in al, dx
		646	jmp @f
		647	.tbi_dis:
4803	hidnplayr	648	udelay 1 ; 100
3545	hidnplayr	649	@@:
4803	hidnplayr	650	DEBUGF 1, "auto-negotiation complete\n"
3545	hidnplayr	651
		652	;***************************************************************************
		653	; Function
		654	; rt8169_reset
		655	; Description
		656	; Place the chip (ie, the ethernet card) into a virgin state
		657	; Destroyed registers
		658	; eax, ebx, ecx, edx
		659	;
		660	;***************************************************************************
		661	align 4
		662	reset:
		663
4803	hidnplayr	664	DEBUGF 1,"resetting\n"
3545	hidnplayr	665
5050	hidnplayr	666	lea eax, [ebx + device.tx_ring]
		667	mov [ebx + device.TxDescArrays], eax
		668	mov [ebx + device.TxDescArray], eax
3545	hidnplayr	669
5050	hidnplayr	670	lea eax, [ebx + device.rx_ring]
		671	mov [ebx + device.RxDescArrays], eax
		672	mov [ebx + device.RxDescArray], eax
3545	hidnplayr	673
		674	call init_ring
		675	call hw_start
		676
		677	; clear packet/byte counters
		678
		679	xor eax, eax
5050	hidnplayr	680	lea edi, [ebx + device.bytes_tx]
3545	hidnplayr	681	mov ecx, 6
		682	rep stosd
		683
5050	hidnplayr	684	mov [ebx + device.mtu], 1500
3545	hidnplayr	685
		686	; Set link state to unknown
5050	hidnplayr	687	mov [ebx + device.state], ETH_LINK_UNKNOWN
3545	hidnplayr	688
4803	hidnplayr	689	DEBUGF 2,"init OK!\n"
3545	hidnplayr	690	xor eax, eax
		691	ret
		692
		693
		694
		695
		696
		697	align 4
		698	PHY_config:
		699
5050	hidnplayr	700	DEBUGF 1,"hw_PHY_config: priv.mcfg=%d, priv.pcfg=%d\n", [ebx + device.mcfg], [ebx + device.pcfg]
3545	hidnplayr	701
5050	hidnplayr	702	cmp [ebx + device.mcfg], MCFG_METHOD_04
3545	hidnplayr	703	jne .not_4
5050	hidnplayr	704	set_io [ebx + device.io_addr], 0
3545	hidnplayr	705	; WRITE_GMII_REG 0x1F, 0x0001
		706	; WRITE_GMII_REG 0x1b, 0x841e
		707	; WRITE_GMII_REG 0x0e, 0x7bfb
		708	; WRITE_GMII_REG 0x09, 0x273a
		709	WRITE_GMII_REG 0x1F, 0x0002
		710	WRITE_GMII_REG 0x01, 0x90D0
		711	WRITE_GMII_REG 0x1F, 0x0000
		712	jmp .exit
		713	.not_4:
5050	hidnplayr	714	cmp [ebx + device.mcfg], MCFG_METHOD_02
3545	hidnplayr	715	je @f
5050	hidnplayr	716	cmp [ebx + device.mcfg], MCFG_METHOD_03
3545	hidnplayr	717	jne .not_2_or_3
		718	@@:
5050	hidnplayr	719	set_io [ebx + device.io_addr], 0
3545	hidnplayr	720	WRITE_GMII_REG 0x1F, 0x0001
		721	WRITE_GMII_REG 0x15, 0x1000
		722	WRITE_GMII_REG 0x18, 0x65C7
		723	WRITE_GMII_REG 0x04, 0x0000
		724	WRITE_GMII_REG 0x03, 0x00A1
		725	WRITE_GMII_REG 0x02, 0x0008
		726	WRITE_GMII_REG 0x01, 0x1020
		727	WRITE_GMII_REG 0x00, 0x1000
		728	WRITE_GMII_REG 0x04, 0x0800
		729	WRITE_GMII_REG 0x04, 0x0000
		730	WRITE_GMII_REG 0x04, 0x7000
		731	WRITE_GMII_REG 0x03, 0xFF41
		732	WRITE_GMII_REG 0x02, 0xDE60
		733	WRITE_GMII_REG 0x01, 0x0140
		734	WRITE_GMII_REG 0x00, 0x0077
		735	WRITE_GMII_REG 0x04, 0x7800
		736	WRITE_GMII_REG 0x04, 0x7000
		737	WRITE_GMII_REG 0x04, 0xA000
		738	WRITE_GMII_REG 0x03, 0xDF01
		739	WRITE_GMII_REG 0x02, 0xDF20
		740	WRITE_GMII_REG 0x01, 0xFF95
		741	WRITE_GMII_REG 0x00, 0xFA00
		742	WRITE_GMII_REG 0x04, 0xA800
		743	WRITE_GMII_REG 0x04, 0xA000
		744	WRITE_GMII_REG 0x04, 0xB000
		745	WRITE_GMII_REG 0x03, 0xFF41
		746	WRITE_GMII_REG 0x02, 0xDE20
		747	WRITE_GMII_REG 0x01, 0x0140
		748	WRITE_GMII_REG 0x00, 0x00BB
		749	WRITE_GMII_REG 0x04, 0xB800
		750	WRITE_GMII_REG 0x04, 0xB000
		751	WRITE_GMII_REG 0x04, 0xF000
		752	WRITE_GMII_REG 0x03, 0xDF01
		753	WRITE_GMII_REG 0x02, 0xDF20
		754	WRITE_GMII_REG 0x01, 0xFF95
		755	WRITE_GMII_REG 0x00, 0xBF00
		756	WRITE_GMII_REG 0x04, 0xF800
		757	WRITE_GMII_REG 0x04, 0xF000
		758	WRITE_GMII_REG 0x04, 0x0000
		759	WRITE_GMII_REG 0x1F, 0x0000
		760	WRITE_GMII_REG 0x0B, 0x0000
		761	jmp .exit
		762	.not_2_or_3:
5050	hidnplayr	763	DEBUGF 1,"mcfg=%d, discard hw PHY config\n", [ebx + device.mcfg]
3545	hidnplayr	764	.exit:
		765	ret
		766
		767
		768
		769	align 4
		770	set_rx_mode:
		771
		772	DEBUGF 1,"set_rx_mode\n"
		773
		774	; IFF_ALLMULTI
		775	; Too many to filter perfectly -- accept all multicasts
5050	hidnplayr	776	set_io [ebx + device.io_addr], 0
		777	set_io [ebx + device.io_addr], REG_RxConfig
3545	hidnplayr	778	in eax, dx
5494	hidnplayr	779	and eax, 0xff7e1880
3545	hidnplayr	780	or eax, rx_config or (RXM_AcceptBroadcast or RXM_AcceptMulticast or RXM_AcceptMyPhys)
		781	out dx, eax
		782
		783	; Multicast hash filter
5050	hidnplayr	784	set_io [ebx + device.io_addr], REG_MAR0 + 0
3545	hidnplayr	785	or eax, -1
		786	out dx, eax
5050	hidnplayr	787	set_io [ebx + device.io_addr], REG_MAR0 + 4
3545	hidnplayr	788	out dx, eax
		789
		790	ret
		791
		792
		793	align 4
		794	init_ring:
		795
		796	DEBUGF 1,"init_ring\n"
		797
		798	xor eax, eax
5050	hidnplayr	799	mov [ebx + device.cur_rx], eax
		800	mov [ebx + device.cur_tx], eax
3545	hidnplayr	801
5050	hidnplayr	802	lea edi, [ebx + device.tx_ring]
		803	mov ecx, (NUM_TX_DESC * sizeof.tx_desc) / 4
3545	hidnplayr	804	rep stosd
		805
5050	hidnplayr	806	lea edi, [ebx + device.rx_ring]
		807	mov ecx, (NUM_RX_DESC * sizeof.rx_desc) / 4
3545	hidnplayr	808	rep stosd
		809
5050	hidnplayr	810	mov edi, [ebx + device.RxDescArray]
3545	hidnplayr	811	mov ecx, NUM_RX_DESC
		812	.loop:
		813	push ecx
5050	hidnplayr	814	invoke KernelAlloc, RX_BUF_SIZE
		815	mov dword [edi + rx_desc.buf_soft_addr], eax
		816	invoke GetPgAddr
3545	hidnplayr	817	mov dword [edi + rx_desc.buf_addr], eax
		818	mov [edi + rx_desc.status], DSB_OWNbit or RX_BUF_SIZE
5050	hidnplayr	819	add edi, sizeof.rx_desc
3545	hidnplayr	820	pop ecx
5050	hidnplayr	821	dec ecx
		822	jnz .loop
		823	or [edi - sizeof.rx_desc + rx_desc.status], DSB_EORbit
3545	hidnplayr	824
		825	ret
		826
		827
		828	align 4
		829	hw_start:
		830
		831	DEBUGF 1,"hw_start\n"
		832
		833	; attach int handler
5050	hidnplayr	834	movzx eax, [ebx + device.irq_line]
3545	hidnplayr	835	DEBUGF 1,"Attaching int handler to irq %x\n", eax:1
5050	hidnplayr	836	invoke AttachIntHandler, eax, int_handler, ebx
		837	test eax, eax
		838	jnz @f
		839	DEBUGF 2,"Could not attach int handler!\n"
		840	or eax, -1
		841	ret
		842	@@:
3545	hidnplayr	843
		844	; Soft reset the chip
5050	hidnplayr	845	set_io [ebx + device.io_addr], 0
		846	set_io [ebx + device.io_addr], REG_ChipCmd
3545	hidnplayr	847	mov al, CMD_Reset
		848	out dx, al
		849
		850	DEBUGF 1,"Waiting for chip to reset... "
		851	; Check that the chip has finished the reset
		852	mov ecx, 1000
5050	hidnplayr	853	set_io [ebx + device.io_addr], REG_ChipCmd
3545	hidnplayr	854	@@: in al, dx
		855	test al, CMD_Reset
		856	jz @f
		857	udelay 10
		858	loop @b
		859	@@:
		860	DEBUGF 1,"done!\n"
		861
5050	hidnplayr	862	set_io [ebx + device.io_addr], REG_Cfg9346
3545	hidnplayr	863	mov al, CFG_9346_Unlock
		864	out dx, al
		865
5050	hidnplayr	866	set_io [ebx + device.io_addr], REG_ChipCmd
3545	hidnplayr	867	mov al, CMD_TxEnb or CMD_RxEnb
		868	out dx, al
		869
5050	hidnplayr	870	set_io [ebx + device.io_addr], REG_ETThReg
3545	hidnplayr	871	mov al, ETTh
		872	out dx, al
		873
		874	; For gigabit rtl8169
5050	hidnplayr	875	set_io [ebx + device.io_addr], REG_RxMaxSize
3545	hidnplayr	876	mov ax, RxPacketMaxSize
		877	out dx, ax
		878
		879	; Set Rx Config register
5050	hidnplayr	880	set_io [ebx + device.io_addr], REG_RxConfig
3545	hidnplayr	881	in ax, dx
5494	hidnplayr	882	and eax, 0xff7e1880
3545	hidnplayr	883	or eax, rx_config
		884	out dx, eax
		885
		886	; Set DMA burst size and Interframe Gap Time
5050	hidnplayr	887	set_io [ebx + device.io_addr], REG_TxConfig
3545	hidnplayr	888	mov eax, (TX_DMA_BURST shl TXC_DMAShift) or (InterFrameGap shl TXC_InterFrameGapShift)
		889	out dx, eax
		890
5050	hidnplayr	891	set_io [ebx + device.io_addr], REG_CPlusCmd
3545	hidnplayr	892	in ax, dx
		893	out dx, ax
		894
		895	in ax, dx
		896	or ax, 1 shl 3
5050	hidnplayr	897	cmp [ebx + device.mcfg], MCFG_METHOD_02
3545	hidnplayr	898	jne @f
5050	hidnplayr	899	cmp [ebx + device.mcfg], MCFG_METHOD_03
3545	hidnplayr	900	jne @f
		901	or ax,1 shl 14
		902	DEBUGF 1,"Set MAC Reg C+CR Offset 0xE0: bit-3 and bit-14\n"
		903	jmp .set
		904	@@:
		905	DEBUGF 1,"Set MAC Reg C+CR Offset 0xE0: bit-3\n"
		906	.set:
5050	hidnplayr	907	set_io [ebx + device.io_addr], REG_CPlusCmd
3545	hidnplayr	908	out dx, ax
		909
5050	hidnplayr	910	set_io [ebx + device.io_addr], 0xE2
3545	hidnplayr	911	; mov ax, 0x1517
		912	; out dx, ax
		913	; mov ax, 0x152a
		914	; out dx, ax
		915	; mov ax, 0x282a
		916	; out dx, ax
		917	xor ax, ax
		918	out dx, ax
		919
		920	xor eax, eax
5050	hidnplayr	921	mov [ebx + device.cur_rx], eax
		922	lea eax, [ebx + device.tx_ring]
		923	invoke GetPhysAddr
		924	set_io [ebx + device.io_addr], REG_TxDescStartAddr
3545	hidnplayr	925	out dx, eax
5050	hidnplayr	926	set_io [ebx + device.io_addr], REG_TxDescStartAddr + 4
4301	clevermous	927	xor eax, eax
		928	out dx, eax
3545	hidnplayr	929
5050	hidnplayr	930	lea eax, [ebx + device.rx_ring]
		931	invoke GetPhysAddr
		932	set_io [ebx + device.io_addr], REG_RxDescStartAddr
3545	hidnplayr	933	out dx, eax
4301	clevermous	934	xor eax, eax
5050	hidnplayr	935	set_io [ebx + device.io_addr], REG_RxDescStartAddr + 4
4301	clevermous	936	out dx, eax
3545	hidnplayr	937
5050	hidnplayr	938	set_io [ebx + device.io_addr], REG_Cfg9346
3545	hidnplayr	939	mov al, CFG_9346_Lock
		940	out dx, al
		941
		942	udelay 10
		943
		944	xor eax, eax
5050	hidnplayr	945	set_io [ebx + device.io_addr], REG_RxMissed
3545	hidnplayr	946	out dx, eax
		947
		948	call set_rx_mode
		949
5050	hidnplayr	950	set_io [ebx + device.io_addr], 0
3545	hidnplayr	951	; no early-rx interrupts
5050	hidnplayr	952	set_io [ebx + device.io_addr], REG_MultiIntr
3545	hidnplayr	953	in ax, dx
		954	and ax, 0xF000
		955	out dx, ax
		956
		957	; set interrupt mask
5050	hidnplayr	958	set_io [ebx + device.io_addr], REG_IntrMask
3545	hidnplayr	959	mov ax, intr_mask
		960	out dx, ax
		961
		962	xor eax, eax
		963	ret
		964
		965
		966	align 4
		967	read_mac:
		968
5050	hidnplayr	969	set_io [ebx + device.io_addr], 0
		970	set_io [ebx + device.io_addr], REG_MAC0
3545	hidnplayr	971	xor ecx, ecx
5050	hidnplayr	972	lea edi, [ebx + device.mac]
3545	hidnplayr	973	mov ecx, 6
		974
		975	; Get MAC address. FIXME: read EEPROM
		976	@@: in al, dx
		977	stosb
		978	inc edx
		979	loop @r
		980
		981	DEBUGF 1,"MAC = %x-%x-%x-%x-%x-%x\n",\
5050	hidnplayr	982	[ebx + device.mac+0]:2,[ebx + device.mac+1]:2,[ebx + device.mac+2]:2,[ebx + device.mac+3]:2,[ebx + device.mac+4]:2,[ebx + device.mac+5]:2
3545	hidnplayr	983
		984	ret
		985
		986	align 4
		987	write_mac:
		988
		989	ret 6
		990
		991
		992	;***************************************************************************
		993	; Function
		994	; transmit
		995	; Description
		996	; Transmits a packet of data via the ethernet card
		997	;
		998	; Destroyed registers
		999	; eax, edx, esi, edi
		1000	;
		1001	;***************************************************************************
		1002
5050	hidnplayr	1003	proc transmit stdcall bufferptr, buffersize
		1004
		1005	pushf
		1006	cli
		1007
		1008	DEBUGF 1,"Transmitting packet, buffer:%x, size:%u\n", [bufferptr], [buffersize]
		1009	mov eax, [bufferptr]
3545	hidnplayr	1010	DEBUGF 1,"To: %x-%x-%x-%x-%x-%x From: %x-%x-%x-%x-%x-%x Type:%x%x\n",\
		1011	[eax+00]:2,[eax+01]:2,[eax+02]:2,[eax+03]:2,[eax+04]:2,[eax+05]:2,\
		1012	[eax+06]:2,[eax+07]:2,[eax+08]:2,[eax+09]:2,[eax+10]:2,[eax+11]:2,\
		1013	[eax+13]:2,[eax+12]:2
		1014
5050	hidnplayr	1015	cmp [buffersize], 1514
3545	hidnplayr	1016	ja .fail
5050	hidnplayr	1017	cmp [buffersize], 60
		1018	jb .fail
3545	hidnplayr	1019
		1020	;----------------------------------
		1021	; Find currentTX descriptor address
		1022
5050	hidnplayr	1023	mov eax, sizeof.tx_desc
		1024	mul [ebx + device.cur_tx]
		1025	lea esi, [ebx + device.tx_ring + eax]
3545	hidnplayr	1026
		1027	DEBUGF 1,"Using TX desc: %x\n", esi
		1028
		1029	;---------------------------
		1030	; Program the packet pointer
		1031
5050	hidnplayr	1032	mov eax, [bufferptr]
3545	hidnplayr	1033	mov [esi + tx_desc.buf_soft_addr], eax
5050	hidnplayr	1034	invoke GetPhysAddr
3545	hidnplayr	1035	mov dword [esi + tx_desc.buf_addr], eax
		1036
		1037	;------------------------
		1038	; Program the packet size
		1039
5050	hidnplayr	1040	mov eax, [buffersize]
3545	hidnplayr	1041	@@: or eax, DSB_OWNbit or DSB_FSbit or DSB_LSbit
5050	hidnplayr	1042	cmp [ebx + device.cur_tx], NUM_TX_DESC - 1
3545	hidnplayr	1043	jne @f
		1044	or eax, DSB_EORbit
		1045	@@: mov [esi + tx_desc.status], eax
		1046
		1047	;-----------------------------------------
		1048	; Set the polling bit (start transmission)
		1049
5050	hidnplayr	1050	set_io [ebx + device.io_addr], 0
		1051	set_io [ebx + device.io_addr], REG_TxPoll
3545	hidnplayr	1052	mov al, 0x40 ; set polling bit
		1053	out dx, al
		1054
		1055	;-----------------------
		1056	; Update TX descriptor
		1057
5050	hidnplayr	1058	inc [ebx + device.cur_tx]
		1059	and [ebx + device.cur_tx], NUM_TX_DESC - 1
3545	hidnplayr	1060
		1061	;-------------
		1062	; Update stats
		1063
5050	hidnplayr	1064	inc [ebx + device.packets_tx]
		1065	mov eax, [buffersize]
		1066	add dword [ebx + device.bytes_tx], eax
		1067	adc dword [ebx + device.bytes_tx + 4], 0
3545	hidnplayr	1068
5126	hidnplayr	1069	popf
3545	hidnplayr	1070	xor eax, eax
5050	hidnplayr	1071	ret
3545	hidnplayr	1072
		1073	.fail:
5050	hidnplayr	1074	DEBUGF 2,"Transmit failed\n"
		1075	invoke KernelFree, [bufferptr]
		1076	popf
3545	hidnplayr	1077	or eax, -1
5050	hidnplayr	1078	ret
3545	hidnplayr	1079
5050	hidnplayr	1080	endp
3545	hidnplayr	1081
5050	hidnplayr	1082
3545	hidnplayr	1083	;;;DSB_OWNbit
		1084
		1085
		1086	;;;;;;;;;;;;;;;;;;;;;;;
		1087	;; ;;
		1088	;; Interrupt handler ;;
		1089	;; ;;
		1090	;;;;;;;;;;;;;;;;;;;;;;;
		1091
		1092	align 4
		1093	int_handler:
		1094
		1095	push ebx esi edi
		1096
4334	hidnplayr	1097	DEBUGF 1,"INT\n"
3545	hidnplayr	1098
		1099	; find pointer of device wich made IRQ occur
		1100
		1101	mov ecx, [devices]
		1102	test ecx, ecx
		1103	jz .nothing
		1104	mov esi, device_list
		1105	.nextdevice:
		1106	mov ebx, [esi]
		1107
5050	hidnplayr	1108	set_io [ebx + device.io_addr], 0
		1109	set_io [ebx + device.io_addr], REG_IntrStatus
3545	hidnplayr	1110	in ax, dx
		1111	test ax, ax
		1112	jnz .got_it
		1113	.continue:
		1114	add esi, 4
		1115	dec ecx
		1116	jnz .nextdevice
		1117	.nothing:
		1118	pop edi esi ebx
		1119	xor eax, eax
		1120
		1121	ret ; If no device was found, abort (The irq was probably for a device, not registered to this driver)
		1122
		1123	.got_it:
		1124
5050	hidnplayr	1125	DEBUGF 1,"Device: %x Status: %x\n", ebx, ax
3545	hidnplayr	1126
		1127	cmp ax, 0xFFFF ; if so, hardware is no longer present
		1128	je .fail
		1129
		1130	;--------
		1131	; Receive
		1132
		1133	test ax, ISB_RxOK
		1134	jz .no_rx
		1135
		1136	push ax
		1137	push ebx
		1138
		1139	.check_more:
		1140	pop ebx
5050	hidnplayr	1141	mov eax, sizeof.rx_desc
		1142	mul [ebx + device.cur_rx]
		1143	lea esi, [ebx + device.rx_ring + eax]
3545	hidnplayr	1144
		1145	DEBUGF 1,"RxDesc.status = 0x%x\n", [esi + rx_desc.status]
		1146	mov eax, [esi + rx_desc.status]
		1147	test eax, DSB_OWNbit ;;;
		1148	jnz .rx_return
		1149
5050	hidnplayr	1150	DEBUGF 1,"cur_rx = %u\n", [ebx + device.cur_rx]
3545	hidnplayr	1151
		1152	test eax, SD_RxRES
		1153	jnz .rx_return ;;;;; RX error!
		1154
		1155	push ebx
		1156	push .check_more
		1157	and eax, 0x00001FFF
		1158	add eax, -4 ; we dont need CRC
		1159	push eax
		1160	DEBUGF 1,"data length = %u\n", ax
		1161
		1162	;-------------
		1163	; Update stats
		1164
5050	hidnplayr	1165	add dword [ebx + device.bytes_rx], eax
		1166	adc dword [ebx + device.bytes_rx + 4], 0
		1167	inc [ebx + device.packets_rx]
3545	hidnplayr	1168
5050	hidnplayr	1169	pushd [esi + rx_desc.buf_soft_addr]
3545	hidnplayr	1170
		1171	;----------------------
		1172	; Allocate a new buffer
		1173
5050	hidnplayr	1174	invoke KernelAlloc, RX_BUF_SIZE
3545	hidnplayr	1175	mov [esi + rx_desc.buf_soft_addr], eax
5050	hidnplayr	1176	invoke GetPhysAddr
3545	hidnplayr	1177	mov dword [esi + rx_desc.buf_addr], eax
		1178
		1179	;---------------
		1180	; re set OWN bit
		1181
		1182	mov eax, DSB_OWNbit or RX_BUF_SIZE
5050	hidnplayr	1183	cmp [ebx + device.cur_rx], NUM_RX_DESC - 1
3545	hidnplayr	1184	jne @f
		1185	or eax, DSB_EORbit
5050	hidnplayr	1186	@@:
		1187	mov [esi + rx_desc.status], eax
3545	hidnplayr	1188
		1189	;--------------
		1190	; Update rx ptr
		1191
5050	hidnplayr	1192	inc [ebx + device.cur_rx]
		1193	and [ebx + device.cur_rx], NUM_RX_DESC - 1
3545	hidnplayr	1194
5050	hidnplayr	1195	jmp [Eth_input]
3545	hidnplayr	1196	.rx_return:
		1197
		1198	pop ax
		1199	.no_rx:
		1200
		1201	;---------
		1202	; Transmit
		1203
		1204	test ax, ISB_TxOK
		1205	jz .no_tx
		1206	push ax
		1207
		1208	DEBUGF 1,"TX ok!\n"
		1209
		1210	mov ecx, NUM_TX_DESC
5050	hidnplayr	1211	lea esi, [ebx + device.tx_ring]
3545	hidnplayr	1212	.txloop:
5050	hidnplayr	1213	cmp dword [esi + tx_desc.buf_soft_addr], 0
3545	hidnplayr	1214	jz .maybenext
		1215
		1216	test [esi + tx_desc.status], DSB_OWNbit
		1217	jnz .maybenext
		1218
		1219	push ecx
		1220	DEBUGF 1,"Freeing up TX desc: %x\n", esi
5050	hidnplayr	1221	invoke KernelFree, [esi + tx_desc.buf_soft_addr]
3545	hidnplayr	1222	pop ecx
5050	hidnplayr	1223	and dword [esi + tx_desc.buf_soft_addr], 0
3545	hidnplayr	1224
		1225	.maybenext:
5050	hidnplayr	1226	add esi, sizeof.tx_desc
3545	hidnplayr	1227	dec ecx
		1228	jnz .txloop
		1229
		1230	pop ax
		1231	.no_tx:
		1232
		1233	;-------
		1234	; Finish
		1235
5050	hidnplayr	1236	set_io [ebx + device.io_addr], 0
		1237	set_io [ebx + device.io_addr], REG_IntrStatus
3545	hidnplayr	1238	out dx, ax ; ACK all interrupts
		1239
		1240	.fail:
		1241	pop edi esi ebx
		1242	xor eax, eax
		1243	inc eax
		1244
		1245	ret
		1246
		1247
		1248
5050	hidnplayr	1249	; End of code
3545	hidnplayr	1250
5050	hidnplayr	1251	data fixups
		1252	end data
3545	hidnplayr	1253
5050	hidnplayr	1254	include '../peimport.inc'
3545	hidnplayr	1255
		1256	my_service db 'RTL8169',0 ; max 16 chars include zero
		1257
		1258	include_debug_strings ; All data wich FDO uses will be included here
		1259
5494	hidnplayr	1260	MAC_VERSION_LIST:
3545	hidnplayr	1261
5494	hidnplayr	1262	; 8168EP family.
		1263	dd 0x7cf00000, 0x50200000, 51, name_49
		1264	dd 0x7cf00000, 0x50100000, 50, name_49
		1265	dd 0x7cf00000, 0x50000000, 49, name_49
3545	hidnplayr	1266
5494	hidnplayr	1267	; 8168H family.
		1268	dd 0x7cf00000, 0x54100000, 46, name_45
		1269	dd 0x7cf00000, 0x54000000, 45, name_45
3545	hidnplayr	1270
5494	hidnplayr	1271	; 8168G family.
		1272	dd 0x7cf00000, 0x5c800000, 44, name_44
		1273	dd 0x7cf00000, 0x50900000, 42, name_40
		1274	dd 0x7cf00000, 0x4c100000, 41, name_40
		1275	dd 0x7cf00000, 0x4c000000, 40, name_40
		1276
		1277	; 8168F family.
		1278	dd 0x7c800000, 0x48800000, 38, name_38
		1279	dd 0x7cf00000, 0x48100000, 36, name_35
		1280	dd 0x7cf00000, 0x48000000, 35, name_35
		1281
		1282	; 8168E family.
		1283	dd 0x7c800000, 0x2c800000, 34, name_34
		1284	dd 0x7cf00000, 0x2c200000, 33, name_32
		1285	dd 0x7cf00000, 0x2c100000, 32, name_32
		1286	dd 0x7c800000, 0x2c000000, 33, name_32
		1287
		1288	; 8168D family.
		1289	dd 0x7cf00000, 0x28300000, 26, name_25
		1290	dd 0x7cf00000, 0x28100000, 25, name_25
		1291	dd 0x7c800000, 0x28000000, 26, name_25
		1292
		1293	; 8168DP family.
		1294	dd 0x7cf00000, 0x28800000, 27, name_27
		1295	dd 0x7cf00000, 0x28a00000, 28, name_27
		1296
		1297	; 8168C family.
		1298	dd 0x7cf00000, 0x3cb00000, 24, name_23
		1299	dd 0x7cf00000, 0x3c900000, 23, name_23
		1300	dd 0x7cf00000, 0x3c800000, 18, name_18
		1301	dd 0x7c800000, 0x3c800000, 24, name_23
		1302	dd 0x7cf00000, 0x3c000000, 19, name_19
		1303	dd 0x7cf00000, 0x3c200000, 20, name_19
		1304	dd 0x7cf00000, 0x3c300000, 21, name_19
		1305	dd 0x7cf00000, 0x3c400000, 22, name_19
		1306	dd 0x7c800000, 0x3c000000, 22, name_19
		1307
		1308	; 8168B family.
		1309	dd 0x7cf00000, 0x38000000, 12, name_11
		1310	dd 0x7cf00000, 0x38500000, 17, name_10
		1311	dd 0x7c800000, 0x38000000, 17, name_10
		1312	dd 0x7c800000, 0x30000000, 11, name_11
		1313
		1314	; 8101 family.
		1315	dd 0x7cf00000, 0x34a00000, 09, name_07
		1316	dd 0x7cf00000, 0x24a00000, 09, name_07
		1317	dd 0x7cf00000, 0x34900000, 08, name_07
		1318	dd 0x7cf00000, 0x24900000, 08, name_07
		1319	dd 0x7cf00000, 0x34800000, 07, name_07
		1320	dd 0x7cf00000, 0x24800000, 07, name_07
		1321	dd 0x7cf00000, 0x34000000, 13, name_10
		1322	dd 0x7cf00000, 0x34300000, 10, name_10
		1323	dd 0x7cf00000, 0x34200000, 16, name_11
		1324	dd 0x7c800000, 0x34800000, 09, name_07
		1325	dd 0x7c800000, 0x24800000, 09, name_07
		1326	dd 0x7c800000, 0x34000000, 16, name_11
		1327	dd 0xfc800000, 0x38800000, 15, name_14
		1328	dd 0xfc800000, 0x30800000, 14, name_14
		1329
		1330	; 8110 family.
		1331	dd 0xfc800000, 0x98000000, 06, name_05
		1332	dd 0xfc800000, 0x18000000, 05, name_05
		1333	dd 0xfc800000, 0x10000000, 04, name_04
		1334	dd 0xfc800000, 0x04000000, 03, name_03
		1335	dd 0xfc800000, 0x00800000, 02, name_02
		1336	dd 0xfc800000, 0x00000000, 01, name_01
		1337
		1338	; Catch-all
		1339	dd 0x00000000, 0x00000000, 0, name_unknown
		1340
		1341	; PCI-devices
		1342	name_01 db "RTL8169",0
		1343	name_02 db "RTL8169s",0
		1344	name_03 db "RTL8110s",0
		1345	name_04 db "RTL8169sb/8110sb",0
		1346	name_05 db "RTL8169sc/8110sc",0
		1347	;name_06 db "RTL8169sc/8110sc",0
		1348
		1349	; PCI-E devices
		1350	name_07 db "RTL8102e",0
		1351	;name_08 db "RTL8102e",0
		1352	;name_09 db "RTL8102e",0
		1353	name_10 db "RTL8101e",0
		1354	name_11 db "RTL8168b/8111b",0
		1355	;name_12 db "RTL8168b/8111b",0
		1356	;name_13 db "RTL8101e",0
		1357	name_14 db "RTL8100e",0
		1358	;name_15 db "RTL8100e",0
		1359	;name_16 db "RTL8168b/8111b",0
		1360	;name_17 db "RTL8101e",0
		1361	name_18 db "RTL8168cp/8111cp",0
		1362	name_19 db "RTL8168c/8111c",0
		1363	;name_20 db "RTL8168c/8111c",0
		1364	;name_21 db "RTL8168c/8111c",0
		1365	;name_22 db "RTL8168c/8111c",0
		1366	name_23 db "RTL8168cp/8111cp",0
		1367	;name_24 db "RTL8168cp/8111cp",0
		1368	name_25 db "RTL8168d/8111d",0
		1369	;name_26 db "RTL8168d/8111d",0
		1370	name_27 db "RTL8168dp/8111dp",0
		1371	;name_28 db "RTL8168dp/8111dp",0
		1372	name_29 db "RTL8105e",0
		1373	;name_30 db "RTL8105e",0
		1374	;name_31 db "RTL8168dp/8111dp",0
		1375	name_32 db "RTL8168e/8111e",0
		1376	;name_33 db "RTL8168e/8111e",0
		1377	name_34 db "RTL8168evl/8111evl",0
		1378	name_35 db "RTL8168f/8111f",0
		1379	;name_36 db "RTL8168f/8111f",0
		1380	name_37 db "RTL8402",0
		1381	name_38 db "RTL8411",0
		1382	name_39 db "RTL8106e",0
		1383	name_40 db "RTL8168g/8111g",0
		1384	;name_41 db "RTL8168g/8111g",0
		1385	;name_42 db "RTL8168g/8111g",0
		1386	;name_43 db "RTL8106e",0
		1387	name_44 db "RTL8411",0
		1388	name_45 db "RTL8168h/8111h",0
		1389	;name_46 db "RTL8168h/8111h",0
		1390	name_47 db "RTL8107e",0
		1391	;name_48 db "RTL8107e",0
		1392	name_49 db "RTL8168ep/8111ep",0
		1393	;name_50 db "RTL8168ep/8111ep",0
		1394	;name_51 db "RTL8168ep/8111ep",0
		1395
		1396	name_unknown db "unknown RTL8169 clone",0
		1397
5050	hidnplayr	1398	align 4
		1399	devices dd 0
3545	hidnplayr	1400	device_list rd MAX_DEVICES ; This list contains all pointers to device structures the driver is handling
		1401

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(root)/drivers/ethernet/RTL8169.asm @ 5363 – Rev 5494