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Rev | Author | Line No. | Line |
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3545 | hidnplayr | 1 | ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; |
2 | ;; ;; |
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4467 | hidnplayr | 3 | ;; Copyright (C) KolibriOS team 2004-2014. All rights reserved. ;; |
3545 | hidnplayr | 4 | ;; Distributed under terms of the GNU General Public License ;; |
5 | ;; ;; |
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6 | ;; RTL8169 driver for KolibriOS ;; |
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7 | ;; ;; |
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8 | ;; Copyright 2007 mike.dld, ;; |
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9 | ;; mike.dld@gmail.com ;; |
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10 | ;; ;; |
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11 | ;; port to net branch by hidnplayr ;; |
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12 | ;; ;; |
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13 | ;; References: ;; |
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14 | ;; r8169.c - linux driver (etherboot project) ;; |
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15 | ;; ;; |
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16 | ;; GNU GENERAL PUBLIC LICENSE ;; |
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17 | ;; Version 2, June 1991 ;; |
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18 | ;; ;; |
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19 | ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; |
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20 | |||
5050 | hidnplayr | 21 | format PE DLL native |
22 | entry START |
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3545 | hidnplayr | 23 | |
5050 | hidnplayr | 24 | CURRENT_API = 0x0200 |
25 | COMPATIBLE_API = 0x0100 |
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26 | API_VERSION = (COMPATIBLE_API shl 16) + CURRENT_API |
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3545 | hidnplayr | 27 | |
28 | MAX_DEVICES = 16 |
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29 | |||
30 | __DEBUG__ = 1 |
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5050 | hidnplayr | 31 | __DEBUG_LEVEL__ = 2 ; 1 = verbose, 2 = errors only |
3545 | hidnplayr | 32 | |
33 | NUM_TX_DESC = 4 |
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34 | NUM_RX_DESC = 4 |
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35 | |||
5050 | hidnplayr | 36 | section '.flat' readable writable executable |
37 | |||
38 | include '../proc32.inc' |
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4467 | hidnplayr | 39 | include '../struct.inc' |
40 | include '../macros.inc' |
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3545 | hidnplayr | 41 | include '../fdo.inc' |
5074 | hidnplayr | 42 | include '../netdrv.inc' |
3545 | hidnplayr | 43 | |
44 | REG_MAC0 = 0x0 ; Ethernet hardware address |
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45 | REG_MAR0 = 0x8 ; Multicast filter |
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46 | REG_TxDescStartAddr = 0x20 |
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47 | REG_TxHDescStartAddr = 0x28 |
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48 | REG_FLASH = 0x30 |
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49 | REG_ERSR = 0x36 |
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50 | REG_ChipCmd = 0x37 |
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51 | REG_TxPoll = 0x38 |
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52 | REG_IntrMask = 0x3C |
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53 | REG_IntrStatus = 0x3E |
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54 | REG_TxConfig = 0x40 |
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55 | REG_RxConfig = 0x44 |
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56 | REG_RxMissed = 0x4C |
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57 | REG_Cfg9346 = 0x50 |
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58 | REG_Config0 = 0x51 |
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59 | REG_Config1 = 0x52 |
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60 | REG_Config2 = 0x53 |
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61 | REG_Config3 = 0x54 |
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62 | REG_Config4 = 0x55 |
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63 | REG_Config5 = 0x56 |
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64 | REG_MultiIntr = 0x5C |
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65 | REG_PHYAR = 0x60 |
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66 | REG_TBICSR = 0x64 |
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67 | REG_TBI_ANAR = 0x68 |
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68 | REG_TBI_LPAR = 0x6A |
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69 | REG_PHYstatus = 0x6C |
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70 | REG_RxMaxSize = 0xDA |
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71 | REG_CPlusCmd = 0xE0 |
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72 | REG_RxDescStartAddr = 0xE4 |
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73 | REG_ETThReg = 0xEC |
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74 | REG_FuncEvent = 0xF0 |
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75 | REG_FuncEventMask = 0xF4 |
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76 | REG_FuncPresetState = 0xF8 |
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77 | REG_FuncForceEvent = 0xFC |
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78 | |||
79 | ; InterruptStatusBits |
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80 | ISB_SYSErr = 0x8000 |
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81 | ISB_PCSTimeout = 0x4000 |
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82 | ISB_SWInt = 0x0100 |
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83 | ISB_TxDescUnavail = 0x80 |
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84 | ISB_RxFIFOOver = 0x40 |
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85 | ISB_LinkChg = 0x20 |
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86 | ISB_RxOverflow = 0x10 |
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87 | ISB_TxErr = 0x08 |
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88 | ISB_TxOK = 0x04 |
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89 | ISB_RxErr = 0x02 |
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90 | ISB_RxOK = 0x01 |
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91 | |||
92 | ; RxStatusDesc |
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93 | SD_RxRES = 0x00200000 |
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94 | SD_RxCRC = 0x00080000 |
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95 | SD_RxRUNT = 0x00100000 |
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96 | SD_RxRWT = 0x00400000 |
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97 | |||
98 | ; ChipCmdBits |
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99 | CMD_Reset = 0x10 |
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100 | CMD_RxEnb = 0x08 |
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101 | CMD_TxEnb = 0x04 |
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102 | CMD_RxBufEmpty = 0x01 |
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103 | |||
104 | ; Cfg9346Bits |
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105 | CFG_9346_Lock = 0x00 |
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106 | CFG_9346_Unlock = 0xC0 |
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107 | |||
108 | ; rx_mode_bits |
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109 | RXM_AcceptErr = 0x20 |
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110 | RXM_AcceptRunt = 0x10 |
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111 | RXM_AcceptBroadcast = 0x08 |
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112 | RXM_AcceptMulticast = 0x04 |
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113 | RXM_AcceptMyPhys = 0x02 |
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114 | RXM_AcceptAllPhys = 0x01 |
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115 | |||
116 | ; RxConfigBits |
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117 | RXC_FIFOShift = 13 |
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118 | RXC_DMAShift = 8 |
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119 | |||
120 | ; TxConfigBits |
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121 | TXC_InterFrameGapShift = 24 |
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122 | TXC_DMAShift = 8 ; DMA burst value (0-7) is shift this many bits |
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123 | |||
124 | ; PHYstatus |
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125 | PHYS_TBI_Enable = 0x80 |
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126 | PHYS_TxFlowCtrl = 0x40 |
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127 | PHYS_RxFlowCtrl = 0x20 |
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128 | PHYS_1000bpsF = 0x10 |
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129 | PHYS_100bps = 0x08 |
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130 | PHYS_10bps = 0x04 |
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131 | PHYS_LinkStatus = 0x02 |
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132 | PHYS_FullDup = 0x01 |
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133 | |||
134 | ; GIGABIT_PHY_registers |
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135 | PHY_CTRL_REG = 0 |
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136 | PHY_STAT_REG = 1 |
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137 | PHY_AUTO_NEGO_REG = 4 |
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138 | PHY_1000_CTRL_REG = 9 |
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139 | |||
140 | ; GIGABIT_PHY_REG_BIT |
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141 | PHY_Restart_Auto_Nego = 0x0200 |
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142 | PHY_Enable_Auto_Nego = 0x1000 |
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143 | |||
144 | ; PHY_STAT_REG = 1 |
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145 | PHY_Auto_Neco_Comp = 0x0020 |
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146 | |||
147 | ; PHY_AUTO_NEGO_REG = 4 |
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148 | PHY_Cap_10_Half = 0x0020 |
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149 | PHY_Cap_10_Full = 0x0040 |
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150 | PHY_Cap_100_Half = 0x0080 |
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151 | PHY_Cap_100_Full = 0x0100 |
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152 | |||
153 | ; PHY_1000_CTRL_REG = 9 |
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154 | PHY_Cap_1000_Full = 0x0200 |
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155 | PHY_Cap_1000_Half = 0x0100 |
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156 | |||
157 | PHY_Cap_PAUSE = 0x0400 |
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158 | PHY_Cap_ASYM_PAUSE = 0x0800 |
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159 | |||
160 | PHY_Cap_Null = 0x0 |
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161 | |||
162 | ; _MediaType |
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163 | MT_10_Half = 0x01 |
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164 | MT_10_Full = 0x02 |
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165 | MT_100_Half = 0x04 |
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166 | MT_100_Full = 0x08 |
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167 | MT_1000_Full = 0x10 |
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168 | |||
169 | ; _TBICSRBit |
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170 | TBI_LinkOK = 0x02000000 |
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171 | |||
172 | ; _DescStatusBit |
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173 | DSB_OWNbit = 0x80000000 |
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174 | DSB_EORbit = 0x40000000 |
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175 | DSB_FSbit = 0x20000000 |
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176 | DSB_LSbit = 0x10000000 |
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177 | |||
178 | RX_BUF_SIZE = 1536 ; Rx Buffer size |
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179 | |||
180 | ; max supported gigabit ethernet frame size -- must be at least (dev->mtu+14+4) |
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181 | MAX_ETH_FRAME_SIZE = 1536 |
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182 | |||
183 | TX_FIFO_THRESH = 256 ; In bytes |
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184 | |||
185 | RX_FIFO_THRESH = 7 ; 7 means NO threshold, Rx buffer level before first PCI xfer |
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186 | RX_DMA_BURST = 7 ; Maximum PCI burst, '6' is 1024 |
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187 | TX_DMA_BURST = 7 ; Maximum PCI burst, '6' is 1024 |
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188 | ETTh = 0x3F ; 0x3F means NO threshold |
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189 | |||
190 | EarlyTxThld = 0x3F ; 0x3F means NO early transmit |
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191 | RxPacketMaxSize = 0x0800 ; Maximum size supported is 16K-1 |
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192 | InterFrameGap = 0x03 ; 3 means InterFrameGap = the shortest one |
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193 | |||
194 | HZ = 1000 |
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195 | |||
196 | RTL_MIN_IO_SIZE = 0x80 |
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197 | TX_TIMEOUT = (6*HZ) |
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198 | |||
199 | TIMER_EXPIRE_TIME = 100 |
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200 | |||
201 | ETH_HDR_LEN = 14 |
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202 | DEFAULT_MTU = 1500 |
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203 | DEFAULT_RX_BUF_LEN = 1536 |
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204 | |||
205 | |||
206 | ;ifdef JUMBO_FRAME_SUPPORT |
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207 | ; MAX_JUMBO_FRAME_MTU = 10000 |
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208 | ; MAX_RX_SKBDATA_SIZE = (MAX_JUMBO_FRAME_MTU + ETH_HDR_LEN ) |
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209 | ;else |
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210 | MAX_RX_SKBDATA_SIZE = 1600 |
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211 | ;end if |
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212 | |||
213 | MCFG_METHOD_01 = 0x01 |
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214 | MCFG_METHOD_02 = 0x02 |
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215 | MCFG_METHOD_03 = 0x03 |
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216 | MCFG_METHOD_04 = 0x04 |
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217 | MCFG_METHOD_05 = 0x05 |
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218 | MCFG_METHOD_11 = 0x0b |
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219 | MCFG_METHOD_12 = 0x0c |
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220 | MCFG_METHOD_13 = 0x0d |
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221 | MCFG_METHOD_14 = 0x0e |
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222 | MCFG_METHOD_15 = 0x0f |
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223 | |||
224 | PCFG_METHOD_1 = 0x01 ; PHY Reg 0x03 bit0-3 == 0x0000 |
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225 | PCFG_METHOD_2 = 0x02 ; PHY Reg 0x03 bit0-3 == 0x0001 |
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226 | PCFG_METHOD_3 = 0x03 ; PHY Reg 0x03 bit0-3 == 0x0002 |
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227 | |||
5050 | hidnplayr | 228 | struct tx_desc |
229 | status dd ? |
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230 | vlan_tag dd ? |
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231 | buf_addr dq ? |
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232 | ends |
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233 | tx_desc.buf_soft_addr = NUM_TX_DESC*sizeof.tx_desc |
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3545 | hidnplayr | 234 | |
5050 | hidnplayr | 235 | struct rx_desc |
236 | status dd ? |
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237 | vlan_tag dd ? |
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238 | buf_addr dq ? |
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239 | ends |
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240 | rx_desc.buf_soft_addr = NUM_RX_DESC*sizeof.rx_desc |
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3545 | hidnplayr | 241 | |
5050 | hidnplayr | 242 | struct device ETH_DEVICE |
3545 | hidnplayr | 243 | |
5050 | hidnplayr | 244 | io_addr dd ? |
245 | pci_bus dd ? |
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246 | pci_dev dd ? |
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247 | irq_line db ? |
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248 | rb 3 ; align 4 |
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249 | mmio_addr dd ? ; memory map physical address |
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250 | chipset dd ? |
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251 | pcfg dd ? |
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252 | mcfg dd ? |
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253 | cur_rx dd ? ; Index into the Rx descriptor buffer of next Rx pkt |
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254 | cur_tx dd ? ; Index into the Tx descriptor buffer of next Rx pkt |
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255 | TxDescArrays dd ? ; Index of Tx Descriptor buffer |
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256 | RxDescArrays dd ? ; Index of Rx Descriptor buffer |
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257 | TxDescArray dd ? ; Index of 256-alignment Tx Descriptor buffer |
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258 | RxDescArray dd ? ; Index of 256-alignment Rx Descriptor buffer |
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3545 | hidnplayr | 259 | |
5050 | hidnplayr | 260 | rb 0x100-($ and 0xff) ; align 256 |
261 | tx_ring rb NUM_TX_DESC * sizeof.tx_desc * 2 |
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3545 | hidnplayr | 262 | |
5050 | hidnplayr | 263 | rb 0x100-($ and 0xff) ; align 256 |
264 | rx_ring rb NUM_RX_DESC * sizeof.rx_desc * 2 |
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3545 | hidnplayr | 265 | |
5050 | hidnplayr | 266 | ends |
3545 | hidnplayr | 267 | |
268 | intr_mask = ISB_LinkChg or ISB_RxOverflow or ISB_RxFIFOOver or ISB_TxErr or ISB_TxOK or ISB_RxErr or ISB_RxOK |
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269 | rx_config = (RX_FIFO_THRESH shl RXC_FIFOShift) or (RX_DMA_BURST shl RXC_DMAShift) or 0x0000000E |
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270 | |||
271 | |||
272 | macro udelay msec { |
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273 | |||
4803 | hidnplayr | 274 | push esi ecx |
3545 | hidnplayr | 275 | mov esi, msec |
5050 | hidnplayr | 276 | invoke Sleep |
4803 | hidnplayr | 277 | pop ecx esi |
3545 | hidnplayr | 278 | |
279 | } |
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280 | |||
281 | macro WRITE_GMII_REG RegAddr, value { |
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282 | |||
5050 | hidnplayr | 283 | set_io [ebx + device.io_addr], REG_PHYAR |
3545 | hidnplayr | 284 | if value eq ax |
285 | and eax, 0x0000ffff |
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286 | or eax, 0x80000000 + (RegAddr shl 16) |
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287 | else |
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288 | mov eax, 0x80000000 + (RegAddr shl 16) + value |
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289 | end if |
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290 | out dx, eax |
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291 | |||
292 | call PHY_WAIT_WRITE |
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293 | } |
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294 | |||
295 | macro READ_GMII_REG RegAddr { |
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296 | |||
297 | local .error, .done |
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298 | |||
5050 | hidnplayr | 299 | set_io [ebx + device.io_addr], REG_PHYAR |
3545 | hidnplayr | 300 | mov eax, RegAddr shl 16 |
301 | out dx, eax |
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302 | |||
303 | call PHY_WAIT_READ |
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304 | jz .error |
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305 | |||
306 | in eax, dx |
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307 | and eax, 0xFFFF |
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308 | jmp .done |
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309 | |||
310 | .error: |
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311 | or eax, -1 |
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312 | .done: |
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313 | } |
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314 | |||
315 | align 4 |
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316 | PHY_WAIT_READ: ; io addr must already be set to REG_PHYAR |
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317 | |||
318 | udelay 1 ;;;1000 |
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319 | |||
320 | push ecx |
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321 | mov ecx, 2000 |
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322 | ; Check if the RTL8169 has completed writing/reading to the specified MII register |
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323 | @@: |
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324 | in eax, dx |
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325 | test eax, 0x80000000 |
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326 | jnz .exit |
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327 | udelay 1 ;;;100 |
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328 | loop @b |
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329 | .exit: |
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330 | pop ecx |
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331 | ret |
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332 | |||
333 | align 4 |
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334 | PHY_WAIT_WRITE: ; io addr must already be set to REG_PHYAR |
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335 | |||
336 | udelay 1 ;;;1000 |
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337 | |||
338 | push ecx |
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339 | mov ecx, 2000 |
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340 | ; Check if the RTL8169 has completed writing/reading to the specified MII register |
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341 | @@: |
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342 | in eax, dx |
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343 | test eax, 0x80000000 |
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344 | jz .exit |
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345 | udelay 1 ;;;100 |
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346 | loop @b |
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347 | .exit: |
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348 | pop ecx |
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349 | ret |
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350 | |||
351 | |||
352 | |||
353 | ;;;;;;;;;;;;;;;;;;;;;;;;;;;; |
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354 | ;; ;; |
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355 | ;; proc START ;; |
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356 | ;; ;; |
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357 | ;; (standard driver proc) ;; |
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358 | ;;;;;;;;;;;;;;;;;;;;;;;;;;;; |
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359 | |||
5050 | hidnplayr | 360 | proc START c, reason:dword, cmdline:dword |
3545 | hidnplayr | 361 | |
5050 | hidnplayr | 362 | cmp [reason], DRV_ENTRY |
363 | jne .fail |
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3545 | hidnplayr | 364 | |
5050 | hidnplayr | 365 | DEBUGF 2,"Loading driver\n" |
366 | invoke RegService, my_service, service_proc |
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3545 | hidnplayr | 367 | ret |
368 | |||
369 | .fail: |
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5050 | hidnplayr | 370 | xor eax, eax |
3545 | hidnplayr | 371 | ret |
372 | |||
373 | endp |
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374 | |||
375 | |||
376 | ;;;;;;;;;;;;;;;;;;;;;;;;;;;; |
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377 | ;; ;; |
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378 | ;; proc SERVICE_PROC ;; |
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379 | ;; ;; |
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380 | ;; (standard driver proc) ;; |
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381 | ;;;;;;;;;;;;;;;;;;;;;;;;;;;; |
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382 | |||
383 | proc service_proc stdcall, ioctl:dword |
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384 | |||
385 | mov edx, [ioctl] |
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4470 | hidnplayr | 386 | mov eax, [edx + IOCTL.io_code] |
3545 | hidnplayr | 387 | |
388 | ;------------------------------------------------------ |
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389 | |||
390 | cmp eax, 0 ;SRV_GETVERSION |
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391 | jne @F |
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392 | |||
4470 | hidnplayr | 393 | cmp [edx + IOCTL.out_size], 4 |
3545 | hidnplayr | 394 | jb .fail |
4470 | hidnplayr | 395 | mov eax, [edx + IOCTL.output] |
3545 | hidnplayr | 396 | mov [eax], dword API_VERSION |
397 | |||
398 | xor eax, eax |
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399 | ret |
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400 | |||
401 | ;------------------------------------------------------ |
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402 | @@: |
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403 | cmp eax, 1 ;SRV_HOOK |
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404 | jne .fail |
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405 | |||
4470 | hidnplayr | 406 | cmp [edx + IOCTL.inp_size], 3 ; Data input must be at least 3 bytes |
3545 | hidnplayr | 407 | jb .fail |
408 | |||
4470 | hidnplayr | 409 | mov eax, [edx + IOCTL.input] |
3545 | hidnplayr | 410 | cmp byte [eax], 1 ; 1 means device number and bus number (pci) are given |
411 | jne .fail ; other types arent supported for this card yet |
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412 | |||
413 | ; check if the device is already listed |
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414 | |||
415 | mov esi, device_list |
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416 | mov ecx, [devices] |
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417 | test ecx, ecx |
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418 | jz .firstdevice |
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419 | |||
4470 | hidnplayr | 420 | ; mov eax, [edx + IOCTL.input] ; get the pci bus and device numbers |
421 | mov ax, [eax+1] ; |
||
3545 | hidnplayr | 422 | .nextdevice: |
423 | mov ebx, [esi] |
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5050 | hidnplayr | 424 | cmp al, byte[ebx + device.pci_bus] |
3545 | hidnplayr | 425 | jne @f |
5050 | hidnplayr | 426 | cmp ah, byte[ebx + device.pci_dev] |
3545 | hidnplayr | 427 | je .find_devicenum ; Device is already loaded, let's find it's device number |
428 | @@: |
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429 | add esi, 4 |
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430 | loop .nextdevice |
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431 | |||
432 | |||
433 | ; This device doesnt have its own eth_device structure yet, lets create one |
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434 | .firstdevice: |
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435 | cmp [devices], MAX_DEVICES ; First check if the driver can handle one more card |
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436 | jae .fail |
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437 | |||
5050 | hidnplayr | 438 | allocate_and_clear ebx, sizeof.device, .fail ; Allocate memory to put the device structure in |
3545 | hidnplayr | 439 | |
440 | ; Fill in the direct call addresses into the struct |
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441 | |||
5050 | hidnplayr | 442 | mov [ebx + device.reset], reset |
443 | mov [ebx + device.transmit], transmit |
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444 | mov [ebx + device.unload], unload |
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445 | mov [ebx + device.name], my_service |
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3545 | hidnplayr | 446 | |
447 | ; save the pci bus and device numbers |
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448 | |||
4470 | hidnplayr | 449 | mov eax, [edx + IOCTL.input] |
3545 | hidnplayr | 450 | movzx ecx, byte[eax+1] |
5050 | hidnplayr | 451 | mov [ebx + device.pci_bus], ecx |
3545 | hidnplayr | 452 | movzx ecx, byte[eax+2] |
5050 | hidnplayr | 453 | mov [ebx + device.pci_dev], ecx |
3545 | hidnplayr | 454 | |
455 | ; Now, it's time to find the base io addres of the PCI device |
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456 | |||
5050 | hidnplayr | 457 | stdcall PCI_find_io, [ebx + device.pci_bus], [ebx + device.pci_dev] |
458 | mov [ebx + device.io_addr], eax |
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3545 | hidnplayr | 459 | |
460 | ; We've found the io address, find IRQ now |
||
461 | |||
5050 | hidnplayr | 462 | invoke PciRead8, [ebx + device.pci_bus], [ebx + device.pci_dev], PCI_header00.interrupt_line |
463 | mov [ebx + device.irq_line], al |
||
3545 | hidnplayr | 464 | |
465 | DEBUGF 2,"Hooking into device, dev:%x, bus:%x, irq:%x, addr:%x\n",\ |
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5050 | hidnplayr | 466 | [ebx + device.pci_dev]:1,[ebx + device.pci_bus]:1,[ebx + device.irq_line]:1,[ebx + device.io_addr]:8 |
3545 | hidnplayr | 467 | |
468 | ; Ok, the eth_device structure is ready, let's probe the device |
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469 | ; Because initialization fires IRQ, IRQ handler must be aware of this device |
||
470 | mov eax, [devices] ; Add the device structure to our device list |
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471 | mov [device_list + 4*eax], ebx ; (IRQ handler uses this list to find device) |
||
472 | inc [devices] ; |
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473 | |||
474 | call probe ; this function will output in eax |
||
475 | test eax, eax |
||
476 | jnz .err2 ; If an error occured, exit |
||
477 | |||
5050 | hidnplayr | 478 | mov [ebx + device.type], NET_TYPE_ETH |
479 | invoke NetRegDev |
||
3545 | hidnplayr | 480 | |
481 | cmp eax, -1 |
||
482 | je .destroy |
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483 | |||
484 | ret |
||
485 | |||
486 | ; If the device was already loaded, find the device number and return it in eax |
||
487 | |||
488 | .find_devicenum: |
||
489 | DEBUGF 2,"Trying to find device number of already registered device\n" |
||
5050 | hidnplayr | 490 | invoke NetPtrToNum ; This kernel procedure converts a pointer to device struct in ebx |
3545 | hidnplayr | 491 | ; into a device number in edi |
492 | mov eax, edi ; Application wants it in eax instead |
||
493 | DEBUGF 2,"Kernel says: %u\n", eax |
||
494 | ret |
||
495 | |||
496 | ; If an error occured, remove all allocated data and exit (returning -1 in eax) |
||
497 | |||
498 | .destroy: |
||
499 | ; todo: reset device into virgin state |
||
500 | |||
501 | .err2: |
||
502 | dec [devices] |
||
503 | .err: |
||
504 | DEBUGF 2,"removing device structure\n" |
||
5050 | hidnplayr | 505 | invoke KernelFree, ebx |
3545 | hidnplayr | 506 | .fail: |
507 | or eax, -1 |
||
508 | ret |
||
509 | |||
510 | ;------------------------------------------------------ |
||
511 | endp |
||
512 | |||
513 | |||
514 | align 4 |
||
515 | unload: |
||
516 | |||
517 | ret |
||
518 | |||
519 | |||
520 | align 4 |
||
521 | init_board: |
||
522 | |||
523 | DEBUGF 1,"init_board\n" |
||
524 | |||
5050 | hidnplayr | 525 | ; Make the device a bus master |
526 | invoke PciRead32, [ebx + device.pci_bus], [ebx + device.pci_dev], PCI_header00.command |
||
527 | or al, PCI_CMD_MASTER |
||
528 | invoke PciWrite32, [ebx + device.pci_bus], [ebx + device.pci_dev], PCI_header00.command, eax |
||
3545 | hidnplayr | 529 | |
530 | ; Soft reset the chip |
||
5050 | hidnplayr | 531 | set_io [ebx + device.io_addr], 0 |
532 | set_io [ebx + device.io_addr], REG_ChipCmd |
||
3545 | hidnplayr | 533 | mov al, CMD_Reset |
534 | out dx, al |
||
535 | |||
536 | ; Check that the chip has finished the reset |
||
537 | mov ecx, 1000 |
||
5050 | hidnplayr | 538 | set_io [ebx + device.io_addr], REG_ChipCmd |
3545 | hidnplayr | 539 | @@: in al, dx |
540 | test al, CMD_Reset |
||
541 | jz @f |
||
542 | udelay 10 |
||
543 | loop @b |
||
544 | @@: |
||
545 | ; identify config method |
||
5050 | hidnplayr | 546 | set_io [ebx + device.io_addr], REG_TxConfig |
3545 | hidnplayr | 547 | in eax, dx |
548 | and eax, 0x7c800000 |
||
549 | DEBUGF 1,"init_board: TxConfig & 0x7c800000 = 0x%x\n", eax |
||
550 | mov esi, mac_info-8 |
||
551 | @@: add esi, 8 |
||
552 | mov ecx, eax |
||
553 | and ecx, [esi] |
||
554 | cmp ecx, [esi] |
||
555 | jne @b |
||
556 | mov eax, [esi+4] |
||
5050 | hidnplayr | 557 | mov [ebx + device.mcfg], eax |
3545 | hidnplayr | 558 | |
5050 | hidnplayr | 559 | mov [ebx + device.pcfg], PCFG_METHOD_3 |
3545 | hidnplayr | 560 | READ_GMII_REG 3 |
561 | and al, 0x0f |
||
562 | or al, al |
||
563 | jnz @f |
||
5050 | hidnplayr | 564 | mov [ebx + device.pcfg], PCFG_METHOD_1 |
3545 | hidnplayr | 565 | jmp .pconf |
566 | @@: dec al |
||
567 | jnz .pconf |
||
5050 | hidnplayr | 568 | mov [ebx + device.pcfg], PCFG_METHOD_2 |
3545 | hidnplayr | 569 | .pconf: |
570 | |||
571 | ; identify chip attached to board |
||
572 | mov ecx, 10 |
||
5050 | hidnplayr | 573 | mov eax, [ebx + device.mcfg] |
3545 | hidnplayr | 574 | @@: dec ecx |
575 | js @f |
||
576 | cmp eax, [rtl_chip_info + ecx*8] |
||
577 | jne @b |
||
5050 | hidnplayr | 578 | mov [ebx + device.chipset], ecx |
3545 | hidnplayr | 579 | jmp .match |
580 | @@: |
||
581 | ; if unknown chip, assume array element #0, original RTL-8169 in this case |
||
582 | DEBUGF 1,"init_board: PCI device: unknown chip version, assuming RTL-8169\n" |
||
5050 | hidnplayr | 583 | set_io [ebx + device.io_addr], REG_TxConfig |
3545 | hidnplayr | 584 | in eax, dx |
585 | DEBUGF 1,"init_board: PCI device: TxConfig = 0x%x\n", eax |
||
586 | |||
5050 | hidnplayr | 587 | mov [ebx + device.chipset], 0 |
3545 | hidnplayr | 588 | |
589 | xor eax, eax |
||
590 | inc eax |
||
591 | ret |
||
592 | |||
593 | .match: |
||
594 | DEBUGF 1,"init_board: chipset=%u\n", ecx |
||
595 | xor eax,eax |
||
596 | ret |
||
597 | |||
598 | |||
599 | |||
600 | ;*************************************************************************** |
||
601 | ; Function |
||
602 | ; probe |
||
603 | ; Description |
||
604 | ; Searches for an ethernet card, enables it and clears the rx buffer |
||
605 | ; If a card was found, it enables the ethernet -> TCPIP link |
||
606 | ; Destroyed registers |
||
607 | ; eax, ebx, ecx, edx |
||
608 | ; |
||
609 | ;*************************************************************************** |
||
610 | align 4 |
||
611 | probe: |
||
612 | |||
613 | DEBUGF 1,"probe\n" |
||
614 | |||
615 | call init_board |
||
616 | call read_mac |
||
617 | call PHY_config |
||
618 | |||
4334 | hidnplayr | 619 | DEBUGF 1,"Set MAC Reg C+CR Offset 0x82h = 0x01h\n" |
5050 | hidnplayr | 620 | set_io [ebx + device.io_addr], 0 |
621 | set_io [ebx + device.io_addr], 0x82 |
||
3545 | hidnplayr | 622 | mov al, 0x01 |
623 | out dx, al |
||
5050 | hidnplayr | 624 | cmp [ebx + device.mcfg], MCFG_METHOD_03 |
3545 | hidnplayr | 625 | jae @f |
4334 | hidnplayr | 626 | DEBUGF 1,"Set PCI Latency=0x40\n" |
5050 | hidnplayr | 627 | ; Adjust PCI latency to be at least 64 |
628 | invoke PciRead8, [ebx + device.pci_bus], [ebx + device.pci_dev], PCI_header00.max_latency |
||
629 | cmp al, 64 |
||
630 | jae @f |
||
631 | mov al, 64 |
||
632 | invoke PciWrite8, [ebx + device.pci_bus], [ebx + device.pci_dev], PCI_header00.max_latency, eax |
||
633 | @@: |
||
634 | cmp [ebx + device.mcfg], MCFG_METHOD_02 |
||
3545 | hidnplayr | 635 | jne @f |
4334 | hidnplayr | 636 | DEBUGF 1,"Set MAC Reg C+CR Offset 0x82h = 0x01h\n" |
5050 | hidnplayr | 637 | set_io [ebx + device.io_addr], 0 |
638 | set_io [ebx + device.io_addr], 0x82 |
||
3545 | hidnplayr | 639 | mov al, 0x01 |
640 | out dx, al |
||
4334 | hidnplayr | 641 | DEBUGF 1,"Set PHY Reg 0x0bh = 0x00h\n" |
3545 | hidnplayr | 642 | WRITE_GMII_REG 0x0b, 0x0000 ; w 0x0b 15 0 0 |
643 | @@: |
||
644 | ; if TBI is not enabled |
||
5050 | hidnplayr | 645 | set_io [ebx + device.io_addr], 0 |
646 | set_io [ebx + device.io_addr], REG_PHYstatus |
||
3545 | hidnplayr | 647 | in al, dx |
648 | test al, PHYS_TBI_Enable |
||
649 | jz .tbi_dis |
||
650 | READ_GMII_REG PHY_AUTO_NEGO_REG |
||
651 | |||
652 | ; enable 10/100 Full/Half Mode, leave PHY_AUTO_NEGO_REG bit4:0 unchanged |
||
653 | and eax, 0x0C1F |
||
654 | or eax, PHY_Cap_10_Half or PHY_Cap_10_Full or PHY_Cap_100_Half or PHY_Cap_100_Full |
||
655 | WRITE_GMII_REG PHY_AUTO_NEGO_REG, ax |
||
656 | |||
657 | ; enable 1000 Full Mode |
||
658 | WRITE_GMII_REG PHY_1000_CTRL_REG, PHY_Cap_1000_Full or PHY_Cap_1000_Half ; rtl8168 |
||
659 | |||
660 | ; Enable auto-negotiation and restart auto-nigotiation |
||
661 | WRITE_GMII_REG PHY_CTRL_REG, PHY_Enable_Auto_Nego or PHY_Restart_Auto_Nego |
||
662 | |||
4803 | hidnplayr | 663 | udelay 1 ; 100 |
664 | mov ecx, 200 ; 10000 |
||
665 | DEBUGF 1, "Waiting for auto-negotiation to complete\n" |
||
3545 | hidnplayr | 666 | ; wait for auto-negotiation process |
667 | @@: dec ecx |
||
668 | jz @f |
||
5050 | hidnplayr | 669 | set_io [ebx + device.io_addr], 0 |
3545 | hidnplayr | 670 | READ_GMII_REG PHY_STAT_REG |
4803 | hidnplayr | 671 | udelay 1 ; 100 |
3545 | hidnplayr | 672 | test eax, PHY_Auto_Neco_Comp |
673 | jz @b |
||
5050 | hidnplayr | 674 | set_io [ebx + device.io_addr], REG_PHYstatus |
3545 | hidnplayr | 675 | in al, dx |
676 | jmp @f |
||
677 | .tbi_dis: |
||
4803 | hidnplayr | 678 | udelay 1 ; 100 |
3545 | hidnplayr | 679 | @@: |
4803 | hidnplayr | 680 | DEBUGF 1, "auto-negotiation complete\n" |
3545 | hidnplayr | 681 | |
682 | ;*************************************************************************** |
||
683 | ; Function |
||
684 | ; rt8169_reset |
||
685 | ; Description |
||
686 | ; Place the chip (ie, the ethernet card) into a virgin state |
||
687 | ; Destroyed registers |
||
688 | ; eax, ebx, ecx, edx |
||
689 | ; |
||
690 | ;*************************************************************************** |
||
691 | align 4 |
||
692 | reset: |
||
693 | |||
4803 | hidnplayr | 694 | DEBUGF 1,"resetting\n" |
3545 | hidnplayr | 695 | |
5050 | hidnplayr | 696 | lea eax, [ebx + device.tx_ring] |
697 | mov [ebx + device.TxDescArrays], eax |
||
698 | mov [ebx + device.TxDescArray], eax |
||
3545 | hidnplayr | 699 | |
5050 | hidnplayr | 700 | lea eax, [ebx + device.rx_ring] |
701 | mov [ebx + device.RxDescArrays], eax |
||
702 | mov [ebx + device.RxDescArray], eax |
||
3545 | hidnplayr | 703 | |
704 | call init_ring |
||
705 | call hw_start |
||
706 | |||
707 | ; clear packet/byte counters |
||
708 | |||
709 | xor eax, eax |
||
5050 | hidnplayr | 710 | lea edi, [ebx + device.bytes_tx] |
3545 | hidnplayr | 711 | mov ecx, 6 |
712 | rep stosd |
||
713 | |||
5050 | hidnplayr | 714 | mov [ebx + device.mtu], 1500 |
3545 | hidnplayr | 715 | |
716 | ; Set link state to unknown |
||
5050 | hidnplayr | 717 | mov [ebx + device.state], ETH_LINK_UNKNOWN |
3545 | hidnplayr | 718 | |
4803 | hidnplayr | 719 | DEBUGF 2,"init OK!\n" |
3545 | hidnplayr | 720 | xor eax, eax |
721 | ret |
||
722 | |||
723 | |||
724 | |||
725 | |||
726 | |||
727 | align 4 |
||
728 | PHY_config: |
||
729 | |||
5050 | hidnplayr | 730 | DEBUGF 1,"hw_PHY_config: priv.mcfg=%d, priv.pcfg=%d\n", [ebx + device.mcfg], [ebx + device.pcfg] |
3545 | hidnplayr | 731 | |
5050 | hidnplayr | 732 | cmp [ebx + device.mcfg], MCFG_METHOD_04 |
3545 | hidnplayr | 733 | jne .not_4 |
5050 | hidnplayr | 734 | set_io [ebx + device.io_addr], 0 |
3545 | hidnplayr | 735 | ; WRITE_GMII_REG 0x1F, 0x0001 |
736 | ; WRITE_GMII_REG 0x1b, 0x841e |
||
737 | ; WRITE_GMII_REG 0x0e, 0x7bfb |
||
738 | ; WRITE_GMII_REG 0x09, 0x273a |
||
739 | WRITE_GMII_REG 0x1F, 0x0002 |
||
740 | WRITE_GMII_REG 0x01, 0x90D0 |
||
741 | WRITE_GMII_REG 0x1F, 0x0000 |
||
742 | jmp .exit |
||
743 | .not_4: |
||
5050 | hidnplayr | 744 | cmp [ebx + device.mcfg], MCFG_METHOD_02 |
3545 | hidnplayr | 745 | je @f |
5050 | hidnplayr | 746 | cmp [ebx + device.mcfg], MCFG_METHOD_03 |
3545 | hidnplayr | 747 | jne .not_2_or_3 |
748 | @@: |
||
5050 | hidnplayr | 749 | set_io [ebx + device.io_addr], 0 |
3545 | hidnplayr | 750 | WRITE_GMII_REG 0x1F, 0x0001 |
751 | WRITE_GMII_REG 0x15, 0x1000 |
||
752 | WRITE_GMII_REG 0x18, 0x65C7 |
||
753 | WRITE_GMII_REG 0x04, 0x0000 |
||
754 | WRITE_GMII_REG 0x03, 0x00A1 |
||
755 | WRITE_GMII_REG 0x02, 0x0008 |
||
756 | WRITE_GMII_REG 0x01, 0x1020 |
||
757 | WRITE_GMII_REG 0x00, 0x1000 |
||
758 | WRITE_GMII_REG 0x04, 0x0800 |
||
759 | WRITE_GMII_REG 0x04, 0x0000 |
||
760 | WRITE_GMII_REG 0x04, 0x7000 |
||
761 | WRITE_GMII_REG 0x03, 0xFF41 |
||
762 | WRITE_GMII_REG 0x02, 0xDE60 |
||
763 | WRITE_GMII_REG 0x01, 0x0140 |
||
764 | WRITE_GMII_REG 0x00, 0x0077 |
||
765 | WRITE_GMII_REG 0x04, 0x7800 |
||
766 | WRITE_GMII_REG 0x04, 0x7000 |
||
767 | WRITE_GMII_REG 0x04, 0xA000 |
||
768 | WRITE_GMII_REG 0x03, 0xDF01 |
||
769 | WRITE_GMII_REG 0x02, 0xDF20 |
||
770 | WRITE_GMII_REG 0x01, 0xFF95 |
||
771 | WRITE_GMII_REG 0x00, 0xFA00 |
||
772 | WRITE_GMII_REG 0x04, 0xA800 |
||
773 | WRITE_GMII_REG 0x04, 0xA000 |
||
774 | WRITE_GMII_REG 0x04, 0xB000 |
||
775 | WRITE_GMII_REG 0x03, 0xFF41 |
||
776 | WRITE_GMII_REG 0x02, 0xDE20 |
||
777 | WRITE_GMII_REG 0x01, 0x0140 |
||
778 | WRITE_GMII_REG 0x00, 0x00BB |
||
779 | WRITE_GMII_REG 0x04, 0xB800 |
||
780 | WRITE_GMII_REG 0x04, 0xB000 |
||
781 | WRITE_GMII_REG 0x04, 0xF000 |
||
782 | WRITE_GMII_REG 0x03, 0xDF01 |
||
783 | WRITE_GMII_REG 0x02, 0xDF20 |
||
784 | WRITE_GMII_REG 0x01, 0xFF95 |
||
785 | WRITE_GMII_REG 0x00, 0xBF00 |
||
786 | WRITE_GMII_REG 0x04, 0xF800 |
||
787 | WRITE_GMII_REG 0x04, 0xF000 |
||
788 | WRITE_GMII_REG 0x04, 0x0000 |
||
789 | WRITE_GMII_REG 0x1F, 0x0000 |
||
790 | WRITE_GMII_REG 0x0B, 0x0000 |
||
791 | jmp .exit |
||
792 | .not_2_or_3: |
||
5050 | hidnplayr | 793 | DEBUGF 1,"mcfg=%d, discard hw PHY config\n", [ebx + device.mcfg] |
3545 | hidnplayr | 794 | .exit: |
795 | ret |
||
796 | |||
797 | |||
798 | |||
799 | align 4 |
||
800 | set_rx_mode: |
||
801 | |||
802 | DEBUGF 1,"set_rx_mode\n" |
||
803 | |||
804 | ; IFF_ALLMULTI |
||
805 | ; Too many to filter perfectly -- accept all multicasts |
||
5050 | hidnplayr | 806 | set_io [ebx + device.io_addr], 0 |
807 | set_io [ebx + device.io_addr], REG_RxConfig |
||
3545 | hidnplayr | 808 | in eax, dx |
5050 | hidnplayr | 809 | mov ecx, [ebx + device.chipset] |
3545 | hidnplayr | 810 | and eax, [rtl_chip_info + ecx * 8 + 4] ; RxConfigMask |
811 | or eax, rx_config or (RXM_AcceptBroadcast or RXM_AcceptMulticast or RXM_AcceptMyPhys) |
||
812 | out dx, eax |
||
813 | |||
814 | ; Multicast hash filter |
||
5050 | hidnplayr | 815 | set_io [ebx + device.io_addr], REG_MAR0 + 0 |
3545 | hidnplayr | 816 | or eax, -1 |
817 | out dx, eax |
||
5050 | hidnplayr | 818 | set_io [ebx + device.io_addr], REG_MAR0 + 4 |
3545 | hidnplayr | 819 | out dx, eax |
820 | |||
821 | ret |
||
822 | |||
823 | |||
824 | align 4 |
||
825 | init_ring: |
||
826 | |||
827 | DEBUGF 1,"init_ring\n" |
||
828 | |||
829 | xor eax, eax |
||
5050 | hidnplayr | 830 | mov [ebx + device.cur_rx], eax |
831 | mov [ebx + device.cur_tx], eax |
||
3545 | hidnplayr | 832 | |
5050 | hidnplayr | 833 | lea edi, [ebx + device.tx_ring] |
834 | mov ecx, (NUM_TX_DESC * sizeof.tx_desc) / 4 |
||
3545 | hidnplayr | 835 | rep stosd |
836 | |||
5050 | hidnplayr | 837 | lea edi, [ebx + device.rx_ring] |
838 | mov ecx, (NUM_RX_DESC * sizeof.rx_desc) / 4 |
||
3545 | hidnplayr | 839 | rep stosd |
840 | |||
5050 | hidnplayr | 841 | mov edi, [ebx + device.RxDescArray] |
3545 | hidnplayr | 842 | mov ecx, NUM_RX_DESC |
843 | .loop: |
||
844 | push ecx |
||
5050 | hidnplayr | 845 | invoke KernelAlloc, RX_BUF_SIZE |
846 | mov dword [edi + rx_desc.buf_soft_addr], eax |
||
847 | invoke GetPgAddr |
||
3545 | hidnplayr | 848 | mov dword [edi + rx_desc.buf_addr], eax |
849 | mov [edi + rx_desc.status], DSB_OWNbit or RX_BUF_SIZE |
||
5050 | hidnplayr | 850 | add edi, sizeof.rx_desc |
3545 | hidnplayr | 851 | pop ecx |
5050 | hidnplayr | 852 | dec ecx |
853 | jnz .loop |
||
854 | or [edi - sizeof.rx_desc + rx_desc.status], DSB_EORbit |
||
3545 | hidnplayr | 855 | |
856 | ret |
||
857 | |||
858 | |||
859 | align 4 |
||
860 | hw_start: |
||
861 | |||
862 | DEBUGF 1,"hw_start\n" |
||
863 | |||
864 | ; attach int handler |
||
5050 | hidnplayr | 865 | movzx eax, [ebx + device.irq_line] |
3545 | hidnplayr | 866 | DEBUGF 1,"Attaching int handler to irq %x\n", eax:1 |
5050 | hidnplayr | 867 | invoke AttachIntHandler, eax, int_handler, ebx |
868 | test eax, eax |
||
869 | jnz @f |
||
870 | DEBUGF 2,"Could not attach int handler!\n" |
||
871 | or eax, -1 |
||
872 | ret |
||
873 | @@: |
||
3545 | hidnplayr | 874 | |
875 | ; Soft reset the chip |
||
5050 | hidnplayr | 876 | set_io [ebx + device.io_addr], 0 |
877 | set_io [ebx + device.io_addr], REG_ChipCmd |
||
3545 | hidnplayr | 878 | mov al, CMD_Reset |
879 | out dx, al |
||
880 | |||
881 | DEBUGF 1,"Waiting for chip to reset... " |
||
882 | ; Check that the chip has finished the reset |
||
883 | mov ecx, 1000 |
||
5050 | hidnplayr | 884 | set_io [ebx + device.io_addr], REG_ChipCmd |
3545 | hidnplayr | 885 | @@: in al, dx |
886 | test al, CMD_Reset |
||
887 | jz @f |
||
888 | udelay 10 |
||
889 | loop @b |
||
890 | @@: |
||
891 | DEBUGF 1,"done!\n" |
||
892 | |||
5050 | hidnplayr | 893 | set_io [ebx + device.io_addr], REG_Cfg9346 |
3545 | hidnplayr | 894 | mov al, CFG_9346_Unlock |
895 | out dx, al |
||
896 | |||
5050 | hidnplayr | 897 | set_io [ebx + device.io_addr], REG_ChipCmd |
3545 | hidnplayr | 898 | mov al, CMD_TxEnb or CMD_RxEnb |
899 | out dx, al |
||
900 | |||
5050 | hidnplayr | 901 | set_io [ebx + device.io_addr], REG_ETThReg |
3545 | hidnplayr | 902 | mov al, ETTh |
903 | out dx, al |
||
904 | |||
905 | ; For gigabit rtl8169 |
||
5050 | hidnplayr | 906 | set_io [ebx + device.io_addr], REG_RxMaxSize |
3545 | hidnplayr | 907 | mov ax, RxPacketMaxSize |
908 | out dx, ax |
||
909 | |||
910 | ; Set Rx Config register |
||
5050 | hidnplayr | 911 | set_io [ebx + device.io_addr], REG_RxConfig |
3545 | hidnplayr | 912 | in ax, dx |
5050 | hidnplayr | 913 | mov ecx, [ebx + device.chipset] |
3545 | hidnplayr | 914 | and eax, [rtl_chip_info + ecx * 8 + 4] ; RxConfigMask |
915 | or eax, rx_config |
||
916 | out dx, eax |
||
917 | |||
918 | ; Set DMA burst size and Interframe Gap Time |
||
5050 | hidnplayr | 919 | set_io [ebx + device.io_addr], REG_TxConfig |
3545 | hidnplayr | 920 | mov eax, (TX_DMA_BURST shl TXC_DMAShift) or (InterFrameGap shl TXC_InterFrameGapShift) |
921 | out dx, eax |
||
922 | |||
5050 | hidnplayr | 923 | set_io [ebx + device.io_addr], REG_CPlusCmd |
3545 | hidnplayr | 924 | in ax, dx |
925 | out dx, ax |
||
926 | |||
927 | in ax, dx |
||
928 | or ax, 1 shl 3 |
||
5050 | hidnplayr | 929 | cmp [ebx + device.mcfg], MCFG_METHOD_02 |
3545 | hidnplayr | 930 | jne @f |
5050 | hidnplayr | 931 | cmp [ebx + device.mcfg], MCFG_METHOD_03 |
3545 | hidnplayr | 932 | jne @f |
933 | or ax,1 shl 14 |
||
934 | DEBUGF 1,"Set MAC Reg C+CR Offset 0xE0: bit-3 and bit-14\n" |
||
935 | jmp .set |
||
936 | @@: |
||
937 | DEBUGF 1,"Set MAC Reg C+CR Offset 0xE0: bit-3\n" |
||
938 | .set: |
||
5050 | hidnplayr | 939 | set_io [ebx + device.io_addr], REG_CPlusCmd |
3545 | hidnplayr | 940 | out dx, ax |
941 | |||
5050 | hidnplayr | 942 | set_io [ebx + device.io_addr], 0xE2 |
3545 | hidnplayr | 943 | ; mov ax, 0x1517 |
944 | ; out dx, ax |
||
945 | ; mov ax, 0x152a |
||
946 | ; out dx, ax |
||
947 | ; mov ax, 0x282a |
||
948 | ; out dx, ax |
||
949 | xor ax, ax |
||
950 | out dx, ax |
||
951 | |||
952 | xor eax, eax |
||
5050 | hidnplayr | 953 | mov [ebx + device.cur_rx], eax |
954 | lea eax, [ebx + device.tx_ring] |
||
955 | invoke GetPhysAddr |
||
956 | set_io [ebx + device.io_addr], REG_TxDescStartAddr |
||
3545 | hidnplayr | 957 | out dx, eax |
5050 | hidnplayr | 958 | set_io [ebx + device.io_addr], REG_TxDescStartAddr + 4 |
4301 | clevermous | 959 | xor eax, eax |
960 | out dx, eax |
||
3545 | hidnplayr | 961 | |
5050 | hidnplayr | 962 | lea eax, [ebx + device.rx_ring] |
963 | invoke GetPhysAddr |
||
964 | set_io [ebx + device.io_addr], REG_RxDescStartAddr |
||
3545 | hidnplayr | 965 | out dx, eax |
4301 | clevermous | 966 | xor eax, eax |
5050 | hidnplayr | 967 | set_io [ebx + device.io_addr], REG_RxDescStartAddr + 4 |
4301 | clevermous | 968 | out dx, eax |
3545 | hidnplayr | 969 | |
5050 | hidnplayr | 970 | set_io [ebx + device.io_addr], REG_Cfg9346 |
3545 | hidnplayr | 971 | mov al, CFG_9346_Lock |
972 | out dx, al |
||
973 | |||
974 | udelay 10 |
||
975 | |||
976 | xor eax, eax |
||
5050 | hidnplayr | 977 | set_io [ebx + device.io_addr], REG_RxMissed |
3545 | hidnplayr | 978 | out dx, eax |
979 | |||
980 | call set_rx_mode |
||
981 | |||
5050 | hidnplayr | 982 | set_io [ebx + device.io_addr], 0 |
3545 | hidnplayr | 983 | ; no early-rx interrupts |
5050 | hidnplayr | 984 | set_io [ebx + device.io_addr], REG_MultiIntr |
3545 | hidnplayr | 985 | in ax, dx |
986 | and ax, 0xF000 |
||
987 | out dx, ax |
||
988 | |||
989 | ; set interrupt mask |
||
5050 | hidnplayr | 990 | set_io [ebx + device.io_addr], REG_IntrMask |
3545 | hidnplayr | 991 | mov ax, intr_mask |
992 | out dx, ax |
||
993 | |||
994 | xor eax, eax |
||
995 | ret |
||
996 | |||
997 | |||
998 | align 4 |
||
999 | read_mac: |
||
1000 | |||
5050 | hidnplayr | 1001 | set_io [ebx + device.io_addr], 0 |
1002 | set_io [ebx + device.io_addr], REG_MAC0 |
||
3545 | hidnplayr | 1003 | xor ecx, ecx |
5050 | hidnplayr | 1004 | lea edi, [ebx + device.mac] |
3545 | hidnplayr | 1005 | mov ecx, 6 |
1006 | |||
1007 | ; Get MAC address. FIXME: read EEPROM |
||
1008 | @@: in al, dx |
||
1009 | stosb |
||
1010 | inc edx |
||
1011 | loop @r |
||
1012 | |||
1013 | DEBUGF 1,"MAC = %x-%x-%x-%x-%x-%x\n",\ |
||
5050 | hidnplayr | 1014 | [ebx + device.mac+0]:2,[ebx + device.mac+1]:2,[ebx + device.mac+2]:2,[ebx + device.mac+3]:2,[ebx + device.mac+4]:2,[ebx + device.mac+5]:2 |
3545 | hidnplayr | 1015 | |
1016 | ret |
||
1017 | |||
1018 | align 4 |
||
1019 | write_mac: |
||
1020 | |||
1021 | ret 6 |
||
1022 | |||
1023 | |||
1024 | ;*************************************************************************** |
||
1025 | ; Function |
||
1026 | ; transmit |
||
1027 | ; Description |
||
1028 | ; Transmits a packet of data via the ethernet card |
||
1029 | ; |
||
1030 | ; Destroyed registers |
||
1031 | ; eax, edx, esi, edi |
||
1032 | ; |
||
1033 | ;*************************************************************************** |
||
1034 | |||
5050 | hidnplayr | 1035 | proc transmit stdcall bufferptr, buffersize |
1036 | |||
1037 | pushf |
||
1038 | cli |
||
1039 | |||
1040 | DEBUGF 1,"Transmitting packet, buffer:%x, size:%u\n", [bufferptr], [buffersize] |
||
1041 | mov eax, [bufferptr] |
||
3545 | hidnplayr | 1042 | DEBUGF 1,"To: %x-%x-%x-%x-%x-%x From: %x-%x-%x-%x-%x-%x Type:%x%x\n",\ |
1043 | [eax+00]:2,[eax+01]:2,[eax+02]:2,[eax+03]:2,[eax+04]:2,[eax+05]:2,\ |
||
1044 | [eax+06]:2,[eax+07]:2,[eax+08]:2,[eax+09]:2,[eax+10]:2,[eax+11]:2,\ |
||
1045 | [eax+13]:2,[eax+12]:2 |
||
1046 | |||
5050 | hidnplayr | 1047 | cmp [buffersize], 1514 |
3545 | hidnplayr | 1048 | ja .fail |
5050 | hidnplayr | 1049 | cmp [buffersize], 60 |
1050 | jb .fail |
||
3545 | hidnplayr | 1051 | |
1052 | ;---------------------------------- |
||
1053 | ; Find currentTX descriptor address |
||
1054 | |||
5050 | hidnplayr | 1055 | mov eax, sizeof.tx_desc |
1056 | mul [ebx + device.cur_tx] |
||
1057 | lea esi, [ebx + device.tx_ring + eax] |
||
3545 | hidnplayr | 1058 | |
1059 | DEBUGF 1,"Using TX desc: %x\n", esi |
||
1060 | |||
1061 | ;--------------------------- |
||
1062 | ; Program the packet pointer |
||
1063 | |||
5050 | hidnplayr | 1064 | mov eax, [bufferptr] |
3545 | hidnplayr | 1065 | mov [esi + tx_desc.buf_soft_addr], eax |
5050 | hidnplayr | 1066 | invoke GetPhysAddr |
3545 | hidnplayr | 1067 | mov dword [esi + tx_desc.buf_addr], eax |
1068 | |||
1069 | ;------------------------ |
||
1070 | ; Program the packet size |
||
1071 | |||
5050 | hidnplayr | 1072 | mov eax, [buffersize] |
3545 | hidnplayr | 1073 | @@: or eax, DSB_OWNbit or DSB_FSbit or DSB_LSbit |
5050 | hidnplayr | 1074 | cmp [ebx + device.cur_tx], NUM_TX_DESC - 1 |
3545 | hidnplayr | 1075 | jne @f |
1076 | or eax, DSB_EORbit |
||
1077 | @@: mov [esi + tx_desc.status], eax |
||
1078 | |||
1079 | ;----------------------------------------- |
||
1080 | ; Set the polling bit (start transmission) |
||
1081 | |||
5050 | hidnplayr | 1082 | set_io [ebx + device.io_addr], 0 |
1083 | set_io [ebx + device.io_addr], REG_TxPoll |
||
3545 | hidnplayr | 1084 | mov al, 0x40 ; set polling bit |
1085 | out dx, al |
||
1086 | |||
1087 | ;----------------------- |
||
1088 | ; Update TX descriptor |
||
1089 | |||
5050 | hidnplayr | 1090 | inc [ebx + device.cur_tx] |
1091 | and [ebx + device.cur_tx], NUM_TX_DESC - 1 |
||
3545 | hidnplayr | 1092 | |
1093 | ;------------- |
||
1094 | ; Update stats |
||
1095 | |||
5050 | hidnplayr | 1096 | inc [ebx + device.packets_tx] |
1097 | mov eax, [buffersize] |
||
1098 | add dword [ebx + device.bytes_tx], eax |
||
1099 | adc dword [ebx + device.bytes_tx + 4], 0 |
||
3545 | hidnplayr | 1100 | |
1101 | xor eax, eax |
||
5050 | hidnplayr | 1102 | popf |
1103 | ret |
||
3545 | hidnplayr | 1104 | |
1105 | .fail: |
||
5050 | hidnplayr | 1106 | DEBUGF 2,"Transmit failed\n" |
1107 | invoke KernelFree, [bufferptr] |
||
1108 | popf |
||
3545 | hidnplayr | 1109 | or eax, -1 |
5050 | hidnplayr | 1110 | ret |
3545 | hidnplayr | 1111 | |
5050 | hidnplayr | 1112 | endp |
3545 | hidnplayr | 1113 | |
5050 | hidnplayr | 1114 | |
3545 | hidnplayr | 1115 | ;;;DSB_OWNbit |
1116 | |||
1117 | |||
1118 | ;;;;;;;;;;;;;;;;;;;;;;; |
||
1119 | ;; ;; |
||
1120 | ;; Interrupt handler ;; |
||
1121 | ;; ;; |
||
1122 | ;;;;;;;;;;;;;;;;;;;;;;; |
||
1123 | |||
1124 | align 4 |
||
1125 | int_handler: |
||
1126 | |||
1127 | push ebx esi edi |
||
1128 | |||
4334 | hidnplayr | 1129 | DEBUGF 1,"INT\n" |
3545 | hidnplayr | 1130 | |
1131 | ; find pointer of device wich made IRQ occur |
||
1132 | |||
1133 | mov ecx, [devices] |
||
1134 | test ecx, ecx |
||
1135 | jz .nothing |
||
1136 | mov esi, device_list |
||
1137 | .nextdevice: |
||
1138 | mov ebx, [esi] |
||
1139 | |||
5050 | hidnplayr | 1140 | set_io [ebx + device.io_addr], 0 |
1141 | set_io [ebx + device.io_addr], REG_IntrStatus |
||
3545 | hidnplayr | 1142 | in ax, dx |
1143 | test ax, ax |
||
1144 | jnz .got_it |
||
1145 | .continue: |
||
1146 | add esi, 4 |
||
1147 | dec ecx |
||
1148 | jnz .nextdevice |
||
1149 | .nothing: |
||
1150 | pop edi esi ebx |
||
1151 | xor eax, eax |
||
1152 | |||
1153 | ret ; If no device was found, abort (The irq was probably for a device, not registered to this driver) |
||
1154 | |||
1155 | .got_it: |
||
1156 | |||
5050 | hidnplayr | 1157 | DEBUGF 1,"Device: %x Status: %x\n", ebx, ax |
3545 | hidnplayr | 1158 | |
1159 | cmp ax, 0xFFFF ; if so, hardware is no longer present |
||
1160 | je .fail |
||
1161 | |||
1162 | ;-------- |
||
1163 | ; Receive |
||
1164 | |||
1165 | test ax, ISB_RxOK |
||
1166 | jz .no_rx |
||
1167 | |||
1168 | push ax |
||
1169 | push ebx |
||
1170 | |||
1171 | .check_more: |
||
1172 | pop ebx |
||
5050 | hidnplayr | 1173 | mov eax, sizeof.rx_desc |
1174 | mul [ebx + device.cur_rx] |
||
1175 | lea esi, [ebx + device.rx_ring + eax] |
||
3545 | hidnplayr | 1176 | |
1177 | DEBUGF 1,"RxDesc.status = 0x%x\n", [esi + rx_desc.status] |
||
1178 | mov eax, [esi + rx_desc.status] |
||
1179 | test eax, DSB_OWNbit ;;; |
||
1180 | jnz .rx_return |
||
1181 | |||
5050 | hidnplayr | 1182 | DEBUGF 1,"cur_rx = %u\n", [ebx + device.cur_rx] |
3545 | hidnplayr | 1183 | |
1184 | test eax, SD_RxRES |
||
1185 | jnz .rx_return ;;;;; RX error! |
||
1186 | |||
1187 | push ebx |
||
1188 | push .check_more |
||
1189 | and eax, 0x00001FFF |
||
1190 | add eax, -4 ; we dont need CRC |
||
1191 | push eax |
||
1192 | DEBUGF 1,"data length = %u\n", ax |
||
1193 | |||
1194 | ;------------- |
||
1195 | ; Update stats |
||
1196 | |||
5050 | hidnplayr | 1197 | add dword [ebx + device.bytes_rx], eax |
1198 | adc dword [ebx + device.bytes_rx + 4], 0 |
||
1199 | inc [ebx + device.packets_rx] |
||
3545 | hidnplayr | 1200 | |
5050 | hidnplayr | 1201 | pushd [esi + rx_desc.buf_soft_addr] |
3545 | hidnplayr | 1202 | |
1203 | ;---------------------- |
||
1204 | ; Allocate a new buffer |
||
1205 | |||
5050 | hidnplayr | 1206 | invoke KernelAlloc, RX_BUF_SIZE |
3545 | hidnplayr | 1207 | mov [esi + rx_desc.buf_soft_addr], eax |
5050 | hidnplayr | 1208 | invoke GetPhysAddr |
3545 | hidnplayr | 1209 | mov dword [esi + rx_desc.buf_addr], eax |
1210 | |||
1211 | ;--------------- |
||
1212 | ; re set OWN bit |
||
1213 | |||
1214 | mov eax, DSB_OWNbit or RX_BUF_SIZE |
||
5050 | hidnplayr | 1215 | cmp [ebx + device.cur_rx], NUM_RX_DESC - 1 |
3545 | hidnplayr | 1216 | jne @f |
1217 | or eax, DSB_EORbit |
||
5050 | hidnplayr | 1218 | @@: |
1219 | mov [esi + rx_desc.status], eax |
||
3545 | hidnplayr | 1220 | |
1221 | ;-------------- |
||
1222 | ; Update rx ptr |
||
1223 | |||
5050 | hidnplayr | 1224 | inc [ebx + device.cur_rx] |
1225 | and [ebx + device.cur_rx], NUM_RX_DESC - 1 |
||
3545 | hidnplayr | 1226 | |
5050 | hidnplayr | 1227 | jmp [Eth_input] |
3545 | hidnplayr | 1228 | .rx_return: |
1229 | |||
1230 | pop ax |
||
1231 | .no_rx: |
||
1232 | |||
1233 | ;--------- |
||
1234 | ; Transmit |
||
1235 | |||
1236 | test ax, ISB_TxOK |
||
1237 | jz .no_tx |
||
1238 | push ax |
||
1239 | |||
1240 | DEBUGF 1,"TX ok!\n" |
||
1241 | |||
1242 | mov ecx, NUM_TX_DESC |
||
5050 | hidnplayr | 1243 | lea esi, [ebx + device.tx_ring] |
3545 | hidnplayr | 1244 | .txloop: |
5050 | hidnplayr | 1245 | cmp dword [esi + tx_desc.buf_soft_addr], 0 |
3545 | hidnplayr | 1246 | jz .maybenext |
1247 | |||
1248 | test [esi + tx_desc.status], DSB_OWNbit |
||
1249 | jnz .maybenext |
||
1250 | |||
1251 | push ecx |
||
1252 | DEBUGF 1,"Freeing up TX desc: %x\n", esi |
||
5050 | hidnplayr | 1253 | invoke KernelFree, [esi + tx_desc.buf_soft_addr] |
3545 | hidnplayr | 1254 | pop ecx |
5050 | hidnplayr | 1255 | and dword [esi + tx_desc.buf_soft_addr], 0 |
3545 | hidnplayr | 1256 | |
1257 | .maybenext: |
||
5050 | hidnplayr | 1258 | add esi, sizeof.tx_desc |
3545 | hidnplayr | 1259 | dec ecx |
1260 | jnz .txloop |
||
1261 | |||
1262 | pop ax |
||
1263 | .no_tx: |
||
1264 | |||
1265 | ;------- |
||
1266 | ; Finish |
||
1267 | |||
5050 | hidnplayr | 1268 | set_io [ebx + device.io_addr], 0 |
1269 | set_io [ebx + device.io_addr], REG_IntrStatus |
||
3545 | hidnplayr | 1270 | out dx, ax ; ACK all interrupts |
1271 | |||
1272 | .fail: |
||
1273 | pop edi esi ebx |
||
1274 | xor eax, eax |
||
1275 | inc eax |
||
1276 | |||
1277 | ret |
||
1278 | |||
1279 | |||
1280 | |||
5050 | hidnplayr | 1281 | ; End of code |
3545 | hidnplayr | 1282 | |
5050 | hidnplayr | 1283 | data fixups |
1284 | end data |
||
3545 | hidnplayr | 1285 | |
5050 | hidnplayr | 1286 | include '../peimport.inc' |
3545 | hidnplayr | 1287 | |
1288 | my_service db 'RTL8169',0 ; max 16 chars include zero |
||
1289 | |||
1290 | include_debug_strings ; All data wich FDO uses will be included here |
||
1291 | |||
1292 | rtl_chip_info dd \ |
||
1293 | MCFG_METHOD_01, 0xff7e1880, \ ; RTL8169 |
||
1294 | MCFG_METHOD_02, 0xff7e1880, \ ; RTL8169s/8110s |
||
1295 | MCFG_METHOD_03, 0xff7e1880, \ ; RTL8169s/8110s |
||
1296 | MCFG_METHOD_04, 0xff7e1880, \ ; RTL8169sb/8110sb |
||
1297 | MCFG_METHOD_05, 0xff7e1880, \ ; RTL8169sc/8110sc |
||
1298 | MCFG_METHOD_11, 0xff7e1880, \ ; RTL8168b/8111b // PCI-E |
||
1299 | MCFG_METHOD_12, 0xff7e1880, \ ; RTL8168b/8111b // PCI-E |
||
1300 | MCFG_METHOD_13, 0xff7e1880, \ ; RTL8101e // PCI-E 8139 |
||
1301 | MCFG_METHOD_14, 0xff7e1880, \ ; RTL8100e // PCI-E 8139 |
||
1302 | MCFG_METHOD_15, 0xff7e1880 ; RTL8100e // PCI-E 8139 |
||
1303 | |||
1304 | mac_info dd \ |
||
1305 | 0x38800000, MCFG_METHOD_15, \ |
||
1306 | 0x38000000, MCFG_METHOD_12, \ |
||
1307 | 0x34000000, MCFG_METHOD_13, \ |
||
1308 | 0x30800000, MCFG_METHOD_14, \ |
||
1309 | 0x30000000, MCFG_METHOD_11, \ |
||
1310 | 0x18000000, MCFG_METHOD_05, \ |
||
1311 | 0x10000000, MCFG_METHOD_04, \ |
||
1312 | 0x04000000, MCFG_METHOD_03, \ |
||
1313 | 0x00800000, MCFG_METHOD_02, \ |
||
1314 | 0x00000000, MCFG_METHOD_01 ; catch-all |
||
1315 | |||
1316 | name_01 db "RTL8169", 0 |
||
1317 | name_02_03 db "RTL8169s/8110s", 0 |
||
1318 | name_04 db "RTL8169sb/8110sb", 0 |
||
1319 | name_05 db "RTL8169sc/8110sc", 0 |
||
1320 | name_11_12 db "RTL8168b/8111b", 0 ; PCI-E |
||
1321 | name_13 db "RTL8101e", 0 ; PCI-E 8139 |
||
1322 | name_14_15 db "RTL8100e", 0 ; PCI-E 8139 |
||
1323 | |||
5050 | hidnplayr | 1324 | align 4 |
1325 | devices dd 0 |
||
3545 | hidnplayr | 1326 | device_list rd MAX_DEVICES ; This list contains all pointers to device structures the driver is handling |
1327 |