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#include 

#include 

#include 

#include 

#include 

#define CARDBUS_RESERVE_BUSNR   3

{

    return 0;

};

 * Translate the low bits of the PCI base

 * to the resource type

 */

static inline unsigned int pci_calc_resource_flags(unsigned int flags)

{

    if (flags & PCI_BASE_ADDRESS_SPACE_IO)

        return IORESOURCE_IO;

        return IORESOURCE_MEM | IORESOURCE_PREFETCH;

}

{

    u64 size = mask & maxbase;  /* Find the significant bits */

    if (!size)

        return 0;

       from that the extent.  */

    size = (size & ~(size-1)) - 1;

       already been programmed with all 1s.  */

    if (base == maxbase && ((base | size) & mask) != mask)

        return 0;

}

{

    if ((bar & PCI_BASE_ADDRESS_SPACE) == PCI_BASE_ADDRESS_SPACE_IO) {

        res->flags = bar & ~PCI_BASE_ADDRESS_IO_MASK;

        return pci_bar_io;

    }

        return pci_bar_mem64;

    return pci_bar_mem32;

}

 * pci_read_base - read a PCI BAR

 * @dev: the PCI device

 * @type: type of the BAR

 * @res: resource buffer to be filled in

 * @pos: BAR position in the config space

 *

 * Returns 1 if the BAR is 64-bit, or 0 if 32-bit.

 */

int __pci_read_base(struct pci_dev *dev, enum pci_bar_type type,

            struct resource *res, unsigned int pos)

{

    u32 l, sz, mask;

    u16 orig_cmd;

        pci_read_config_word(dev, PCI_COMMAND, &orig_cmd);

        pci_write_config_word(dev, PCI_COMMAND,

            orig_cmd & ~(PCI_COMMAND_MEMORY | PCI_COMMAND_IO));

    }

    pci_write_config_dword(dev, pos, l | mask);

    pci_read_config_dword(dev, pos, &sz);

    pci_write_config_dword(dev, pos, l);

        pci_write_config_word(dev, PCI_COMMAND, orig_cmd);

     * All bits set in sz means the device isn't working properly.

     * If the BAR isn't implemented, all bits must be 0.  If it's a

     * memory BAR or a ROM, bit 0 must be clear; if it's an io BAR, bit

     * 1 must be clear.

     */

    if (!sz || sz == 0xffffffff)

        goto fail;

     * I don't know how l can have all bits set.  Copied from old code.

     * Maybe it fixes a bug on some ancient platform.

     */

    if (l == 0xffffffff)

        l = 0;

        type = decode_bar(res, l);

        res->flags |= pci_calc_resource_flags(l) | IORESOURCE_SIZEALIGN;

        if (type == pci_bar_io) {

            l &= PCI_BASE_ADDRESS_IO_MASK;

            mask = PCI_BASE_ADDRESS_IO_MASK & IO_SPACE_LIMIT;

        } else {

            l &= PCI_BASE_ADDRESS_MEM_MASK;

            mask = (u32)PCI_BASE_ADDRESS_MEM_MASK;

        }

    } else {

        res->flags |= (l & IORESOURCE_ROM_ENABLE);

        l &= PCI_ROM_ADDRESS_MASK;

        mask = (u32)PCI_ROM_ADDRESS_MASK;

    }

        u64 l64 = l;

        u64 sz64 = sz;

        u64 mask64 = mask | (u64)~0 << 32;

        pci_write_config_dword(dev, pos + 4, ~0);

        pci_read_config_dword(dev, pos + 4, &sz);

        pci_write_config_dword(dev, pos + 4, l);

        sz64 |= ((u64)sz << 32);

            goto fail;

            dbgprintf("%s reg %x: can't handle 64-bit BAR\n",

                __FUNCTION__, pos);

            goto fail;

        }

        if ((sizeof(resource_size_t) < 8) && l) {

            /* Address above 32-bit boundary; disable the BAR */

            pci_write_config_dword(dev, pos, 0);

            pci_write_config_dword(dev, pos + 4, 0);

            res->start = 0;

            res->end = sz64;

        } else {

            res->start = l64;

            res->end = l64 + sz64;

        dbgprintf("%s reg %x: %pR\n", __FUNCTION__, pos, res);

        }

    } else {

        sz = pci_size(l, sz, mask);

            goto fail;

        res->end = l + sz;

    }

    return (type == pci_bar_mem64) ? 1 : 0;

 fail:

    res->flags = 0;

    goto out;

}

{

    unsigned int pos, reg;

        struct resource *res = &dev->resource[pos];

        reg = PCI_BASE_ADDRESS_0 + (pos << 2);

        pos += __pci_read_base(dev, pci_bar_unknown, res, reg);

    }

        struct resource *res = &dev->resource[PCI_ROM_RESOURCE];

        dev->rom_base_reg = rom;

        res->flags = IORESOURCE_MEM | IORESOURCE_PREFETCH |

                IORESOURCE_READONLY | IORESOURCE_CACHEABLE |

                IORESOURCE_SIZEALIGN;

        __pci_read_base(dev, pci_bar_mem32, res, rom);

    }

}

{

    struct pci_dev *dev = child->self;

    struct resource *res;

    int i;

        return;

         child->secondary, child->subordinate,

         dev->transparent ? " (subtractive decode)" : "");

    for (i = 0; i < PCI_BRIDGE_RESOURCE_NUM; i++)

        child->resource[i] = &dev->resource[PCI_BRIDGE_RESOURCES+i];

    pci_read_bridge_mmio(child);

    pci_read_bridge_mmio_pref(child);

        pci_bus_for_each_resource(child->parent, res, i) {

            if (res) {

                pci_bus_add_resource(child, res,

                             PCI_SUBTRACTIVE_DECODE);

                dbgprintf("  bridge window %pR (subtractive decode)\n", res);

            }

        }

    }

}

{

    struct pci_bus *b;

    if (b) {

        INIT_LIST_HEAD(&b->node);

        INIT_LIST_HEAD(&b->children);

        INIT_LIST_HEAD(&b->devices);

        INIT_LIST_HEAD(&b->slots);

        INIT_LIST_HEAD(&b->resources);

//        b->max_bus_speed = PCI_SPEED_UNKNOWN;

//        b->cur_bus_speed = PCI_SPEED_UNKNOWN;

    }

    return b;

}

    PCI_SPEED_UNKNOWN,      /* 0 */

    PCI_SPEED_66MHz_PCIX,       /* 1 */

    PCI_SPEED_100MHz_PCIX,      /* 2 */

    PCI_SPEED_133MHz_PCIX,      /* 3 */

    PCI_SPEED_UNKNOWN,      /* 4 */

    PCI_SPEED_66MHz_PCIX_ECC,   /* 5 */

    PCI_SPEED_100MHz_PCIX_ECC,  /* 6 */

    PCI_SPEED_133MHz_PCIX_ECC,  /* 7 */

    PCI_SPEED_UNKNOWN,      /* 8 */

    PCI_SPEED_66MHz_PCIX_266,   /* 9 */

    PCI_SPEED_100MHz_PCIX_266,  /* A */

    PCI_SPEED_133MHz_PCIX_266,  /* B */

    PCI_SPEED_UNKNOWN,      /* C */

    PCI_SPEED_66MHz_PCIX_533,   /* D */

    PCI_SPEED_100MHz_PCIX_533,  /* E */

    PCI_SPEED_133MHz_PCIX_533   /* F */

};

    PCI_SPEED_UNKNOWN,      /* 0 */

    PCIE_SPEED_2_5GT,       /* 1 */

    PCIE_SPEED_5_0GT,       /* 2 */

    PCIE_SPEED_8_0GT,       /* 3 */

    PCI_SPEED_UNKNOWN,      /* 4 */

    PCI_SPEED_UNKNOWN,      /* 5 */

    PCI_SPEED_UNKNOWN,      /* 6 */

    PCI_SPEED_UNKNOWN,      /* 7 */

    PCI_SPEED_UNKNOWN,      /* 8 */

    PCI_SPEED_UNKNOWN,      /* 9 */

    PCI_SPEED_UNKNOWN,      /* A */

    PCI_SPEED_UNKNOWN,      /* B */

    PCI_SPEED_UNKNOWN,      /* C */

    PCI_SPEED_UNKNOWN,      /* D */

    PCI_SPEED_UNKNOWN,      /* E */

    PCI_SPEED_UNKNOWN       /* F */

};

{

    struct pci_dev *bridge = bus->self;

    int pos;

    if (!pos)

        pos = pci_find_capability(bridge, PCI_CAP_ID_AGP3);

    if (pos) {

        u32 agpstat, agpcmd;

        bus->max_bus_speed = agp_speed(agpstat & 8, agpstat & 7);

        bus->cur_bus_speed = agp_speed(agpstat & 8, agpcmd & 7);

    }

    if (pos) {

        u16 status;

        enum pci_bus_speed max;

        pci_read_config_word(bridge, pos + 2, &status);

            max = PCI_SPEED_133MHz_PCIX_533;

        } else if (status & 0x4000) {

            max = PCI_SPEED_133MHz_PCIX_266;

        } else if (status & 0x0002) {

            if (((status >> 12) & 0x3) == 2) {

                max = PCI_SPEED_133MHz_PCIX_ECC;

            } else {

                max = PCI_SPEED_133MHz_PCIX;

            }

        } else {

            max = PCI_SPEED_66MHz_PCIX;

        }

        bus->cur_bus_speed = pcix_bus_speed[(status >> 6) & 0xf];

    }

    if (pos) {

        u32 linkcap;

        u16 linksta;

        bus->max_bus_speed = pcie_link_speed[linkcap & 0xf];

        pcie_update_link_speed(bus, linksta);

    }

}

                       struct pci_dev *bridge, int busnr)

{

    struct pci_bus *child;

    int i;

     * Allocate a new bus, and inherit stuff from the parent..

     */

    child = pci_alloc_bus();

    if (!child)

        return NULL;

    child->ops = parent->ops;

    child->sysdata = parent->sysdata;

    child->bus_flags = parent->bus_flags;

     * now as the parent is not properly set up yet.  This device will get

     * registered later in pci_bus_add_devices()

     */

//    child->dev.class = &pcibus_class;

//    dev_set_name(&child->dev, "%04x:%02x", pci_domain_nr(child), busnr);

     * Set up the primary, secondary and subordinate

     * bus numbers.

     */

    child->number = child->secondary = busnr;

    child->primary = parent->secondary;

    child->subordinate = 0xff;

        return child;

//    child->bridge = get_device(&bridge->dev);

    for (i = 0; i < PCI_BRIDGE_RESOURCE_NUM; i++) {

        child->resource[i] = &bridge->resource[PCI_BRIDGE_RESOURCES+i];

        child->resource[i]->name = child->name;

    }

    bridge->subordinate = child;

}

{

    struct pci_bus *child;

    if (child) {

//        down_write(&pci_bus_sem);

        list_add_tail(&child->node, &parent->children);

//        up_write(&pci_bus_sem);

    }

    return child;

}

{

    struct pci_bus *parent = child->parent;

       we're going to re-assign all bus numbers. */

    if (!pcibios_assign_all_busses())

        return;

        parent->subordinate = max;

        pci_write_config_byte(parent->self, PCI_SUBORDINATE_BUS, max);

        parent = parent->parent;

    }

}

 * If it's a bridge, configure it and scan the bus behind it.

 * For CardBus bridges, we don't scan behind as the devices will

 * be handled by the bridge driver itself.

 *

 * We need to process bridges in two passes -- first we scan those

 * already configured by the BIOS and after we are done with all of

 * them, we proceed to assigning numbers to the remaining buses in

 * order to avoid overlaps between old and new bus numbers.

 */

int pci_scan_bridge(struct pci_bus *bus, struct pci_dev *dev, int max, int pass)

{

    struct pci_bus *child;

    int is_cardbus = (dev->hdr_type == PCI_HEADER_TYPE_CARDBUS);

    u32 buses, i, j = 0;

    u16 bctl;

    u8 primary, secondary, subordinate;

    int broken = 0;

    primary = buses & 0xFF;

    secondary = (buses >> 8) & 0xFF;

    subordinate = (buses >> 16) & 0xFF;

        secondary, subordinate, pass);

    if (!pass &&

        (primary != bus->number || secondary <= bus->number)) {

        dbgprintf("bus configuration invalid, reconfiguring\n");

        broken = 1;

    }

       of bus errors (in some architectures) */

    pci_read_config_word(dev, PCI_BRIDGE_CONTROL, &bctl);

    pci_write_config_word(dev, PCI_BRIDGE_CONTROL,

                  bctl & ~PCI_BRIDGE_CTL_MASTER_ABORT);

        !is_cardbus && !broken) {

        unsigned int cmax;

        /*

         * Bus already configured by firmware, process it in the first

         * pass and just note the configuration.

         */

        if (pass)

            goto out;

         * If we already got to this bus through a different bridge,

         * don't re-add it. This can happen with the i450NX chipset.

         *

         * However, we continue to descend down the hierarchy and

         * scan remaining child buses.

         */

        child = pci_find_bus(pci_domain_nr(bus), secondary);

        if (!child) {

            child = pci_add_new_bus(bus, dev, secondary);

            if (!child)

                goto out;

            child->primary = primary;

            child->subordinate = subordinate;

            child->bridge_ctl = bctl;

        }

        if (cmax > max)

            max = cmax;

        if (child->subordinate > max)

            max = child->subordinate;

    } else {

        /*

         * We need to assign a number to this bus which we always

         * do in the second pass.

         */

        if (!pass) {

            if (pcibios_assign_all_busses() || broken)

                /* Temporarily disable forwarding of the

                   configuration cycles on all bridges in

                   this bus segment to avoid possible

                   conflicts in the second pass between two

                   bridges programmed with overlapping

                   bus ranges. */

                pci_write_config_dword(dev, PCI_PRIMARY_BUS,

                               buses & ~0xffffff);

            goto out;

        }

        pci_write_config_word(dev, PCI_STATUS, 0xffff);

         * This can happen when a bridge is hot-plugged */

        if (pci_find_bus(pci_domain_nr(bus), max+1))

            goto out;

        child = pci_add_new_bus(bus, dev, ++max);

        buses = (buses & 0xff000000)

              | ((unsigned int)(child->primary)     <<  0)

              | ((unsigned int)(child->secondary)   <<  8)

              | ((unsigned int)(child->subordinate) << 16);

         * yenta.c forces a secondary latency timer of 176.

         * Copy that behaviour here.

         */

        if (is_cardbus) {

            buses &= ~0xff000000;

            buses |= CARDBUS_LATENCY_TIMER << 24;

        }

         * We need to blast all three values with a single write.

         */

        pci_write_config_dword(dev, PCI_PRIMARY_BUS, buses);

            child->bridge_ctl = bctl;

            /*

             * Adjust subordinate busnr in parent buses.

             * We do this before scanning for children because

             * some devices may not be detected if the bios

             * was lazy.

             */

            pci_fixup_parent_subordinate_busnr(child, max);

            /* Now we can scan all subordinate buses... */

            max = pci_scan_child_bus(child);

            /*

             * now fix it up again since we have found

             * the real value of max.

             */

            pci_fixup_parent_subordinate_busnr(child, max);

        } else {

            /*

             * For CardBus bridges, we leave 4 bus numbers

             * as cards with a PCI-to-PCI bridge can be

             * inserted later.

             */

            for (i=0; i

                struct pci_bus *parent = bus;

                if (pci_find_bus(pci_domain_nr(bus),

                            max+i+1))

                    break;

                while (parent->parent) {

                    if ((!pcibios_assign_all_busses()) &&

                        (parent->subordinate > max) &&

                        (parent->subordinate <= max+i)) {

                        j = 1;

                    }

                    parent = parent->parent;

                }

                if (j) {

                    /*

                     * Often, there are two cardbus bridges

                     * -- try to leave one valid bus number

                     * for each one.

                     */

                    i /= 2;

                    break;

                }

            }

            max += i;

            pci_fixup_parent_subordinate_busnr(child, max);

        }

        /*

         * Set the subordinate bus number to its real value.

         */

        child->subordinate = max;

        pci_write_config_byte(dev, PCI_SUBORDINATE_BUS, max);

    }

        (is_cardbus ? "PCI CardBus %04x:%02x" : "PCI Bus %04x:%02x"),

        pci_domain_nr(bus), child->number);

    while (bus->parent) {

        if ((child->subordinate > bus->subordinate) ||

            (child->number > bus->subordinate) ||

            (child->number < bus->number) ||

            (child->subordinate < bus->number)) {

            dbgprintf("[bus %02x-%02x] %s "

                "hidden behind%s bridge %s [bus %02x-%02x]\n",

                child->number, child->subordinate,

                (bus->number > child->subordinate &&

                 bus->subordinate < child->number) ?

                    "wholly" : "partially",

                bus->self->transparent ? " transparent" : "",

                "FIX BRIDGE NAME",

                bus->number, bus->subordinate);

        }

        bus = bus->parent;

    }

    pci_write_config_word(dev, PCI_BRIDGE_CONTROL, bctl);

}

{

    int pos;

    u16 reg16;

    if (!pos)

        return;

    //pdev->is_pcie = 1;

    pdev->pcie_cap = pos;

    pci_read_config_word(pdev, pos + PCI_EXP_FLAGS, ®16);

    pdev->pcie_type = (reg16 & PCI_EXP_FLAGS_TYPE) >> 4;

}

{

    int pos;

    u16 reg16;

    u32 reg32;

    if (!pos)

        return;

    pci_read_config_word(pdev, pos + PCI_EXP_FLAGS, ®16);

    if (!(reg16 & PCI_EXP_FLAGS_SLOT))

        return;

    pci_read_config_dword(pdev, pos + PCI_EXP_SLTCAP, ®32);

    if (reg32 & PCI_EXP_SLTCAP_HPC)

        pdev->is_hotplug_bridge = 1;

}

 * Read interrupt line and base address registers.

 * The architecture-dependent code can tweak these, of course.

 */

static void pci_read_irq(struct pci_dev *dev)

{

    unsigned char irq;

    dev->pin = irq;

    if (irq)

        pci_read_config_byte(dev, PCI_INTERRUPT_LINE, &irq);

    dev->irq = irq;

}

 * pci_setup_device - fill in class and map information of a device

 * @dev: the device structure to fill

 *

 * Initialize the device structure with information about the device's

 * vendor,class,memory and IO-space addresses,IRQ lines etc.

 * Called at initialisation of the PCI subsystem and by CardBus services.

 * Returns 0 on success and negative if unknown type of device (not normal,

 * bridge or CardBus).

 */

int pci_setup_device(struct pci_dev *dev)

{

    u32 class;

    u8 hdr_type;

    struct pci_slot *slot;

    int pos = 0;

        return -EIO;

//    dev->dev.parent = dev->bus->bridge;

//    dev->dev.bus = &pci_bus_type;

    dev->hdr_type = hdr_type & 0x7f;

    dev->multifunction = !!(hdr_type & 0x80);

    dev->error_state = pci_channel_io_normal;

    set_pcie_port_type(dev);

        if (PCI_SLOT(dev->devfn) == slot->number)

            dev->slot = slot;

       set this higher, assuming the system even supports it.  */

    dev->dma_mask = 0xffffffff;

//             dev->bus->number, PCI_SLOT(dev->devfn),

//             PCI_FUNC(dev->devfn));

    dev->revision = class & 0xff;

    class >>= 8;                    /* upper 3 bytes */

    dev->class = class;

    class >>= 8;

         dev->vendor, dev->device, class, dev->hdr_type);

    dev->cfg_size = pci_cfg_space_size(dev);

    dev->current_state = PCI_UNKNOWN;

//    pci_fixup_device(pci_fixup_early, dev);

    /* device class may be changed after fixup */

    class = dev->class >> 8;

    case PCI_HEADER_TYPE_NORMAL:            /* standard header */

        if (class == PCI_CLASS_BRIDGE_PCI)

            goto bad;

        pci_read_irq(dev);

        pci_read_bases(dev, 6, PCI_ROM_ADDRESS);

        pci_read_config_word(dev, PCI_SUBSYSTEM_VENDOR_ID, &dev->subsystem_vendor);

        pci_read_config_word(dev, PCI_SUBSYSTEM_ID, &dev->subsystem_device);

         *  Do the ugly legacy mode stuff here rather than broken chip

         *  quirk code. Legacy mode ATA controllers have fixed

         *  addresses. These are not always echoed in BAR0-3, and

         *  BAR0-3 in a few cases contain junk!

         */

        if (class == PCI_CLASS_STORAGE_IDE) {

            u8 progif;

            pci_read_config_byte(dev, PCI_CLASS_PROG, &progif);

            if ((progif & 1) == 0) {

                dev->resource[0].start = 0x1F0;

                dev->resource[0].end = 0x1F7;

                dev->resource[0].flags = LEGACY_IO_RESOURCE;

                dev->resource[1].start = 0x3F6;

                dev->resource[1].end = 0x3F6;

                dev->resource[1].flags = LEGACY_IO_RESOURCE;

            }

            if ((progif & 4) == 0) {

                dev->resource[2].start = 0x170;

                dev->resource[2].end = 0x177;

                dev->resource[2].flags = LEGACY_IO_RESOURCE;

                dev->resource[3].start = 0x376;

                dev->resource[3].end = 0x376;

                dev->resource[3].flags = LEGACY_IO_RESOURCE;

            }

        }

        break;

        if (class != PCI_CLASS_BRIDGE_PCI)

            goto bad;

        /* The PCI-to-PCI bridge spec requires that subtractive

           decoding (i.e. transparent) bridge must have programming

           interface code of 0x01. */

        pci_read_irq(dev);

        dev->transparent = ((dev->class & 0xff) == 1);

        pci_read_bases(dev, 2, PCI_ROM_ADDRESS1);

        set_pcie_hotplug_bridge(dev);

        pos = pci_find_capability(dev, PCI_CAP_ID_SSVID);

        if (pos) {

            pci_read_config_word(dev, pos + PCI_SSVID_VENDOR_ID, &dev->subsystem_vendor);

            pci_read_config_word(dev, pos + PCI_SSVID_DEVICE_ID, &dev->subsystem_device);

        }

        break;

        if (class != PCI_CLASS_BRIDGE_CARDBUS)

            goto bad;

        pci_read_irq(dev);

        pci_read_bases(dev, 1, 0);

        pci_read_config_word(dev, PCI_CB_SUBSYSTEM_VENDOR_ID, &dev->subsystem_vendor);

        pci_read_config_word(dev, PCI_CB_SUBSYSTEM_ID, &dev->subsystem_device);

        break;

        dbgprintf("unknown header type %02x, "

            "ignoring device\n", dev->hdr_type);

        return -EIO;

        dbgprintf("ignoring class %02x (doesn't match header "

            "type %02x)\n", class, dev->hdr_type);

        dev->class = PCI_CLASS_NOT_DEFINED;

    }

    return 0;

}

{

    struct pci_dev *dev;

    if (!dev)

        return NULL;

}

 * Read the config data for a PCI device, sanity-check it

 * and fill in the dev structure...

 */

static struct pci_dev *pci_scan_device(struct pci_bus *bus, int devfn)

{

    struct pci_dev *dev;

    u32 l;

    int timeout = 10;

        return NULL;

    if (l == 0xffffffff || l == 0x00000000 ||

        l == 0x0000ffff || l == 0xffff0000)

        return NULL;

    while (l == 0xffff0001) {

        delay(timeout/10);

        timeout *= 2;

        if (pci_bus_read_config_dword(bus, devfn, PCI_VENDOR_ID, &l))

            return NULL;

        /* Card hasn't responded in 60 seconds?  Must be stuck. */

        if (timeout > 60 * 1000) {

            printk(KERN_WARNING "pci %04x:%02x:%02x.%d: not "

                    "responding\n", pci_domain_nr(bus),

                    bus->number, PCI_SLOT(devfn),

                    PCI_FUNC(devfn));

            return NULL;

        }

    }

    if (!dev)

        return NULL;

    dev->busnr = bus->number;

    dev->devfn = devfn;

    dev->vendor = l & 0xffff;

    dev->device = (l >> 16) & 0xffff;

        kfree(dev);

        return NULL;

    }

}

{

//    device_initialize(&dev->dev);

//    dev->dev.release = pci_release_dev;

//    pci_dev_get(dev);

//    dev->dev.dma_parms = &dev->dma_parms;

//    dev->dev.coherent_dma_mask = 0xffffffffull;

//    pci_set_dma_seg_boundary(dev, 0xffffffff);

//    pci_fixup_device(pci_fixup_header, dev);

    dev->state_saved = false;

//    pci_init_capabilities(dev);

     * Add the device to our list of discovered devices

     * and the bus list for fixup functions, etc.

     */

//    down_write(&pci_bus_sem);

    list_add_tail(&dev->bus_list, &bus->devices);

//    up_write(&pci_bus_sem);

}

{

    struct pci_dev *dev;

    if (dev) {

//        pci_dev_put(dev);

        return dev;

    }

    if (!dev)

        return NULL;

}

{

    u16 cap;

    unsigned pos, next_fn;

        return 0;

    if (!pos)

        return 0;

    pci_read_config_word(dev, pos + 4, &cap);

    next_fn = cap >> 8;

    if (next_fn <= fn)

        return 0;

    return next_fn;

}

{

    return (fn + 1) % 8;

}

{

    return 0;

}

{

    struct pci_dev *parent = bus->self;

    if (!parent || !pci_is_pcie(parent))

        return 0;

    if (parent->pcie_type == PCI_EXP_TYPE_ROOT_PORT ||

        parent->pcie_type == PCI_EXP_TYPE_DOWNSTREAM)

        return 1;

    return 0;

}

 * pci_scan_slot - scan a PCI slot on a bus for devices.

 * @bus: PCI bus to scan

 * @devfn: slot number to scan (must have zero function.)

 *

 * Scan a PCI slot on the specified PCI bus for devices, adding

 * discovered devices to the @bus->devices list.  New devices

 * will not have is_added set.

 *

 * Returns the number of new devices found.

 */

int pci_scan_slot(struct pci_bus *bus, int devfn)

{

    unsigned fn, nr = 0;

    struct pci_dev *dev;

    unsigned (*next_fn)(struct pci_dev *, unsigned) = no_next_fn;

        return 0; /* Already scanned the entire slot */

    if (!dev)

        return 0;

    if (!dev->is_added)

        nr++;

        next_fn = next_ari_fn;

    else if (dev->multifunction)

        next_fn = next_trad_fn;

        dev = pci_scan_single_device(bus, devfn + fn);

        if (dev) {

            if (!dev->is_added)

                nr++;

            dev->multifunction = 1;

        }

    }

//    if (bus->self && nr)

//        pcie_aspm_init_link_state(bus->self);

}

{

    unsigned int devfn, pass, max = bus->secondary;

    struct pci_dev *dev;

    for (devfn = 0; devfn < 0x100; devfn += 8)

        pci_scan_slot(bus, devfn);

    //max += pci_iov_bus_range(bus);

     * After performing arch-dependent fixup of the bus, look behind

     * all PCI-to-PCI bridges on this bus.

     */

    if (!bus->is_added) {

        dbgprintf("fixups for bus\n");

//        pcibios_fixup_bus(bus);

        if (pci_is_root_bus(bus))

            bus->is_added = 1;

    }

        list_for_each_entry(dev, &bus->devices, bus_list) {

            if (dev->hdr_type == PCI_HEADER_TYPE_BRIDGE ||

                dev->hdr_type == PCI_HEADER_TYPE_CARDBUS)

                max = pci_scan_bridge(bus, dev, max, pass);

        }

     * We've scanned the bus and so we know all about what's on

     * the other side of any bridges that may be on this bus plus

     * any devices.

     *

     * Return how far we've got finding sub-buses.

     */

    dbgprintf("bus scan returning with max=%02x\n", max);

    return max;

}

 * pci_cfg_space_size - get the configuration space size of the PCI device.

 * @dev: PCI device

 *

 * Regular PCI devices have 256 bytes, but PCI-X 2 and PCI Express devices

 * have 4096 bytes.  Even if the device is capable, that doesn't mean we can

 * access it.  Maybe we don't have a way to generate extended config space

 * accesses, or the device is behind a reverse Express bridge.  So we try

 * reading the dword at 0x100 which must either be 0 or a valid extended

 * capability header.

 */

int pci_cfg_space_size_ext(struct pci_dev *dev)

{

    u32 status;

    int pos = PCI_CFG_SPACE_SIZE;

        goto fail;

    if (status == 0xffffffff)

        goto fail;

    return PCI_CFG_SPACE_SIZE;

}

{

    int pos;

    u32 status;

    u16 class;

    if (class == PCI_CLASS_BRIDGE_HOST)

        return pci_cfg_space_size_ext(dev);

    if (!pos) {

        pos = pci_find_capability(dev, PCI_CAP_ID_PCIX);

        if (!pos)