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Rev | Author | Line No. | Line |
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1628 | serge | 1 | |
2 | #include |
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3 | #include |
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4 | #include |
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5 | #include |
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2187 | Serge | 6 | #include |
1628 | serge | 7 | |
8 | |||
1631 | serge | 9 | |
1628 | serge | 10 | |
1631 | serge | 11 | |
12 | |||
13 | |||
14 | |||
15 | |||
1628 | serge | 16 | |
17 | |||
1631 | serge | 18 | #define CARDBUS_RESERVE_BUSNR 3 |
19 | |||
20 | |||
21 | { |
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22 | return 0; |
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23 | }; |
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24 | |||
25 | |||
1628 | serge | 26 | * pci_ari_enabled - query ARI forwarding status |
1631 | serge | 27 | * @bus: the PCI bus |
28 | * |
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29 | * Returns 1 if ARI forwarding is enabled, or 0 if not enabled; |
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30 | */ |
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31 | static inline int pci_ari_enabled(struct pci_bus *bus) |
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32 | { |
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33 | return bus->self && bus->self->ari_enabled; |
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34 | } |
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35 | |||
36 | |||
37 | * Translate the low bits of the PCI base |
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38 | * to the resource type |
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39 | */ |
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40 | static inline unsigned int pci_calc_resource_flags(unsigned int flags) |
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41 | { |
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42 | if (flags & PCI_BASE_ADDRESS_SPACE_IO) |
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43 | return IORESOURCE_IO; |
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44 | |||
45 | |||
46 | return IORESOURCE_MEM | IORESOURCE_PREFETCH; |
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47 | |||
48 | |||
49 | } |
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50 | |||
51 | |||
52 | { |
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53 | u64 size = mask & maxbase; /* Find the significant bits */ |
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54 | if (!size) |
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55 | return 0; |
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56 | |||
57 | |||
58 | from that the extent. */ |
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59 | size = (size & ~(size-1)) - 1; |
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60 | |||
61 | |||
62 | already been programmed with all 1s. */ |
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63 | if (base == maxbase && ((base | size) & mask) != mask) |
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64 | return 0; |
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65 | |||
66 | |||
67 | } |
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68 | |||
69 | |||
70 | { |
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71 | if ((bar & PCI_BASE_ADDRESS_SPACE) == PCI_BASE_ADDRESS_SPACE_IO) { |
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72 | res->flags = bar & ~PCI_BASE_ADDRESS_IO_MASK; |
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73 | return pci_bar_io; |
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74 | } |
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75 | |||
76 | |||
77 | |||
78 | |||
79 | return pci_bar_mem64; |
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80 | return pci_bar_mem32; |
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81 | } |
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82 | |||
83 | |||
84 | |||
85 | |||
86 | * pci_read_base - read a PCI BAR |
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87 | * @dev: the PCI device |
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88 | * @type: type of the BAR |
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89 | * @res: resource buffer to be filled in |
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90 | * @pos: BAR position in the config space |
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91 | * |
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92 | * Returns 1 if the BAR is 64-bit, or 0 if 32-bit. |
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93 | */ |
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94 | int __pci_read_base(struct pci_dev *dev, enum pci_bar_type type, |
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95 | struct resource *res, unsigned int pos) |
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96 | { |
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97 | u32 l, sz, mask; |
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98 | u16 orig_cmd; |
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99 | |||
100 | |||
101 | |||
102 | |||
103 | pci_read_config_word(dev, PCI_COMMAND, &orig_cmd); |
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104 | pci_write_config_word(dev, PCI_COMMAND, |
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105 | orig_cmd & ~(PCI_COMMAND_MEMORY | PCI_COMMAND_IO)); |
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106 | } |
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107 | |||
108 | |||
109 | |||
110 | |||
111 | pci_write_config_dword(dev, pos, l | mask); |
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112 | pci_read_config_dword(dev, pos, &sz); |
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113 | pci_write_config_dword(dev, pos, l); |
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114 | |||
115 | |||
116 | pci_write_config_word(dev, PCI_COMMAND, orig_cmd); |
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117 | |||
118 | |||
119 | * All bits set in sz means the device isn't working properly. |
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120 | * If the BAR isn't implemented, all bits must be 0. If it's a |
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121 | * memory BAR or a ROM, bit 0 must be clear; if it's an io BAR, bit |
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122 | * 1 must be clear. |
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123 | */ |
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124 | if (!sz || sz == 0xffffffff) |
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125 | goto fail; |
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126 | |||
127 | |||
128 | * I don't know how l can have all bits set. Copied from old code. |
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129 | * Maybe it fixes a bug on some ancient platform. |
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130 | */ |
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131 | if (l == 0xffffffff) |
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132 | l = 0; |
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133 | |||
134 | |||
135 | type = decode_bar(res, l); |
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136 | res->flags |= pci_calc_resource_flags(l) | IORESOURCE_SIZEALIGN; |
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137 | if (type == pci_bar_io) { |
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138 | l &= PCI_BASE_ADDRESS_IO_MASK; |
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139 | mask = PCI_BASE_ADDRESS_IO_MASK & IO_SPACE_LIMIT; |
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140 | } else { |
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141 | l &= PCI_BASE_ADDRESS_MEM_MASK; |
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142 | mask = (u32)PCI_BASE_ADDRESS_MEM_MASK; |
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143 | } |
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144 | } else { |
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145 | res->flags |= (l & IORESOURCE_ROM_ENABLE); |
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146 | l &= PCI_ROM_ADDRESS_MASK; |
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147 | mask = (u32)PCI_ROM_ADDRESS_MASK; |
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148 | } |
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149 | |||
150 | |||
151 | u64 l64 = l; |
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152 | u64 sz64 = sz; |
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153 | u64 mask64 = mask | (u64)~0 << 32; |
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154 | |||
155 | |||
156 | pci_write_config_dword(dev, pos + 4, ~0); |
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157 | pci_read_config_dword(dev, pos + 4, &sz); |
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158 | pci_write_config_dword(dev, pos + 4, l); |
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159 | |||
160 | |||
161 | sz64 |= ((u64)sz << 32); |
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162 | |||
163 | |||
164 | |||
165 | |||
166 | goto fail; |
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167 | |||
168 | |||
169 | dbgprintf("%s reg %x: can't handle 64-bit BAR\n", |
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170 | __FUNCTION__, pos); |
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171 | goto fail; |
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172 | } |
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173 | |||
174 | |||
175 | if ((sizeof(resource_size_t) < 8) && l) { |
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176 | /* Address above 32-bit boundary; disable the BAR */ |
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177 | pci_write_config_dword(dev, pos, 0); |
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178 | pci_write_config_dword(dev, pos + 4, 0); |
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179 | res->start = 0; |
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180 | res->end = sz64; |
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181 | } else { |
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182 | res->start = l64; |
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183 | res->end = l64 + sz64; |
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184 | dbgprintf("%s reg %x: %pR\n", __FUNCTION__, pos, res); |
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185 | } |
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186 | } else { |
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187 | sz = pci_size(l, sz, mask); |
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188 | |||
189 | |||
190 | goto fail; |
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191 | |||
192 | |||
193 | res->end = l + sz; |
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194 | |||
195 | |||
196 | } |
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197 | |||
198 | |||
199 | return (type == pci_bar_mem64) ? 1 : 0; |
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200 | fail: |
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201 | res->flags = 0; |
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202 | goto out; |
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203 | } |
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204 | |||
205 | |||
206 | { |
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207 | unsigned int pos, reg; |
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208 | |||
209 | |||
210 | struct resource *res = &dev->resource[pos]; |
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211 | reg = PCI_BASE_ADDRESS_0 + (pos << 2); |
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212 | pos += __pci_read_base(dev, pci_bar_unknown, res, reg); |
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213 | } |
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214 | |||
215 | |||
216 | struct resource *res = &dev->resource[PCI_ROM_RESOURCE]; |
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217 | dev->rom_base_reg = rom; |
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218 | res->flags = IORESOURCE_MEM | IORESOURCE_PREFETCH | |
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219 | IORESOURCE_READONLY | IORESOURCE_CACHEABLE | |
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220 | IORESOURCE_SIZEALIGN; |
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221 | __pci_read_base(dev, pci_bar_mem32, res, rom); |
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222 | } |
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223 | } |
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224 | |||
225 | |||
226 | |||
227 | |||
228 | { |
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229 | struct pci_dev *dev = child->self; |
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230 | struct resource *res; |
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231 | int i; |
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232 | |||
233 | |||
234 | return; |
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235 | |||
236 | |||
237 | child->secondary, child->subordinate, |
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238 | dev->transparent ? " (subtractive decode)" : ""); |
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239 | |||
240 | |||
241 | for (i = 0; i < PCI_BRIDGE_RESOURCE_NUM; i++) |
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242 | child->resource[i] = &dev->resource[PCI_BRIDGE_RESOURCES+i]; |
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243 | |||
244 | |||
245 | pci_read_bridge_mmio(child); |
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246 | pci_read_bridge_mmio_pref(child); |
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247 | |||
248 | |||
249 | pci_bus_for_each_resource(child->parent, res, i) { |
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250 | if (res) { |
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251 | pci_bus_add_resource(child, res, |
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252 | PCI_SUBTRACTIVE_DECODE); |
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253 | dbgprintf(" bridge window %pR (subtractive decode)\n", res); |
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254 | } |
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255 | } |
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256 | } |
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257 | } |
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258 | |||
259 | |||
260 | |||
261 | |||
262 | { |
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263 | struct pci_bus *b; |
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264 | |||
265 | |||
266 | if (b) { |
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267 | INIT_LIST_HEAD(&b->node); |
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268 | INIT_LIST_HEAD(&b->children); |
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269 | INIT_LIST_HEAD(&b->devices); |
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270 | INIT_LIST_HEAD(&b->slots); |
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271 | INIT_LIST_HEAD(&b->resources); |
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272 | // b->max_bus_speed = PCI_SPEED_UNKNOWN; |
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273 | // b->cur_bus_speed = PCI_SPEED_UNKNOWN; |
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274 | } |
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275 | return b; |
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276 | } |
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277 | |||
278 | |||
279 | |||
280 | |||
281 | |||
282 | PCI_SPEED_UNKNOWN, /* 0 */ |
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283 | PCI_SPEED_66MHz_PCIX, /* 1 */ |
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284 | PCI_SPEED_100MHz_PCIX, /* 2 */ |
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285 | PCI_SPEED_133MHz_PCIX, /* 3 */ |
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286 | PCI_SPEED_UNKNOWN, /* 4 */ |
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287 | PCI_SPEED_66MHz_PCIX_ECC, /* 5 */ |
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288 | PCI_SPEED_100MHz_PCIX_ECC, /* 6 */ |
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289 | PCI_SPEED_133MHz_PCIX_ECC, /* 7 */ |
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290 | PCI_SPEED_UNKNOWN, /* 8 */ |
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291 | PCI_SPEED_66MHz_PCIX_266, /* 9 */ |
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292 | PCI_SPEED_100MHz_PCIX_266, /* A */ |
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293 | PCI_SPEED_133MHz_PCIX_266, /* B */ |
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294 | PCI_SPEED_UNKNOWN, /* C */ |
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295 | PCI_SPEED_66MHz_PCIX_533, /* D */ |
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296 | PCI_SPEED_100MHz_PCIX_533, /* E */ |
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297 | PCI_SPEED_133MHz_PCIX_533 /* F */ |
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298 | }; |
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299 | |||
300 | |||
301 | PCI_SPEED_UNKNOWN, /* 0 */ |
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302 | PCIE_SPEED_2_5GT, /* 1 */ |
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303 | PCIE_SPEED_5_0GT, /* 2 */ |
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304 | PCIE_SPEED_8_0GT, /* 3 */ |
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305 | PCI_SPEED_UNKNOWN, /* 4 */ |
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306 | PCI_SPEED_UNKNOWN, /* 5 */ |
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307 | PCI_SPEED_UNKNOWN, /* 6 */ |
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308 | PCI_SPEED_UNKNOWN, /* 7 */ |
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309 | PCI_SPEED_UNKNOWN, /* 8 */ |
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310 | PCI_SPEED_UNKNOWN, /* 9 */ |
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311 | PCI_SPEED_UNKNOWN, /* A */ |
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312 | PCI_SPEED_UNKNOWN, /* B */ |
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313 | PCI_SPEED_UNKNOWN, /* C */ |
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314 | PCI_SPEED_UNKNOWN, /* D */ |
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315 | PCI_SPEED_UNKNOWN, /* E */ |
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316 | PCI_SPEED_UNKNOWN /* F */ |
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317 | }; |
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318 | |||
319 | |||
320 | |||
321 | { |
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322 | struct pci_dev *bridge = bus->self; |
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323 | int pos; |
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324 | |||
325 | |||
326 | if (!pos) |
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327 | pos = pci_find_capability(bridge, PCI_CAP_ID_AGP3); |
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328 | if (pos) { |
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329 | u32 agpstat, agpcmd; |
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330 | |||
331 | |||
332 | bus->max_bus_speed = agp_speed(agpstat & 8, agpstat & 7); |
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333 | |||
334 | |||
335 | bus->cur_bus_speed = agp_speed(agpstat & 8, agpcmd & 7); |
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336 | } |
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337 | |||
338 | |||
339 | if (pos) { |
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340 | u16 status; |
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341 | enum pci_bus_speed max; |
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342 | pci_read_config_word(bridge, pos + 2, &status); |
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343 | |||
344 | |||
345 | max = PCI_SPEED_133MHz_PCIX_533; |
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346 | } else if (status & 0x4000) { |
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347 | max = PCI_SPEED_133MHz_PCIX_266; |
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348 | } else if (status & 0x0002) { |
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349 | if (((status >> 12) & 0x3) == 2) { |
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350 | max = PCI_SPEED_133MHz_PCIX_ECC; |
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351 | } else { |
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352 | max = PCI_SPEED_133MHz_PCIX; |
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353 | } |
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354 | } else { |
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355 | max = PCI_SPEED_66MHz_PCIX; |
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356 | } |
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357 | |||
358 | |||
359 | bus->cur_bus_speed = pcix_bus_speed[(status >> 6) & 0xf]; |
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360 | |||
361 | |||
362 | } |
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363 | |||
364 | |||
365 | if (pos) { |
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366 | u32 linkcap; |
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367 | u16 linksta; |
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368 | |||
369 | |||
370 | bus->max_bus_speed = pcie_link_speed[linkcap & 0xf]; |
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371 | |||
372 | |||
373 | pcie_update_link_speed(bus, linksta); |
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374 | } |
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375 | } |
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376 | |||
377 | |||
378 | |||
379 | |||
380 | |||
381 | struct pci_dev *bridge, int busnr) |
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382 | { |
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383 | struct pci_bus *child; |
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384 | int i; |
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385 | |||
386 | |||
387 | * Allocate a new bus, and inherit stuff from the parent.. |
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388 | */ |
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389 | child = pci_alloc_bus(); |
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390 | if (!child) |
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391 | return NULL; |
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392 | |||
393 | |||
394 | child->ops = parent->ops; |
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395 | child->sysdata = parent->sysdata; |
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396 | child->bus_flags = parent->bus_flags; |
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397 | |||
398 | |||
399 | * now as the parent is not properly set up yet. This device will get |
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400 | * registered later in pci_bus_add_devices() |
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401 | */ |
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402 | // child->dev.class = &pcibus_class; |
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403 | // dev_set_name(&child->dev, "%04x:%02x", pci_domain_nr(child), busnr); |
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404 | |||
405 | |||
406 | * Set up the primary, secondary and subordinate |
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407 | * bus numbers. |
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408 | */ |
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409 | child->number = child->secondary = busnr; |
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410 | child->primary = parent->secondary; |
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411 | child->subordinate = 0xff; |
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412 | |||
413 | |||
414 | return child; |
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415 | |||
416 | |||
417 | // child->bridge = get_device(&bridge->dev); |
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418 | |||
419 | |||
420 | |||
421 | |||
422 | for (i = 0; i < PCI_BRIDGE_RESOURCE_NUM; i++) { |
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423 | child->resource[i] = &bridge->resource[PCI_BRIDGE_RESOURCES+i]; |
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424 | child->resource[i]->name = child->name; |
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425 | } |
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426 | bridge->subordinate = child; |
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427 | |||
428 | |||
429 | } |
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430 | |||
431 | |||
432 | { |
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433 | struct pci_bus *child; |
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434 | |||
435 | |||
436 | if (child) { |
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437 | // down_write(&pci_bus_sem); |
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438 | list_add_tail(&child->node, &parent->children); |
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439 | // up_write(&pci_bus_sem); |
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440 | } |
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441 | return child; |
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442 | } |
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443 | |||
444 | |||
445 | |||
446 | { |
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447 | struct pci_bus *parent = child->parent; |
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448 | |||
449 | |||
450 | we're going to re-assign all bus numbers. */ |
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451 | if (!pcibios_assign_all_busses()) |
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452 | return; |
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453 | |||
454 | |||
455 | parent->subordinate = max; |
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456 | pci_write_config_byte(parent->self, PCI_SUBORDINATE_BUS, max); |
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457 | parent = parent->parent; |
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458 | } |
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459 | } |
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460 | |||
461 | |||
462 | |||
463 | * If it's a bridge, configure it and scan the bus behind it. |
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464 | * For CardBus bridges, we don't scan behind as the devices will |
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465 | * be handled by the bridge driver itself. |
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466 | * |
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467 | * We need to process bridges in two passes -- first we scan those |
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468 | * already configured by the BIOS and after we are done with all of |
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469 | * them, we proceed to assigning numbers to the remaining buses in |
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470 | * order to avoid overlaps between old and new bus numbers. |
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471 | */ |
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472 | int pci_scan_bridge(struct pci_bus *bus, struct pci_dev *dev, int max, int pass) |
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473 | { |
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474 | struct pci_bus *child; |
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475 | int is_cardbus = (dev->hdr_type == PCI_HEADER_TYPE_CARDBUS); |
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476 | u32 buses, i, j = 0; |
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477 | u16 bctl; |
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478 | u8 primary, secondary, subordinate; |
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479 | int broken = 0; |
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480 | |||
481 | |||
482 | primary = buses & 0xFF; |
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483 | secondary = (buses >> 8) & 0xFF; |
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484 | subordinate = (buses >> 16) & 0xFF; |
||
485 | |||
486 | |||
487 | secondary, subordinate, pass); |
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488 | |||
489 | |||
490 | if (!pass && |
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491 | (primary != bus->number || secondary <= bus->number)) { |
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492 | dbgprintf("bus configuration invalid, reconfiguring\n"); |
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493 | broken = 1; |
||
494 | } |
||
495 | |||
496 | |||
497 | of bus errors (in some architectures) */ |
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498 | pci_read_config_word(dev, PCI_BRIDGE_CONTROL, &bctl); |
||
499 | pci_write_config_word(dev, PCI_BRIDGE_CONTROL, |
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500 | bctl & ~PCI_BRIDGE_CTL_MASTER_ABORT); |
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501 | |||
502 | |||
503 | !is_cardbus && !broken) { |
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504 | unsigned int cmax; |
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505 | /* |
||
506 | * Bus already configured by firmware, process it in the first |
||
507 | * pass and just note the configuration. |
||
508 | */ |
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509 | if (pass) |
||
510 | goto out; |
||
511 | |||
512 | |||
513 | * If we already got to this bus through a different bridge, |
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514 | * don't re-add it. This can happen with the i450NX chipset. |
||
515 | * |
||
516 | * However, we continue to descend down the hierarchy and |
||
517 | * scan remaining child buses. |
||
518 | */ |
||
519 | child = pci_find_bus(pci_domain_nr(bus), secondary); |
||
520 | if (!child) { |
||
521 | child = pci_add_new_bus(bus, dev, secondary); |
||
522 | if (!child) |
||
523 | goto out; |
||
524 | child->primary = primary; |
||
525 | child->subordinate = subordinate; |
||
526 | child->bridge_ctl = bctl; |
||
527 | } |
||
528 | |||
529 | |||
530 | if (cmax > max) |
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531 | max = cmax; |
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532 | if (child->subordinate > max) |
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533 | max = child->subordinate; |
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534 | } else { |
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535 | /* |
||
536 | * We need to assign a number to this bus which we always |
||
537 | * do in the second pass. |
||
538 | */ |
||
539 | if (!pass) { |
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540 | if (pcibios_assign_all_busses() || broken) |
||
541 | /* Temporarily disable forwarding of the |
||
542 | configuration cycles on all bridges in |
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543 | this bus segment to avoid possible |
||
544 | conflicts in the second pass between two |
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545 | bridges programmed with overlapping |
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546 | bus ranges. */ |
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547 | pci_write_config_dword(dev, PCI_PRIMARY_BUS, |
||
548 | buses & ~0xffffff); |
||
549 | goto out; |
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550 | } |
||
551 | |||
552 | |||
553 | pci_write_config_word(dev, PCI_STATUS, 0xffff); |
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554 | |||
555 | |||
556 | * This can happen when a bridge is hot-plugged */ |
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557 | if (pci_find_bus(pci_domain_nr(bus), max+1)) |
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558 | goto out; |
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559 | child = pci_add_new_bus(bus, dev, ++max); |
||
560 | buses = (buses & 0xff000000) |
||
561 | | ((unsigned int)(child->primary) << 0) |
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562 | | ((unsigned int)(child->secondary) << 8) |
||
563 | | ((unsigned int)(child->subordinate) << 16); |
||
564 | |||
565 | |||
566 | * yenta.c forces a secondary latency timer of 176. |
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567 | * Copy that behaviour here. |
||
568 | */ |
||
569 | if (is_cardbus) { |
||
570 | buses &= ~0xff000000; |
||
571 | buses |= CARDBUS_LATENCY_TIMER << 24; |
||
572 | } |
||
573 | |||
574 | |||
575 | * We need to blast all three values with a single write. |
||
576 | */ |
||
577 | pci_write_config_dword(dev, PCI_PRIMARY_BUS, buses); |
||
578 | |||
579 | |||
580 | child->bridge_ctl = bctl; |
||
581 | /* |
||
582 | * Adjust subordinate busnr in parent buses. |
||
583 | * We do this before scanning for children because |
||
584 | * some devices may not be detected if the bios |
||
585 | * was lazy. |
||
586 | */ |
||
587 | pci_fixup_parent_subordinate_busnr(child, max); |
||
588 | /* Now we can scan all subordinate buses... */ |
||
589 | max = pci_scan_child_bus(child); |
||
590 | /* |
||
591 | * now fix it up again since we have found |
||
592 | * the real value of max. |
||
593 | */ |
||
594 | pci_fixup_parent_subordinate_busnr(child, max); |
||
595 | } else { |
||
596 | /* |
||
597 | * For CardBus bridges, we leave 4 bus numbers |
||
598 | * as cards with a PCI-to-PCI bridge can be |
||
599 | * inserted later. |
||
600 | */ |
||
601 | for (i=0; i |
||
602 | struct pci_bus *parent = bus; |
||
603 | if (pci_find_bus(pci_domain_nr(bus), |
||
604 | max+i+1)) |
||
605 | break; |
||
606 | while (parent->parent) { |
||
607 | if ((!pcibios_assign_all_busses()) && |
||
608 | (parent->subordinate > max) && |
||
609 | (parent->subordinate <= max+i)) { |
||
610 | j = 1; |
||
611 | } |
||
612 | parent = parent->parent; |
||
613 | } |
||
614 | if (j) { |
||
615 | /* |
||
616 | * Often, there are two cardbus bridges |
||
617 | * -- try to leave one valid bus number |
||
618 | * for each one. |
||
619 | */ |
||
620 | i /= 2; |
||
621 | break; |
||
622 | } |
||
623 | } |
||
624 | max += i; |
||
625 | pci_fixup_parent_subordinate_busnr(child, max); |
||
626 | } |
||
627 | /* |
||
628 | * Set the subordinate bus number to its real value. |
||
629 | */ |
||
630 | child->subordinate = max; |
||
631 | pci_write_config_byte(dev, PCI_SUBORDINATE_BUS, max); |
||
632 | } |
||
633 | |||
634 | |||
635 | (is_cardbus ? "PCI CardBus %04x:%02x" : "PCI Bus %04x:%02x"), |
||
636 | pci_domain_nr(bus), child->number); |
||
637 | |||
638 | |||
639 | while (bus->parent) { |
||
640 | if ((child->subordinate > bus->subordinate) || |
||
641 | (child->number > bus->subordinate) || |
||
642 | (child->number < bus->number) || |
||
643 | (child->subordinate < bus->number)) { |
||
644 | dbgprintf("[bus %02x-%02x] %s " |
||
645 | "hidden behind%s bridge %s [bus %02x-%02x]\n", |
||
646 | child->number, child->subordinate, |
||
647 | (bus->number > child->subordinate && |
||
648 | bus->subordinate < child->number) ? |
||
649 | "wholly" : "partially", |
||
650 | bus->self->transparent ? " transparent" : "", |
||
651 | "FIX BRIDGE NAME", |
||
652 | bus->number, bus->subordinate); |
||
653 | } |
||
654 | bus = bus->parent; |
||
655 | } |
||
656 | |||
657 | |||
658 | pci_write_config_word(dev, PCI_BRIDGE_CONTROL, bctl); |
||
659 | |||
660 | |||
661 | } |
||
662 | |||
663 | |||
664 | { |
||
665 | int pos; |
||
666 | u16 reg16; |
||
667 | |||
668 | |||
669 | if (!pos) |
||
670 | return; |
||
671 | pdev->is_pcie = 1; |
||
672 | pdev->pcie_cap = pos; |
||
673 | pci_read_config_word(pdev, pos + PCI_EXP_FLAGS, ®16); |
||
674 | pdev->pcie_type = (reg16 & PCI_EXP_FLAGS_TYPE) >> 4; |
||
675 | } |
||
676 | |||
677 | |||
678 | { |
||
679 | int pos; |
||
680 | u16 reg16; |
||
681 | u32 reg32; |
||
682 | |||
683 | |||
684 | if (!pos) |
||
685 | return; |
||
686 | pci_read_config_word(pdev, pos + PCI_EXP_FLAGS, ®16); |
||
687 | if (!(reg16 & PCI_EXP_FLAGS_SLOT)) |
||
688 | return; |
||
689 | pci_read_config_dword(pdev, pos + PCI_EXP_SLTCAP, ®32); |
||
690 | if (reg32 & PCI_EXP_SLTCAP_HPC) |
||
691 | pdev->is_hotplug_bridge = 1; |
||
692 | } |
||
693 | |||
694 | |||
695 | * Read interrupt line and base address registers. |
||
696 | * The architecture-dependent code can tweak these, of course. |
||
697 | */ |
||
698 | static void pci_read_irq(struct pci_dev *dev) |
||
699 | { |
||
700 | unsigned char irq; |
||
701 | |||
702 | |||
703 | dev->pin = irq; |
||
704 | if (irq) |
||
705 | pci_read_config_byte(dev, PCI_INTERRUPT_LINE, &irq); |
||
706 | dev->irq = irq; |
||
707 | } |
||
708 | |||
709 | |||
710 | |||
711 | * pci_setup_device - fill in class and map information of a device |
||
1628 | serge | 712 | * @dev: the device structure to fill |
713 | * |
||
714 | * Initialize the device structure with information about the device's |
||
715 | * vendor,class,memory and IO-space addresses,IRQ lines etc. |
||
716 | * Called at initialisation of the PCI subsystem and by CardBus services. |
||
717 | * Returns 0 on success and negative if unknown type of device (not normal, |
||
718 | * bridge or CardBus). |
||
719 | */ |
||
720 | int pci_setup_device(struct pci_dev *dev) |
||
721 | { |
||
722 | u32 class; |
||
723 | u8 hdr_type; |
||
724 | struct pci_slot *slot; |
||
725 | int pos = 0; |
||
726 | |||
727 | |||
728 | return -EIO; |
||
729 | |||
730 | |||
731 | // dev->dev.parent = dev->bus->bridge; |
||
732 | // dev->dev.bus = &pci_bus_type; |
||
733 | dev->hdr_type = hdr_type & 0x7f; |
||
734 | dev->multifunction = !!(hdr_type & 0x80); |
||
735 | dev->error_state = pci_channel_io_normal; |
||
736 | set_pcie_port_type(dev); |
||
737 | |||
738 | |||
739 | if (PCI_SLOT(dev->devfn) == slot->number) |
||
740 | dev->slot = slot; |
||
741 | |||
742 | |||
743 | set this higher, assuming the system even supports it. */ |
||
744 | dev->dma_mask = 0xffffffff; |
||
745 | |||
746 | |||
747 | // dev->bus->number, PCI_SLOT(dev->devfn), |
||
748 | // PCI_FUNC(dev->devfn)); |
||
749 | |||
750 | |||
751 | dev->revision = class & 0xff; |
||
752 | class >>= 8; /* upper 3 bytes */ |
||
753 | dev->class = class; |
||
754 | class >>= 8; |
||
755 | |||
756 | |||
757 | dev->vendor, dev->device, class, dev->hdr_type); |
||
758 | |||
759 | |||
760 | dev->cfg_size = pci_cfg_space_size(dev); |
||
761 | |||
762 | |||
763 | dev->current_state = PCI_UNKNOWN; |
||
764 | |||
765 | |||
766 | // pci_fixup_device(pci_fixup_early, dev); |
||
767 | /* device class may be changed after fixup */ |
||
768 | class = dev->class >> 8; |
||
769 | |||
770 | |||
771 | case PCI_HEADER_TYPE_NORMAL: /* standard header */ |
||
772 | if (class == PCI_CLASS_BRIDGE_PCI) |
||
773 | goto bad; |
||
774 | pci_read_irq(dev); |
||
775 | pci_read_bases(dev, 6, PCI_ROM_ADDRESS); |
||
776 | pci_read_config_word(dev, PCI_SUBSYSTEM_VENDOR_ID, &dev->subsystem_vendor); |
||
777 | pci_read_config_word(dev, PCI_SUBSYSTEM_ID, &dev->subsystem_device); |
||
778 | |||
779 | |||
780 | * Do the ugly legacy mode stuff here rather than broken chip |
||
781 | * quirk code. Legacy mode ATA controllers have fixed |
||
782 | * addresses. These are not always echoed in BAR0-3, and |
||
783 | * BAR0-3 in a few cases contain junk! |
||
784 | */ |
||
785 | if (class == PCI_CLASS_STORAGE_IDE) { |
||
786 | u8 progif; |
||
787 | pci_read_config_byte(dev, PCI_CLASS_PROG, &progif); |
||
788 | if ((progif & 1) == 0) { |
||
789 | dev->resource[0].start = 0x1F0; |
||
790 | dev->resource[0].end = 0x1F7; |
||
791 | dev->resource[0].flags = LEGACY_IO_RESOURCE; |
||
792 | dev->resource[1].start = 0x3F6; |
||
793 | dev->resource[1].end = 0x3F6; |
||
794 | dev->resource[1].flags = LEGACY_IO_RESOURCE; |
||
795 | } |
||
796 | if ((progif & 4) == 0) { |
||
797 | dev->resource[2].start = 0x170; |
||
798 | dev->resource[2].end = 0x177; |
||
799 | dev->resource[2].flags = LEGACY_IO_RESOURCE; |
||
800 | dev->resource[3].start = 0x376; |
||
801 | dev->resource[3].end = 0x376; |
||
802 | dev->resource[3].flags = LEGACY_IO_RESOURCE; |
||
803 | } |
||
804 | } |
||
805 | break; |
||
806 | |||
807 | |||
808 | if (class != PCI_CLASS_BRIDGE_PCI) |
||
809 | goto bad; |
||
810 | /* The PCI-to-PCI bridge spec requires that subtractive |
||
811 | decoding (i.e. transparent) bridge must have programming |
||
812 | interface code of 0x01. */ |
||
813 | pci_read_irq(dev); |
||
814 | dev->transparent = ((dev->class & 0xff) == 1); |
||
815 | pci_read_bases(dev, 2, PCI_ROM_ADDRESS1); |
||
816 | set_pcie_hotplug_bridge(dev); |
||
817 | pos = pci_find_capability(dev, PCI_CAP_ID_SSVID); |
||
818 | if (pos) { |
||
819 | pci_read_config_word(dev, pos + PCI_SSVID_VENDOR_ID, &dev->subsystem_vendor); |
||
820 | pci_read_config_word(dev, pos + PCI_SSVID_DEVICE_ID, &dev->subsystem_device); |
||
821 | } |
||
822 | break; |
||
823 | |||
824 | |||
825 | if (class != PCI_CLASS_BRIDGE_CARDBUS) |
||
826 | goto bad; |
||
827 | pci_read_irq(dev); |
||
828 | pci_read_bases(dev, 1, 0); |
||
829 | pci_read_config_word(dev, PCI_CB_SUBSYSTEM_VENDOR_ID, &dev->subsystem_vendor); |
||
830 | pci_read_config_word(dev, PCI_CB_SUBSYSTEM_ID, &dev->subsystem_device); |
||
831 | break; |
||
832 | |||
833 | |||
834 | dbgprintf("unknown header type %02x, " |
||
835 | "ignoring device\n", dev->hdr_type); |
||
836 | return -EIO; |
||
837 | |||
838 | |||
839 | dbgprintf("ignoring class %02x (doesn't match header " |
||
840 | "type %02x)\n", class, dev->hdr_type); |
||
841 | dev->class = PCI_CLASS_NOT_DEFINED; |
||
842 | } |
||
843 | |||
844 | |||
845 | return 0; |
||
846 | } |
||
847 | |||
848 | |||
849 | |||
850 | |||
851 | { |
||
852 | struct pci_dev *dev; |
||
853 | |||
854 | |||
855 | if (!dev) |
||
856 | return NULL; |
||
857 | |||
858 | |||
859 | |||
860 | |||
861 | } |
||
862 | |||
863 | |||
864 | * Read the config data for a PCI device, sanity-check it |
||
865 | * and fill in the dev structure... |
||
866 | */ |
||
867 | static struct pci_dev *pci_scan_device(struct pci_bus *bus, int devfn) |
||
868 | { |
||
869 | struct pci_dev *dev; |
||
870 | u32 l; |
||
871 | int timeout = 10; |
||
872 | |||
873 | |||
874 | return NULL; |
||
875 | |||
876 | |||
877 | if (l == 0xffffffff || l == 0x00000000 || |
||
878 | l == 0x0000ffff || l == 0xffff0000) |
||
1633 | serge | 879 | return NULL; |
1628 | serge | 880 | |
881 | |||
882 | while (l == 0xffff0001) { |
||
883 | delay(timeout/10); |
||
884 | timeout *= 2; |
||
885 | if (pci_bus_read_config_dword(bus, devfn, PCI_VENDOR_ID, &l)) |
||
886 | return NULL; |
||
887 | /* Card hasn't responded in 60 seconds? Must be stuck. */ |
||
888 | if (timeout > 60 * 1000) { |
||
1631 | serge | 889 | printk(KERN_WARNING "pci %04x:%02x:%02x.%d: not " |
1628 | serge | 890 | "responding\n", pci_domain_nr(bus), |
891 | bus->number, PCI_SLOT(devfn), |
||
892 | PCI_FUNC(devfn)); |
||
893 | return NULL; |
||
894 | } |
||
895 | } |
||
896 | |||
897 | |||
898 | if (!dev) |
||
899 | return NULL; |
||
900 | |||
901 | |||
902 | dev->busnr = bus->number; |
||
1867 | serge | 903 | dev->devfn = devfn; |
1628 | serge | 904 | dev->vendor = l & 0xffff; |
905 | dev->device = (l >> 16) & 0xffff; |
||
906 | |||
907 | |||
908 | kfree(dev); |
||
909 | return NULL; |
||
910 | } |
||
911 | |||
912 | |||
913 | } |
||
914 | |||
915 | |||
1631 | serge | 916 | { |
917 | // device_initialize(&dev->dev); |
||
918 | // dev->dev.release = pci_release_dev; |
||
919 | // pci_dev_get(dev); |
||
920 | |||
1628 | serge | 921 | |
1631 | serge | 922 | // dev->dev.dma_parms = &dev->dma_parms; |
923 | // dev->dev.coherent_dma_mask = 0xffffffffull; |
||
924 | |||
925 | |||
926 | // pci_set_dma_seg_boundary(dev, 0xffffffff); |
||
927 | |||
928 | |||
929 | // pci_fixup_device(pci_fixup_header, dev); |
||
930 | |||
931 | |||
932 | dev->state_saved = false; |
||
933 | |||
934 | |||
935 | // pci_init_capabilities(dev); |
||
936 | |||
937 | |||
938 | * Add the device to our list of discovered devices |
||
939 | * and the bus list for fixup functions, etc. |
||
940 | */ |
||
941 | // down_write(&pci_bus_sem); |
||
942 | list_add_tail(&dev->bus_list, &bus->devices); |
||
943 | // up_write(&pci_bus_sem); |
||
944 | } |
||
945 | |||
946 | |||
1628 | serge | 947 | { |
948 | struct pci_dev *dev; |
||
949 | |||
950 | |||
951 | if (dev) { |
||
952 | // pci_dev_put(dev); |
||
953 | return dev; |
||
954 | } |
||
955 | |||
956 | |||
957 | if (!dev) |
||
958 | return NULL; |
||
959 | |||
960 | |||
961 | |||
962 | |||
963 | } |
||
964 | |||
965 | |||
966 | { |
||
967 | u16 cap; |
||
968 | unsigned pos, next_fn; |
||
969 | |||
970 | |||
971 | return 0; |
||
972 | |||
973 | |||
974 | if (!pos) |
||
975 | return 0; |
||
976 | pci_read_config_word(dev, pos + 4, &cap); |
||
977 | next_fn = cap >> 8; |
||
978 | if (next_fn <= fn) |
||
979 | return 0; |
||
980 | return next_fn; |
||
981 | } |
||
982 | |||
983 | |||
984 | { |
||
985 | return (fn + 1) % 8; |
||
986 | } |
||
987 | |||
988 | |||
989 | { |
||
990 | return 0; |
||
991 | } |
||
992 | |||
993 | |||
994 | { |
||
995 | struct pci_dev *parent = bus->self; |
||
996 | if (!parent || !pci_is_pcie(parent)) |
||
997 | return 0; |
||
998 | if (parent->pcie_type == PCI_EXP_TYPE_ROOT_PORT || |
||
999 | parent->pcie_type == PCI_EXP_TYPE_DOWNSTREAM) |
||
1000 | return 1; |
||
1001 | return 0; |
||
1002 | } |
||
1003 | |||
1004 | |||
1005 | * pci_scan_slot - scan a PCI slot on a bus for devices. |
||
1006 | * @bus: PCI bus to scan |
||
1007 | * @devfn: slot number to scan (must have zero function.) |
||
1008 | * |
||
1009 | * Scan a PCI slot on the specified PCI bus for devices, adding |
||
1010 | * discovered devices to the @bus->devices list. New devices |
||
1011 | * will not have is_added set. |
||
1012 | * |
||
1013 | * Returns the number of new devices found. |
||
1014 | */ |
||
1015 | int pci_scan_slot(struct pci_bus *bus, int devfn) |
||
1016 | { |
||
1017 | unsigned fn, nr = 0; |
||
1018 | struct pci_dev *dev; |
||
1019 | unsigned (*next_fn)(struct pci_dev *, unsigned) = no_next_fn; |
||
1020 | |||
1021 | |||
1022 | return 0; /* Already scanned the entire slot */ |
||
1023 | |||
1024 | |||
1025 | if (!dev) |
||
1026 | return 0; |
||
1027 | if (!dev->is_added) |
||
1028 | nr++; |
||
1029 | |||
1030 | |||
1031 | next_fn = next_ari_fn; |
||
1032 | else if (dev->multifunction) |
||
1033 | next_fn = next_trad_fn; |
||
1034 | |||
1035 | |||
1036 | dev = pci_scan_single_device(bus, devfn + fn); |
||
1037 | if (dev) { |
||
1038 | if (!dev->is_added) |
||
1039 | nr++; |
||
1040 | dev->multifunction = 1; |
||
1041 | } |
||
1042 | } |
||
1043 | |||
1044 | |||
1045 | // if (bus->self && nr) |
||
1631 | serge | 1046 | // pcie_aspm_init_link_state(bus->self); |
1047 | |||
1628 | serge | 1048 | |
1049 | } |
||
1050 | |||
1051 | |||
1052 | |||
1053 | { |
||
1054 | unsigned int devfn, pass, max = bus->secondary; |
||
1055 | struct pci_dev *dev; |
||
1056 | |||
1057 | |||
1058 | |||
1059 | |||
1060 | for (devfn = 0; devfn < 0x100; devfn += 8) |
||
1061 | pci_scan_slot(bus, devfn); |
||
1062 | |||
1063 | |||
1064 | max += pci_iov_bus_range(bus); |
||
1065 | |||
1066 | |||
1067 | * After performing arch-dependent fixup of the bus, look behind |
||
1068 | * all PCI-to-PCI bridges on this bus. |
||
1069 | */ |
||
1070 | if (!bus->is_added) { |
||
1071 | dbgprintf("fixups for bus\n"); |
||
1072 | // pcibios_fixup_bus(bus); |
||
1631 | serge | 1073 | if (pci_is_root_bus(bus)) |
1628 | serge | 1074 | bus->is_added = 1; |
1075 | } |
||
1076 | |||
1077 | |||
1078 | list_for_each_entry(dev, &bus->devices, bus_list) { |
||
1079 | if (dev->hdr_type == PCI_HEADER_TYPE_BRIDGE || |
||
1080 | dev->hdr_type == PCI_HEADER_TYPE_CARDBUS) |
||
1081 | max = pci_scan_bridge(bus, dev, max, pass); |
||
1082 | } |
||
1083 | |||
1084 | |||
1085 | * We've scanned the bus and so we know all about what's on |
||
1086 | * the other side of any bridges that may be on this bus plus |
||
1087 | * any devices. |
||
1088 | * |
||
1089 | * Return how far we've got finding sub-buses. |
||
1090 | */ |
||
1091 | dbgprintf("bus scan returning with max=%02x\n", max); |
||
1092 | return max; |
||
1093 | } |
||
1094 | |||
1095 | |||
1096 | * pci_cfg_space_size - get the configuration space size of the PCI device. |
||
1097 | * @dev: PCI device |
||
1098 | * |
||
1099 | * Regular PCI devices have 256 bytes, but PCI-X 2 and PCI Express devices |
||
1100 | * have 4096 bytes. Even if the device is capable, that doesn't mean we can |
||
1101 | * access it. Maybe we don't have a way to generate extended config space |
||
1102 | * accesses, or the device is behind a reverse Express bridge. So we try |
||
1103 | * reading the dword at 0x100 which must either be 0 or a valid extended |
||
1104 | * capability header. |
||
1105 | */ |
||
1106 | int pci_cfg_space_size_ext(struct pci_dev *dev) |
||
1107 | { |
||
1108 | u32 status; |
||
1109 | int pos = PCI_CFG_SPACE_SIZE; |
||
1110 | |||
1111 | |||
1112 | goto fail; |
||
1113 | if (status == 0xffffffff) |
||
1114 | goto fail; |
||
1115 | |||
1116 | |||
1117 | |||
1118 | |||
1119 | return PCI_CFG_SPACE_SIZE; |
||
1120 | } |
||
1121 | |||
1122 | |||
1123 | { |
||
1124 | int pos; |
||
1125 | u32 status; |
||
1126 | u16 class; |
||
1127 | |||
1128 | |||
1129 | if (class == PCI_CLASS_BRIDGE_HOST) |
||
1130 | return pci_cfg_space_size_ext(dev); |
||
1131 | |||
1132 | |||
1133 | if (!pos) { |
||
1134 | pos = pci_find_capability(dev, PCI_CAP_ID_PCIX); |
||
1135 | if (!pos) |
||
1136 | goto fail; |
||
1137 | |||
1138 | |||
1139 | if (!(status & (PCI_X_STATUS_266MHZ | PCI_X_STATUS_533MHZ))) |
||
1140 | goto fail; |
||
1141 | } |
||
1142 | |||
1143 | |||
1144 | |||
1145 | |||
1146 | return PCI_CFG_SPACE_SIZE; |
||
1147 | } |
||
1148 | |||
1149 | |||
1150 | |||
1631 | serge | 1151 | |
1152 | { |
||
1153 | int error; |
||
1154 | struct pci_bus *b, *b2; |
||
1155 | |||
1156 | |||
1157 | if (!b) |
||
1158 | return NULL; |
||
1159 | |||
1160 | |||
1161 | b->ops = ops; |
||
1162 | |||
1163 | |||
1164 | if (b2) { |
||
1165 | /* If we already got to this bus through a different bridge, ignore it */ |
||
1166 | dbgprintf("bus already known\n"); |
||
1167 | goto err_out; |
||
1168 | } |
||
1169 | |||
1170 | |||
1171 | list_add_tail(&b->node, &pci_root_buses); |
||
1172 | // up_write(&pci_bus_sem); |
||
1173 | |||
1174 | |||
1175 | b->resource[0] = &ioport_resource; |
||
1176 | b->resource[1] = &iomem_resource; |
||
1177 | |||
1178 | |||
1179 | |||
1180 | |||
1181 | kfree(b); |
||
1182 | return NULL; |
||
1183 | }>>=>>>>=>><>><>><>><>=>>>>><>>>>><>><>><> |
||
1184 |