WebSVN – Kolibri OS – Blame – /drivers/audio/intel_hda/intel_hda.asm

Rev	Author	Line No.	Line
3083	leency	1	;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
		2	;; ;;
		3	;; Copyright (C) KolibriOS team 2004-2012. All rights reserved. ;;
		4	;; Distributed under terms of the GNU General Public License ;;
		5	;; ;;
		6	;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
		7
		8	format MS COFF
		9
		10	DEBUG equ 1
		11	FDEBUG equ 1
		12	DEBUG_IRQ equ 0
		13
		14	USE_SINGLE_MODE equ 0 ; 1 = Single mode; 0 = Normal mode.
		15
		16	TEST_VERSION_NUMBER equ '018b'
		17
		18	;Asper+ [
		19	SDO_TAG equ 1 ;Asper: Output stream tag id (any number except 0)
		20	SDO_IDX equ 4 ;Asper: Output stream index
		21	;According to "Intel� I/O Controller Hub 6 (ICH6) High Definition Audio / AC �97 Programmer�s Reference Manual (PRM) May 2005 Document"
		22	;and "Intel� I/O Controller Hub 6 (ICH6) Family Datasheet" SDO0=4,
		23	;but according to "High Definition Audio Specification Revision 1.0a June 17, 2010" SDO0 depends on the number of SDIs.
		24
		25	SDO_INT equ 1 shl SDO_IDX ;Asper: Output stream interrupt (must be power of 2)
		26	SDO_OFS equ 0x80+(SDO_IDX*0x20) ;Asper: Output stream offset
		27	;Asper+ ]
		28
3085	leency	29	include 'PROC32.INC'
		30	include 'IMPORTS.INC'
		31	include 'CODEC_H.INC'
3083	leency	32
		33
		34	CURRENT_API equ 0x0100 ;1.00
		35	COMPATIBLE_API equ 0x0101 ;1.01
		36	API_VERSION equ (COMPATIBLE_API shl 16) or CURRENT_API
		37
		38	IRQ_REMAP equ 0
		39	IRQ_LINE equ 0
		40
		41	CPU_FREQ equ 2600d
		42
		43	; Vendors
		44	VID_INTEL equ 0x8086
		45	VID_NVIDIA equ 0x10DE
		46	VID_ATI equ 0x1002
		47	VID_AMD equ 0x1022
3170	hidnplayr	48	VID_VIA equ 0x1106
3083	leency	49	VID_SIS equ 0x1039
		50	VID_ULI equ 0x10B9
		51	VID_CREATIVE equ 0x1102
		52	VID_TERA equ 0x6549
		53	VID_RDC equ 0x17F3
		54	VID_VMWARE equ 0x15AD
		55
		56	; Devices
		57	; Intel
		58	CTRL_INTEL_SCH2 equ 0x080a
		59	CTRL_INTEL_HPT equ 0x0c0c
		60	CTRL_INTEL_CPT equ 0x1c20
		61	CTRL_INTEL_PGB equ 0x1d20
		62	CTRL_INTEL_PPT1 equ 0x1e20
		63	CTRL_INTEL_82801F equ 0x2668
		64	CTRL_INTEL_63XXESB equ 0x269a
		65	CTRL_INTEL_82801G equ 0x27d8
		66	CTRL_INTEL_82801H equ 0x284b
		67	CTRL_INTEL_82801_UNK1 equ 0x2911
		68	CTRL_INTEL_82801I equ 0x293e
		69	CTRL_INTEL_82801_UNK2 equ 0x293f
		70	CTRL_INTEL_82801JI equ 0x3a3e
		71	CTRL_INTEL_82801JD equ 0x3a6e
		72	CTRL_INTEL_PCH equ 0x3b56
		73	CTRL_INTEL_PCH2 equ 0x3b57
		74	CTRL_INTEL_SCH equ 0x811b
		75	CTRL_INTEL_LPT equ 0x8c20
		76	; Nvidia
		77	CTRL_NVIDIA_MCP51 equ 0x026c
		78	CTRL_NVIDIA_MCP55 equ 0x0371
		79	CTRL_NVIDIA_MCP61_1 equ 0x03e4
		80	CTRL_NVIDIA_MCP61_2 equ 0x03f0
		81	CTRL_NVIDIA_MCP65_1 equ 0x044a
		82	CTRL_NVIDIA_MCP65_2 equ 0x044b
		83	CTRL_NVIDIA_MCP67_1 equ 0x055c
		84	CTRL_NVIDIA_MCP67_2 equ 0x055d
		85	CTRL_NVIDIA_MCP78_1 equ 0x0774
		86	CTRL_NVIDIA_MCP78_2 equ 0x0775
		87	CTRL_NVIDIA_MCP78_3 equ 0x0776
		88	CTRL_NVIDIA_MCP78_4 equ 0x0777
		89	CTRL_NVIDIA_MCP73_1 equ 0x07fc
		90	CTRL_NVIDIA_MCP73_2 equ 0x07fd
		91	CTRL_NVIDIA_MCP79_1 equ 0x0ac0
		92	CTRL_NVIDIA_MCP79_2 equ 0x0ac1
		93	CTRL_NVIDIA_MCP79_3 equ 0x0ac2
		94	CTRL_NVIDIA_MCP79_4 equ 0x0ac3
		95	CTRL_NVIDIA_0BE2 equ 0x0be2
		96	CTRL_NVIDIA_0BE3 equ 0x0be3
		97	CTRL_NVIDIA_0BE4 equ 0x0be4
		98	CTRL_NVIDIA_GT100 equ 0x0be5
		99	CTRL_NVIDIA_GT106 equ 0x0be9
		100	CTRL_NVIDIA_GT108 equ 0x0bea
		101	CTRL_NVIDIA_GT104 equ 0x0beb
		102	CTRL_NVIDIA_GT116 equ 0x0bee
		103	CTRL_NVIDIA_MCP89_1 equ 0x0d94
		104	CTRL_NVIDIA_MCP89_2 equ 0x0d95
		105	CTRL_NVIDIA_MCP89_3 equ 0x0d96
		106	CTRL_NVIDIA_MCP89_4 equ 0x0d97
		107	CTRL_NVIDIA_GF119 equ 0x0e08
		108	CTRL_NVIDIA_GF110_1 equ 0x0e09
		109	CTRL_NVIDIA_GF110_2 equ 0x0e0c
		110	; ATI
		111	CTRL_ATI_SB450 equ 0x437b
		112	CTRL_ATI_SB600 equ 0x4383
		113	; ATI HDMI
		114	CTRL_ATI_RS600 equ 0x793b
		115	CTRL_ATI_RS690 equ 0x7919
		116	CTRL_ATI_RS780 equ 0x960f
		117	CTRL_ATI_RS_UNK1 equ 0x970f
		118	CTRL_ATI_R600 equ 0xaa00
		119	CTRL_ATI_RV630 equ 0xaa08
		120	CTRL_ATI_RV610 equ 0xaa10
		121	CTRL_ATI_RV670 equ 0xaa18
		122	CTRL_ATI_RV635 equ 0xaa20
		123	CTRL_ATI_RV620 equ 0xaa28
		124	CTRL_ATI_RV770 equ 0xaa30
		125	CTRL_ATI_RV730 equ 0xaa38
		126	CTRL_ATI_RV710 equ 0xaa40
		127	CTRL_ATI_RV740 equ 0xaa48
		128	; AMD
		129	CTRL_AMD_HUDSON equ 0x780d
		130	; VIA
		131	CTRL_VIA_VT82XX equ 0x3288
		132	CTRL_VIA_VT61XX equ 0x9140
		133	CTRL_VIA_VT71XX equ 0x9170
		134	; SiS
		135	CTRL_SIS_966 equ 0x7502
		136	; ULI
		137	CTRL_ULI_M5461 equ 0x5461
		138	; Creative
		139	CTRL_CREATIVE_CA0110_IBG equ 0x0009
		140	CTRL_CREATIVE_SOUND_CORE3D_1 equ 0x0010
		141	CTRL_CREATIVE_SOUND_CORE3D_2 equ 0x0012
		142	; Teradici
		143	CTRL_TERA_UNK1 equ 0x1200
		144	; RDC Semiconductor
		145	CTRL_RDC_R3010 equ 0x3010
		146	;VMware
		147	CTRL_VMWARE_UNK1 equ 0x1977
		148
		149
		150	; driver types
		151	AZX_DRIVER_ICH equ 0
		152	AZX_DRIVER_PCH equ 1
		153	AZX_DRIVER_SCH equ 2
		154	AZX_DRIVER_ATI equ 3
		155	AZX_DRIVER_ATIHDMI equ 4
		156	AZX_DRIVER_VIA equ 5
		157	AZX_DRIVER_SIS equ 6
		158	AZX_DRIVER_ULI equ 7
		159	AZX_DRIVER_NVIDIA equ 8
		160	AZX_DRIVER_TERA equ 9
		161	AZX_DRIVER_CTX equ 10
		162	AZX_DRIVER_GENERIC equ 11
		163	AZX_NUM_DRIVERS equ 12
		164
		165
		166	; registers
		167
		168	ICH6_REG_GCAP equ 0x00
		169	ICH6_REG_VMIN equ 0x02
		170	ICH6_REG_VMAJ equ 0x03
		171	ICH6_REG_OUTPAY equ 0x04
		172	ICH6_REG_INPAY equ 0x06
		173	ICH6_REG_GCTL equ 0x08
		174	ICH6_GCTL_RESET equ (1 shl 0) ; controller reset
		175	ICH6_GCTL_FCNTRL equ (1 shl 1) ; flush control
		176	ICH6_GCTL_UNSOL equ (1 shl 8) ; accept unsol. response enable
		177	ICH6_REG_WAKEEN equ 0x0c
		178	ICH6_REG_STATESTS equ 0x0e
		179	ICH6_REG_GSTS equ 0x10
		180	ICH6_GSTS_FSTS equ (1 shl 1) ; flush status
		181	ICH6_REG_INTCTL equ 0x20
		182	ICH6_REG_INTSTS equ 0x24
		183	ICH6_REG_WALLCLK equ 0x30 ; 24Mhz source
		184	ICH6_REG_OLD_SSYNC equ 0x34 ; SSYNC for old ICH
		185	ICH6_REG_SSYNC equ 0x38
		186	ICH6_REG_CORBLBASE equ 0x40
		187	ICH6_REG_CORBUBASE equ 0x44
		188	ICH6_REG_CORBWP equ 0x48
		189	ICH6_REG_CORBRP equ 0x4A
		190	ICH6_CORBRP_RST equ (1 shl 15) ; read pointer reset
		191	ICH6_REG_CORBCTL equ 0x4c
		192	ICH6_CORBCTL_RUN equ (1 shl 1) ; enable DMA
		193	ICH6_CORBCTL_CMEIE equ (1 shl 0) ; enable memory error irq
		194	ICH6_REG_CORBSTS equ 0x4d
		195	ICH6_CORBSTS_CMEI equ (1 shl 0) ; memory error indication
		196	ICH6_REG_CORBSIZE equ 0x4e
		197
		198	ICH6_REG_RIRBLBASE equ 0x50
		199	ICH6_REG_RIRBUBASE equ 0x54
		200	ICH6_REG_RIRBWP equ 0x58
		201	ICH6_RIRBWP_RST equ (1 shl 15) ; write pointer reset
		202	ICH6_REG_RINTCNT equ 0x5a
		203	ICH6_REG_RIRBCTL equ 0x5c
		204	ICH6_RBCTL_IRQ_EN equ (1 shl 0) ; enable IRQ
		205	ICH6_RBCTL_DMA_EN equ (1 shl 1) ; enable DMA
		206	ICH6_RBCTL_OVERRUN_EN equ (1 shl 2) ; enable overrun irq
		207	ICH6_REG_RIRBSTS equ 0x5d
		208	ICH6_RBSTS_IRQ equ (1 shl 0) ; response irq
		209	ICH6_RBSTS_OVERRUN equ (1 shl 2) ; overrun irq
		210	ICH6_REG_RIRBSIZE equ 0x5e
		211
		212	ICH6_REG_IC equ 0x60
		213	ICH6_REG_IR equ 0x64
		214	ICH6_REG_IRS equ 0x68
		215	ICH6_IRS_VALID equ 2
		216	ICH6_IRS_BUSY equ 1
		217
		218	ICH6_REG_DPLBASE equ 0x70
		219	ICH6_REG_DPUBASE equ 0x74
		220	ICH6_DPLBASE_ENABLE equ 1 ; Enable position buffer
		221
		222	; SD offset: SDI0=0x80, SDI1=0xa0, ... SDO3=0x160 */
		223	SDI0_SD_OFFSET equ 0x80
		224	SDI1_SD_OFFSET equ 0xA0
		225	SDI2_SD_OFFSET equ 0xC0
		226	SDI3_SD_OFFSET equ 0xE0
		227	SDO0_SD_OFFSET equ 0x100
		228	SDO1_SD_OFFSET equ 0x120
		229	SDO2_SD_OFFSET equ 0X140
		230	SDO3_SD_OFFSET equ 0x160
		231
		232	; stream register offsets from stream base
		233	ICH6_REG_SD_CTL equ 0x00
		234	ICH6_REG_SD_STS equ 0x03
		235	ICH6_REG_SD_LPIB equ 0x04
		236	ICH6_REG_SD_CBL equ 0x08
		237	ICH6_REG_SD_LVI equ 0x0c
		238	ICH6_REG_SD_FIFOW equ 0x0e
		239	ICH6_REG_SD_FIFOSIZE equ 0x10
		240	ICH6_REG_SD_FORMAT equ 0x12
		241	ICH6_REG_SD_BDLPL equ 0x18
		242	ICH6_REG_SD_BDLPU equ 0x1c
		243
		244	; PCI space
		245	ICH6_PCIREG_TCSEL equ 0x44
		246
		247	; other constants
		248	ICH6_RIRB_EX_UNSOL_EV equ (1 shl 4)
		249
		250	; max number of SDs
		251	MAX_ICH6_DEV equ 8
		252	; max number of fragments - we may use more if allocating more pages for BDL
		253	AZX_MAX_FRAG equ (4096 / (MAX_ICH6_DEV * 16))
		254	; max buffer size - no h/w limit, you can increase as you like
		255	AZX_MAX_BUF_SIZE equ (102410241024)
		256	; max number of PCM devices per card
		257	AZX_MAX_PCMS equ 8
		258
		259	; RIRB int mask: overrun[2], response[0]
		260	RIRB_INT_RESPONSE equ 0x01
		261	RIRB_INT_OVERRUN equ 0x04
		262	RIRB_INT_MASK equ 0x05
		263
		264	; STATESTS int mask: SD2,SD1,SD0
		265	STATESTS_INT_MASK equ 0x07
		266	AZX_MAX_CODECS equ 4
		267
		268	; SD_CTL bits
		269	SD_CTL_STREAM_RESET equ 0x01 ; stream reset bit
		270	SD_CTL_DMA_START equ 0x02 ; stream DMA start bit
		271	SD_CTL_STREAM_TAG_MASK equ (0xf shl 20)
		272	SD_CTL_STREAM_TAG_SHIFT equ 20
		273
		274	; SD_CTL and SD_STS
		275	SD_INT_DESC_ERR equ 0x10 ; descriptor error interrupt
		276	SD_INT_FIFO_ERR equ 0x08 ; FIFO error interrupt
		277	SD_INT_COMPLETE equ 0x04 ; completion interrupt
		278	SD_INT_MASK equ (SD_INT_DESC_ERR or SD_INT_FIFO_ERR or SD_INT_COMPLETE)
		279
		280	; SD_STS
		281	SD_STS_FIFO_READY equ 0x20 ; FIFO ready
		282
		283	; INTCTL and INTSTS
		284	ICH6_INT_ALL_STREAM equ 0xff ; all stream interrupts
		285	ICH6_INT_CTRL_EN equ 0x40000000 ; controller interrupt enable bit
		286	ICH6_INT_GLOBAL_EN equ 0x80000000 ; global interrupt enable bit
		287
		288	; GCTL reset bit
		289	ICH6_GCTL_RESET equ 1
		290
		291	; CORB/RIRB control, read/write pointer
		292	ICH6_RBCTL_DMA_EN equ 0x02 ; enable DMA
		293	ICH6_RBCTL_IRQ_EN equ 0x01 ; enable IRQ
		294	ICH6_RBRWP_CLR equ 0x8000 ; read/write pointer clear
		295	; below are so far hardcoded - should read registers in future
		296	ICH6_MAX_CORB_ENTRIES equ 256
		297	ICH6_MAX_RIRB_ENTRIES equ 256
		298
		299	; position fix mode
		300	POS_FIX_AUTO equ 0
		301	POS_FIX_LPIB equ 1
		302	POS_FIX_POSBUF equ 2
		303	POS_FIX_VIACOMBO equ 4
		304	POS_FIX_COMBO equ 8
		305
		306	; Defines for ATI HD Audio support in SB450 south bridge
		307	ATI_SB450_HDAUDIO_MISC_CNTR2_ADDR equ 0x42
		308	ATI_SB450_HDAUDIO_ENABLE_SNOOP equ 0x02
		309
		310	; Defines for Nvidia HDA support
		311	NVIDIA_HDA_TRANSREG_ADDR equ 0x4e
		312	NVIDIA_HDA_ENABLE_COHBITS equ 0x0f
		313	NVIDIA_HDA_ISTRM_COH equ 0x4d
		314	NVIDIA_HDA_OSTRM_COH equ 0x4c
		315	NVIDIA_HDA_ENABLE_COHBIT equ 0x01
		316
		317	; Defines for Intel SCH HDA snoop control
		318	INTEL_SCH_HDA_DEVC equ 0x78
		319	INTEL_SCH_HDA_DEVC_NOSNOOP equ (0x1 shl 11)
		320
		321	; Define IN stream 0 FIFO size offset in VIA controller
		322	VIA_IN_STREAM0_FIFO_SIZE_OFFSET equ 0x90
		323	; Define VIA HD Audio Device ID
		324	VIA_HDAC_DEVICE_ID equ 0x3288
		325
		326	; HD Audio class code
		327	PCI_CLASS_MULTIMEDIA_HD_AUDIO equ 0x0403
		328
		329
		330	SRV_GETVERSION equ 0
		331	DEV_PLAY equ 1
		332	DEV_STOP equ 2
		333	DEV_CALLBACK equ 3
		334	DEV_SET_BUFF equ 4
		335	DEV_NOTIFY equ 5
		336	DEV_SET_MASTERVOL equ 6
		337	DEV_GET_MASTERVOL equ 7
		338	DEV_GET_INFO equ 8
		339	DEV_GET_POS equ 9
		340	DEV_SET_CHANNEL_VOLUME equ 10
		341	DEV_GET_CHANNEL_VOLUME equ 11
		342	;Asper: Non standard system service. For the tests only! [
		343	DEV_EXEC_CODEC_CMD equ 100
		344	;Asper: Non standard system service. For the tests only! ]
		345
		346	struc AC_CNTRL ;AC controller base class
		347	{ .bus dd ?
		348	.devfn dd ?
		349
		350	.vendor dw ?
		351	.dev_id dw ?
		352	.pci_cmd dd ?
		353	.pci_stat dd ?
		354
		355	.ctrl_io_base dd ?
		356	.ctrl_mem_base dd ?
		357	.cfg_reg dd ?
		358	.int_line dd ?
		359
		360	.vendor_ids dd ? ;vendor id string
		361	.ctrl_ids dd ? ;hub id string
		362
		363	.buffer dd ?
		364
		365	.notify_pos dd ?
		366	.notify_task dd ?
		367
		368	.lvi_reg dd ?
		369	.civ_val dd 1
		370	.user_callback dd ?
		371
		372	.ctrl_read8 dd ?
		373	.ctrl_read16 dd ?
		374	.ctrl_read32 dd ?
		375
		376	.ctrl_write8 dd ?
		377	.ctrl_write16 dd ?
		378	.ctrl_write32 dd ?
		379
		380	;Asper+ [
		381	.codec_mask dd ?
		382	.rb dd ?
		383	.rirb_rp dw 0
		384	.rirb_wp dw 0
		385	.corb_rp dw 0
		386	.corb_wp dw 0
		387	.rirb_cmd dd 0
		388	.rirb_res dd 0
		389	.rirb_error dd 0
		390	.response_reset dd 0
		391	.polling_mode db 0
		392	.poll_count db 0
		393	.posbuf dd ?
		394	.start_wallclk dd ? ; start + minimum wallclk
		395	.period_wallclk dd ? ; wallclk for period
		396	.position_fix db ?
		397	;Asper+ ]
		398	}
		399
		400	struc CODEC ;Audio Chip base class
		401	{
		402	;Asper+ [
		403	.addr dd ? ; codec slot index (codec address)
		404	.afg dd ? ; AFG node id
		405	.mfg dd ? ; MFG node id
		406
		407	.function_id dd ?
		408	.subsystem_id dd ?
		409	.revision_id dd ?
		410	.chip_id dw ?
		411	.vendor_id dw ?
		412
		413	; widget capabilities cache
		414	.num_nodes dw ?
		415	.start_nid dw ?
		416	.wcaps dd ?
		417
		418	.init_pins dd ? ; initial (BIOS) pin configurations
		419	.num_pins dd ? ;Asper + : word is enough, but for align...
		420	.beeper_nid dw ?
		421	.pad dw ?
		422	;Asper+ ]
		423
		424	.ac_vendor_ids dd ? ;ac vendor id string
		425	.chip_ids dd ? ;chip model string
		426	}
		427
		428	struc CTRL_INFO
		429	{ .pci_cmd dd ?
		430	.irq dd ?
		431	.glob_cntrl dd ?
		432	.glob_sta dd ?
		433	.codec_io_base dd ?
		434	.ctrl_io_base dd ?
		435	.codec_mem_base dd ?
		436	.ctrl_mem_base dd ?
		437	.codec_id dd ?
		438	}
		439
		440	struc IOCTL
		441	{ .handle dd ?
		442	.io_code dd ?
		443	.input dd ?
		444	.inp_size dd ?
		445	.output dd ?
		446	.out_size dd ?
		447	}
		448
		449	virtual at 0
		450	IOCTL IOCTL
		451	end virtual
		452
		453	EVENT_NOTIFY equ 0x00000200
		454
		455	public START
		456	public service_proc
		457	public version
		458
		459	section '.flat' code readable align 16
		460
		461	proc START stdcall, state:dword
		462
		463	cmp [state], 1
		464	jne .stop
		465
		466	if DEBUG
		467	mov esi, msgTV
		468	call SysMsgBoardStr
		469
		470	mov esi, msgInit
		471	call SysMsgBoardStr
		472	end if
		473
		474	call detect_controller
		475	test eax, eax
		476	jz .fail
		477
		478	mov esi,[ctrl.vendor_ids]
		479	call SysMsgBoardStr
		480	mov esi, [ctrl.ctrl_ids]
		481	call SysMsgBoardStr
		482
		483	call init_controller
		484	test eax, eax
		485	jz .fail
		486
		487	;Asper This part is from "azx_create" proc. [
		488	;(...)
		489	mov [ctrl.position_fix], POS_FIX_LPIB
		490	cmp [driver_type], AZX_DRIVER_VIA
		491	je .set_via_patch
		492	cmp [driver_type], AZX_DRIVER_ATI
		493	jne .no_via_patch
		494	.set_via_patch:
		495	or [ctrl.position_fix], POS_FIX_VIACOMBO
		496	.no_via_patch:
		497	; codec detection
		498	mov eax, [ctrl.codec_mask]
		499	test eax, eax
		500	jnz @f
		501	if DEBUG
		502	mov esi, msgNoCodecsFound
		503	jmp .fail_msg
		504	else
		505	jmp .fail
		506	end if
		507	@@:
		508	;Asper ]
		509
		510	mov esi, msgPrimBuff
		511	call SysMsgBoardStr
		512	call create_primary_buff
		513	mov esi, msgDone
		514	call SysMsgBoardStr
		515
		516	if IRQ_REMAP
		517	pushf
		518	cli
		519
		520	mov ebx, [ctrl.int_line]
		521	in al, 0xA1
		522	mov ah, al
		523	in al, 0x21
		524	test ebx, ebx
		525	jz .skip
		526	bts ax, bx ;mask old line
		527	.skip
		528	bts ax, IRQ_LINE ;mask new ine
		529	out 0x21, al
		530	mov al, ah
		531	out 0xA1, al
		532	;remap IRQ
		533	stdcall PciWrite8, 0, 0xF8, 0x61, IRQ_LINE
		534
		535	mov dx, 0x4d0 ;8259 ELCR1
		536	in al, dx
		537	bts ax, IRQ_LINE
		538	out dx, al ;set level-triggered mode
		539	mov [ctrl.int_line], IRQ_LINE
		540	popf
		541	mov esi, msgRemap
		542	call SysMsgBoardStr
		543	end if
		544
		545	mov ebx, [ctrl.int_line]
		546	stdcall AttachIntHandler, ebx, hda_irq, dword 0
		547
		548	;Asper This part is from "azx_probe" proc. [
		549	call azx_codec_create
		550	cmp eax, 0
		551	jl .fail
		552
		553	call azx_codec_configure
		554	cmp eax, 0
		555	jl .fail
		556	;] Asper
		557
		558	; create PCM streams
		559	;Asper+ [
		560	mov eax, [spec.dac_node]
		561	if DEBUG
		562	push eax esi
		563	mov esi, msgVal
		564	call SysMsgBoardStr
		565	stdcall fdword2str, 3
		566	call SysMsgBoardStr
		567	pop esi eax
		568	end if
		569
		570	test eax, eax
		571	jz .fail
		572	mov ebx, [spec.dac_node+4]
		573	if DEBUG
		574	push eax esi
		575	mov esi, msgVal
		576	call SysMsgBoardStr
		577	mov eax, [spec.dac_node+4]
		578	stdcall fdword2str, 3
		579	call SysMsgBoardStr
		580	pop esi eax
		581	end if
		582
		583	test ebx, ebx
		584	jz @f
		585	cmp eax, ebx
		586	je @f
		587	stdcall hda_codec_setup_stream, ebx, SDO_TAG, 0, 0x11 ; Left & Right channels (Front panel)
		588	@@:
		589	stdcall hda_codec_setup_stream, eax, SDO_TAG, 0, 0x11 ; Left & Right channels (Back panel)
		590	;Asper+ ]
		591
		592	if USE_SINGLE_MODE
		593	mov esi, msgSingleMode
		594	call SysMsgBoardStr
		595	else
		596	mov esi, msgNormalMode
		597	call SysMsgBoardStr
		598	end if
		599
		600
		601	.reg:
		602	stdcall RegService, sz_sound_srv, service_proc
		603	ret
		604	.fail:
		605	if DEBUG
		606	mov esi, msgFail
		607	call SysMsgBoardStr
		608	end if
		609	xor eax, eax
		610	ret
		611	.fail_msg:
		612	call SysMsgBoardStr
		613	xor eax, eax
		614	ret
		615	.stop:
		616	call stop
		617	xor eax, eax
		618	ret
		619	endp
		620
		621	handle equ IOCTL.handle
		622	io_code equ IOCTL.io_code
		623	input equ IOCTL.input
		624	inp_size equ IOCTL.inp_size
		625	output equ IOCTL.output
		626	out_size equ IOCTL.out_size
		627
		628	align 4
		629	proc service_proc stdcall, ioctl:dword
		630	mov edi, [ioctl]
		631	mov eax, [edi+io_code]
		632
		633	cmp eax, SRV_GETVERSION
		634	jne @F
		635
		636	mov eax, [edi+output]
		637	cmp [edi+out_size], 4
		638	jne .fail
		639
		640	mov [eax], dword API_VERSION
		641	xor eax, eax
		642	ret
		643	@@:
		644	cmp eax, DEV_PLAY
		645	jne @F
		646	if DEBUG
		647	mov esi, msgPlay
		648	call SysMsgBoardStr
		649	end if
		650	call play
		651	xor eax, eax
		652	ret
		653	@@:
		654	cmp eax, DEV_STOP
		655	jne @F
		656	if DEBUG
		657	mov esi, msgStop
		658	call SysMsgBoardStr
		659	end if
		660	call stop
		661	xor eax, eax
		662	ret
		663	@@:
		664	cmp eax, DEV_CALLBACK
		665	jne @F
		666	mov ebx, [edi+input]
		667	stdcall set_callback, [ebx]
		668	xor eax, eax
		669	ret
		670	@@:
		671	cmp eax, DEV_SET_MASTERVOL
		672	jne @F
		673	mov eax, [edi+input]
		674	mov eax, [eax]
		675	call set_master_vol
		676	xor eax, eax
		677	ret
		678	@@:
		679	cmp eax, DEV_GET_MASTERVOL
		680	jne @F
		681	mov ebx, [edi+output]
		682	stdcall get_master_vol, ebx
		683	xor eax, eax
		684	ret
		685	;@@:
		686	; cmp eax, DEV_GET_INFO
		687	; jne @F
		688	; mov ebx, [edi+output]
		689	; stdcall get_dev_info, ebx
		690	; xor eax, eax
		691	; ret
		692	@@:
		693	cmp eax, DEV_GET_POS
		694	jne @F
		695	stdcall azx_get_position
		696	shr eax, 2
		697	mov ebx, [edi+output]
		698	mov [ebx], eax
		699	xor eax, eax
		700	ret
		701	@@:
		702	; cmp eax, DEV_SET_CHANNEL_VOLUME
		703	; jne @F
		704	; if DEBUG
		705	; mov esi, msgSetChannelVolume
		706	; call SysMsgBoardStr
		707	; end if
		708	; mov ebx, [edi+input]
		709	; mov cl, byte [ebx] ; cl=channel
		710	; mov eax, dword [ebx+1] ; eax=volume in Db
		711	; if DEBUG
		712	; push eax esi
		713	; mov esi, msgYAHOO1
		714	; call SysMsgBoardStr
		715	; stdcall fdword2str, 1
		716	; call SysMsgBoardStr
		717	; mov esi, strSemicolon
		718	; call SysMsgBoardStr
		719	; movzx eax, cl
		720	; stdcall fdword2str, 3
		721	; call SysMsgBoardStr
		722	; pop esi eax
		723	; end if
		724	;
		725	; call set_channel_volume
		726	; xor eax, eax
		727	; ret
		728	;@@:
		729	; cmp eax, DEV_GET_CHANNEL_VOLUME
		730	; jne @F
		731	; mov cl, byte [edi+input] ; cl=channel
		732	; call get_channel_volume
		733	; mov ebx, [edi+output]
		734	; mov [ebx], eax
		735	; xor eax, eax
		736	; ret
		737	;@@:
		738
		739	;Asper: Non standard system service. For the tests only! [
		740	@@:
		741	cmp eax, DEV_EXEC_CODEC_CMD
		742	jne @f
		743
		744	mov eax, [edi+input]
		745	mov eax, [eax]
		746	stdcall codec_exec_verb, eax
		747	xor eax, eax
		748	ret
		749	@@:
		750	;Asper: Non standard system service. For the tests only! ]
		751
		752
		753	.fail:
		754	or eax, -1
		755	ret
		756	endp
		757
		758	restore handle
		759	restore io_code
		760	restore input
		761	restore inp_size
		762	restore output
		763	restore out_size
		764
		765
		766	align 4
		767	proc hda_irq ;+
		768	if DEBUG_IRQ
		769	push eax esi
		770	;mov esi, msgIRQ
		771	;call SysMsgBoardStr
		772	call GetTimerTicks
		773	stdcall fdword2str, 2
		774	call SysMsgBoardStr
		775	pop esi eax
		776	end if
		777	mov edx, ICH6_REG_INTSTS
		778	call azx_readl
		779	test eax, eax
		780	jnz @f
		781	ret
		782	@@:
		783	mov ebx, eax ; status
		784	mov eax, SDO_INT
		785	test ebx, eax
		786	jz @f
		787
		788	mov edx, ICH6_REG_SD_STS + SDO_OFS
		789	call azx_readb
		790	mov bl, al
		791
		792	mov al, SD_INT_MASK
		793	mov edx, ICH6_REG_SD_STS + SDO_OFS
		794	call azx_writeb
		795
		796	test bl, SD_INT_COMPLETE
		797	jz @f
		798
		799	mov eax, [ctrl.civ_val]
		800	inc eax
		801	and eax, 4-1 ;2-1
		802	mov [ctrl.civ_val], eax
		803
		804	mov ebx, dword [buff_list+eax*4]
		805	cmp [ctrl.user_callback], 0
		806	je @f
		807	stdcall [ctrl.user_callback], ebx
		808
		809	@@:
		810
		811	; clear rirb int
		812	mov edx, ICH6_REG_RIRBSTS
		813	call azx_readb
		814
		815	test al, RIRB_INT_MASK
		816	jz .l1
		817	test al, RIRB_INT_RESPONSE
		818	jz .l2
		819
		820	cmp byte [driver_type], AZX_DRIVER_CTX
		821	jne @f
		822	mov eax, 80 ; wait 80 us
		823	call StallExec
		824	@@:
		825
		826	call azx_update_rirb
		827	.l2:
		828	mov al, RIRB_INT_MASK
		829	mov edx, ICH6_REG_RIRBSTS
		830	call azx_writeb
		831	.l1:
		832
		833	;if 0
		834	; clear state status int
		835	mov edx, ICH6_REG_STATESTS
		836	call azx_readb
		837	test al, 0x04
		838	jz @f
		839
		840	mov al, 0x04
		841	mov edx, ICH6_REG_STATESTS
		842	call azx_writeb
		843	@@:
		844	;end if
		845	or eax, 1
		846	ret
		847	endp
		848
		849
		850	align 4
		851	proc create_primary_buff
		852
		853	stdcall KernelAlloc, 4096
		854	mov [ctrl.posbuf], eax
		855
		856	stdcall KernelAlloc, 0x10000 ;0x8000
		857	mov [ctrl.buffer], eax
		858
		859	mov edi, eax
		860	mov ecx, 0x10000/4 ;0x8000/4
		861	xor eax, eax
		862	cld
		863	rep stosd
		864
		865
		866	stdcall KernelAlloc, 4096
		867	mov [pcmout_bdl], eax
		868
		869	mov edi, eax
		870	mov ecx, 4096/4
		871	xor eax, eax
		872	cld
		873	rep stosd
		874
		875
		876	; reset BDL address
		877	xor eax, eax
		878	mov edx, ICH6_REG_SD_BDLPL + SDO_OFS
		879	call azx_writel
		880	xor eax, eax
		881	mov edx, ICH6_REG_SD_BDLPU + SDO_OFS
		882	call azx_writel
		883
		884	; program the initial BDL entries
		885	mov eax, [ctrl.buffer]
		886	mov ebx, eax
		887	call GetPgAddr
		888	and ebx, 0xFFF
		889	add eax, ebx
		890
		891
		892	mov ebx, 0x4000 ;buffer size
		893	mov ecx, 8 ;number of periods
		894	mov edi, [pcmout_bdl] ;pcmout_bdl
		895	.next_period:
		896	push eax ecx
		897	mov ecx, 4 ;2 ;number of bdl in a period
		898	.next_bdl:
		899	; program the address field of the BDL entry
		900	mov dword [edi], eax
		901	mov dword [edi+4], 0
		902	; program the size field of the BDL entry
		903	mov dword [edi+8], ebx
		904	; program the IOC to enable interrupt when buffer completes
		905	mov dword [edi+12], 0x01
		906
		907
		908	add eax, ebx
		909	add edi, 16
		910	dec ecx
		911	jnz .next_bdl
		912
		913	pop ecx eax
		914	dec ecx
		915	jnz .next_period
		916
		917
		918	mov edi, buff_list
		919	mov eax, [ctrl.buffer]
		920	mov ecx, 4 ;2
		921	@@:
		922	mov [edi], eax
		923	mov [edi+8], eax
		924	mov [edi+16], eax
		925	mov [edi+24], eax
		926	mov [edi+32], eax
		927	mov [edi+40], eax
		928	mov [edi+48], eax
		929	mov [edi+56], eax
		930
		931	add eax, ebx
		932	add edi, 4
		933	loop @B
		934
		935	; wallclk has 24Mhz clock source
		936	mov [ctrl.period_wallclk], ((0x4000 * 24000) / 48000) * 1000
		937
		938	;-call azx_stream_reset
		939	call azx_setup_controller
		940	ret
		941	endp
		942
		943	align 4
		944	proc detect_controller
		945	locals
		946	last_bus dd ?
		947	bus dd ?
		948	devfn dd ?
		949	endl
		950
		951	xor eax, eax
		952	mov [bus], eax
		953	inc eax
		954	call PciApi
		955	cmp eax, -1
		956	je .err
		957
		958	mov [last_bus], eax
		959
		960	.next_bus:
		961	and [devfn], 0
		962	.next_dev:
		963	stdcall PciRead32, [bus], [devfn], dword 0
		964	test eax, eax
		965	jz .next
		966	cmp eax, -1
		967	je .next
		968
		969	mov edi, devices
		970	@@:
		971	mov ebx, [edi]
		972	test ebx, ebx
		973	jz .next
		974
		975	cmp eax, ebx
		976	je .found
		977	add edi, 12
		978	jmp @B
		979	.next:
		980	inc [devfn]
		981	cmp [devfn], 256
		982	jb .next_dev
		983	mov eax, [bus]
		984	inc eax
		985	mov [bus], eax
		986	cmp eax, [last_bus]
		987	jna .next_bus
		988	xor eax, eax
		989	ret
		990	.found:
		991	mov ebx, [bus]
		992	mov [ctrl.bus], ebx
		993
		994	mov ecx, [devfn]
		995	mov [ctrl.devfn], ecx
		996
		997	mov edx, eax
		998	and edx, 0xFFFF
		999	mov [ctrl.vendor], dx
		1000	shr eax, 16
		1001	mov [ctrl.dev_id], ax
		1002
		1003	mov ebx, [edi+4]
		1004	mov [ctrl.ctrl_ids], ebx
		1005
		1006	cmp edx, VID_INTEL
		1007	jne @F
		1008	mov [ctrl.vendor_ids], msg_Intel
		1009	jmp .ok
		1010	@@:
		1011	cmp edx, VID_NVIDIA
		1012	jne @F
		1013	mov [ctrl.vendor_ids], msg_NVidia
		1014	jmp .ok
		1015	@@:
		1016	cmp edx, VID_ATI
		1017	jne @F
		1018	cmp eax, 0x4383
		1019	jg .ati_hdmi
		1020	mov [ctrl.vendor_ids], msg_ATI
		1021	jmp .ok
		1022	.ati_hdmi:
		1023	mov [ctrl.vendor_ids], msg_ATI_HDMI
		1024	jmp .ok
		1025	@@:
		1026	cmp edx, VID_AMD
		1027	jne @F
		1028	mov [ctrl.vendor_ids], msg_AMD
		1029	jmp .ok
		1030	@@:
		1031	cmp edx, VID_VIA
		1032	jne @F
		1033	mov [ctrl.vendor_ids], msg_VIA
		1034	jmp .ok
		1035	@@:
		1036	cmp edx, VID_SIS
		1037	jne @F
		1038	mov [ctrl.vendor_ids], msg_SIS
		1039	jmp .ok
		1040	@@:
		1041	cmp edx, VID_ULI
		1042	jne @F
		1043	mov [ctrl.vendor_ids], msg_ULI
		1044	jmp .ok
		1045	@@:
		1046	cmp edx, VID_TERA
		1047	jne @F
		1048	mov [ctrl.vendor_ids], msg_TERA
		1049	jmp .ok
		1050	@@:
		1051	cmp edx, VID_CREATIVE
		1052	jne @F
		1053	mov [ctrl.vendor_ids], msg_CREATIVE
		1054	jmp .ok
		1055	@@:
		1056	cmp edx, VID_RDC
		1057	jne @F
		1058	mov [ctrl.vendor_ids], msg_RDC
		1059	jmp .ok
		1060	@@:
		1061	cmp edx, VID_VMWARE
		1062	jne @F
		1063	mov [ctrl.vendor_ids], msg_VMWARE
		1064	jmp .ok
		1065	@@:
		1066	.err:
		1067	xor eax, eax
		1068	mov [ctrl.vendor_ids], eax ;something wrong ?
		1069	mov [driver_type], -1
		1070	ret
		1071	.ok:
		1072	mov ebx, [edi+8]
		1073	mov [driver_type], ebx
		1074	ret
		1075	endp
		1076
		1077	align 4
		1078	proc init_controller
		1079
		1080	stdcall PciRead32, [ctrl.bus], [ctrl.devfn], dword 4
		1081	test eax, 0x4 ; Test Master bit
		1082	jnz @f
		1083	or eax, 0x4 ; Set Master bit
		1084	stdcall PciWrite32, [ctrl.bus], [ctrl.devfn], dword 4, eax
		1085	stdcall PciRead32, [ctrl.bus], [ctrl.devfn], dword 4
		1086	@@:
		1087
		1088	mov ebx, eax
		1089	and eax, 0xFFFF
		1090	mov [ctrl.pci_cmd], eax
		1091	shr ebx, 16
		1092	mov [ctrl.pci_stat], ebx
		1093
		1094	mov esi, msgPciCmd
		1095	call SysMsgBoardStr
		1096	stdcall fdword2str, 2
		1097	call SysMsgBoardStr
		1098
		1099	mov esi, msgPciStat
		1100	call SysMsgBoardStr
		1101	mov eax, [ctrl.pci_stat]
		1102	stdcall fdword2str, 2
		1103	call SysMsgBoardStr
		1104
		1105	mov esi, msgHDALowMMIo
		1106	call SysMsgBoardStr
		1107	stdcall PciRead32, [ctrl.bus], [ctrl.devfn], dword 0x10
		1108	stdcall fdword2str, 2
		1109	call SysMsgBoardStr
		1110
		1111	and eax, 0xFFFFC000
		1112	mov [ctrl.ctrl_mem_base], eax
		1113
		1114	mov esi, msgHDAUpMMIo
		1115	call SysMsgBoardStr
		1116	stdcall PciRead32, [ctrl.bus], [ctrl.devfn], dword 0x14
		1117	;-mov [ctrl.hda_upper_mem_base], eax
		1118	stdcall fdword2str, 2
		1119	call SysMsgBoardStr
		1120
		1121	.default:
		1122	stdcall PciRead32, [ctrl.bus], [ctrl.devfn], dword 0x3C
		1123	and eax, 0xFF
		1124	@@:
		1125	mov [ctrl.int_line], eax
		1126	mov [ctrl.user_callback], 0
		1127
		1128	call set_HDA
		1129	;Asper This is from "azx_create" proc. [
		1130	xor eax, eax
		1131	mov edx, ICH6_REG_GCAP
		1132	call azx_readw
		1133	if DEBUG
		1134	mov esi, msgGCap
		1135	call SysMsgBoardStr
		1136	stdcall fdword2str, 2
		1137	call SysMsgBoardStr
		1138	end if
		1139
		1140	; allocate CORB/RIRB
		1141	call azx_alloc_cmd_io
		1142
		1143	; initialize chip
		1144	call azx_init_pci
		1145
		1146	xor eax, eax
		1147	call azx_init_chip
		1148	;] Asper
		1149
		1150	xor eax, eax
		1151	inc eax
		1152	ret
		1153	endp
		1154
		1155
		1156
		1157
		1158	PG_SW equ 0x003
		1159	PG_NOCACHE equ 0x018
		1160
		1161	align 4
		1162	proc set_HDA
		1163
		1164	stdcall MapIoMem,[ctrl.ctrl_mem_base],0x1000,PG_SW+PG_NOCACHE
		1165	mov [ctrl.ctrl_mem_base], eax
		1166	ret
		1167	endp
		1168
		1169
		1170	; in: eax - fullreset_flag
		1171	;
		1172	; reset codec link
		1173	align 4
		1174	proc reset_controller
		1175	locals
		1176	counter dd ?
		1177	endl
		1178
		1179	test eax, eax
		1180	jz .skip
		1181
		1182	; clear STATESTS
		1183	mov eax, STATESTS_INT_MASK
		1184	mov edx, ICH6_REG_STATESTS
		1185	call azx_writeb
		1186
		1187	; reset controller
		1188	mov edx, ICH6_REG_GCTL
		1189	call azx_readl
		1190	mov ebx, ICH6_GCTL_RESET
		1191	xor ebx, -1
		1192	and eax, ebx
		1193	mov edx, ICH6_REG_GCTL
		1194	call azx_writel
		1195
		1196	mov [counter], 50 ; total 50*100 us = 0.5s
		1197	.wait0:
		1198
		1199	mov edx, ICH6_REG_GCTL
		1200	call azx_readb
		1201	test eax, eax
		1202	jz @f
		1203
		1204	mov eax, 100 ; wait 100 us
		1205	call StallExec
		1206
		1207	dec [counter]
		1208	jnz .wait0
		1209	@@:
		1210	; delay for >= 100us for codec PLL to settle per spec
		1211	; Rev 0.9 section 5.5.1
		1212	mov eax, 100 ; wait 100 us
		1213	call StallExec
		1214
		1215	; Bring controller out of reset
		1216	mov edx, ICH6_REG_GCTL
		1217	call azx_readb
		1218	or eax, ICH6_GCTL_RESET
		1219	mov edx, ICH6_REG_GCTL
		1220	call azx_writeb
		1221
		1222	mov [counter], 50 ; total 50*100 us = 0.5s
		1223	.wait1:
		1224
		1225	mov edx, ICH6_REG_GCTL
		1226	call azx_readb
		1227	test eax, eax
		1228	jnz @f
		1229
		1230	mov eax, 100 ; wait 100 us
		1231	call StallExec
		1232
		1233	dec [counter]
		1234	jnz .wait1
		1235	@@:
		1236
		1237	; Brent Chartrand said to wait >= 540us for codecs to intialize
		1238	mov eax, 540 ; wait 540 us
		1239	call StallExec
		1240
		1241	.skip:
		1242	; check to see if controller is ready
		1243	mov edx, ICH6_REG_GCTL
		1244	call azx_readb
		1245	test eax, eax
		1246	jz .fail
		1247
		1248	; Accept unsolicited responses
		1249	if USE_SINGLE_MODE
		1250	else
		1251	;UNSUPPORTED YET! [
		1252	; mov edx, ICH6_REG_GCTL
		1253	; call azx_readl
		1254	; or eax, ICH6_GCTL_UNSOL
		1255	; mov edx, ICH6_REG_GCTL
		1256	; call azx_writel
		1257	;UNSUPPORTED YET! ]
		1258	end if
		1259
		1260	; detect codecs
		1261	mov eax, [ctrl.codec_mask]
		1262	test ax, ax
		1263	jnz @f
		1264
		1265	mov edx, ICH6_REG_STATESTS
		1266	call azx_readw
		1267	mov [ctrl.codec_mask], eax
		1268
		1269	if DEBUG
		1270	mov esi, msgCodecMask
		1271	call SysMsgBoardStr
		1272	stdcall fdword2str, 2
		1273	call SysMsgBoardStr
		1274	end if
		1275
		1276	@@:
		1277
		1278	.ok:
		1279	clc
		1280	ret
		1281	.fail:
		1282	if DEBUG
		1283	mov esi, msgHDARFail
		1284	call SysMsgBoardStr
		1285	end if
		1286	stc
		1287	ret
		1288	endp
		1289
		1290
		1291	align 4
		1292	play:
		1293	mov edx, ICH6_REG_WALLCLK
		1294	call azx_readl
		1295	mov [ctrl.start_wallclk], eax
		1296
		1297	call azx_stream_start
		1298	xor eax, eax
		1299	ret
		1300
		1301	align 4
		1302	stop:
		1303	;* call azx_stream_stop ;Asper: Hangs system
		1304	;R push ebx ecx edx
		1305	;R ; stop DMA
		1306	;R mov edx, ICH6_REG_SD_CTL
		1307	;R call azx_sd_readb
		1308	;R mov bl, SD_CTL_DMA_START or SD_INT_MASK
		1309	;R xor bl, -1
		1310	;R and al, bl
		1311	;R mov edx, ICH6_REG_SD_CTL
		1312	;R call azx_sd_writeb
		1313	;R mov edx, ICH6_REG_SD_STS
		1314	;R mov al, SD_INT_MASK
		1315	;R call azx_sd_writeb ; to be sure
		1316	; disable SIE
		1317	;N mov edx, ICH6_REG_INTCTL
		1318	;N call azx_readb
		1319	;N mov bl, SDO_INT ;shl azx_dev->index
		1320	;N xor bl, -1
		1321	;N and al, bl
		1322	;N mov edx, ICH6_REG_INTCTL
		1323	;N call azx_writeb
		1324
		1325	; int timeout = 5000;
		1326	; while (azx_sd_readb(azx_dev, SD_CTL) & SD_CTL_DMA_START && --timeout) ;
		1327	;Asper: Hangs system [
		1328	;* mov ecx, 5000
		1329	;* .l1:
		1330	;* mov edx, ICH6_REG_SD_CTL
		1331	;* call azx_sd_readb
		1332	;* test al, SD_CTL_DMA_START
		1333	;* jz @f
		1334	;* dec ecx
		1335	;* jnz .l1
		1336	;* @@:
		1337	;*
		1338	;* pop edx ecx ebx
		1339	;Asper ]
		1340
		1341	xor eax, eax
		1342	ret
		1343
		1344	;align 4
		1345	;proc get_dev_info stdcall, p_info:dword
		1346	; virtual at esi
		1347	; CTRL_INFO CTRL_INFO
		1348	; end virtual
		1349	;
		1350	; mov esi, [p_info]
		1351	; mov eax, [ctrl.int_line]
		1352	; mov bx, [ctrl.dev_id]
		1353	; shl ebx, 16
		1354	; and bx, [ctrl.vendor]
		1355	; mov ecx, [ctrl.pci_cmd]
		1356	; mov edx, [ctrl.codec_mem_base] ;[ctrl.hda_lower_mem_base]
		1357	; mov edi, [ctrl.ctrl_mem_base] ;[ctrl.hda_upper_mem_base]
		1358	;
		1359	; mov [CTRL_INFO.irq], eax
		1360	; mov [CTRL_INFO.codec_id], ebx
		1361	; mov [CTRL_INFO.pci_cmd], ecx
		1362	; mov [CTRL_INFO.codec_mem_base], edx
		1363	; mov [CTRL_INFO.ctrl_mem_base], edi
		1364	;
		1365	; xor eax, eax
		1366	; mov [CTRL_INFO.codec_io_base], eax
		1367	; mov [CTRL_INFO.ctrl_io_base], eax
		1368	; mov [CTRL_INFO.glob_cntrl], eax
		1369	; mov [CTRL_INFO.glob_sta], eax
		1370	; ret
		1371	;endp
		1372
		1373	align 4
		1374	proc set_callback stdcall, handler:dword
		1375	mov eax, [handler]
		1376	mov [ctrl.user_callback], eax
		1377	ret
		1378	endp
		1379
		1380
		1381
		1382	;;;;;;;;;;;;;;;;;;;;;;;;;;;;
		1383	;; Interface for HD codec ;;
		1384	;;;;;;;;;;;;;;;;;;;;;;;;;;;;
		1385
		1386	;;;;;;;;;;;;;;;;;;;;;;;;;;;
		1387	;; CORB / RIRB interface ;;
		1388	;;;;;;;;;;;;;;;;;;;;;;;;;;;
		1389
		1390	proc azx_alloc_cmd_io
		1391	push eax ecx edx
		1392	; single page (at least 4096 bytes) must suffice for both ringbuffers
		1393	stdcall KernelAlloc, 4096
		1394	mov [ctrl.rb], eax
		1395
		1396	mov edi, eax
		1397	mov ecx, 4096/4
		1398	xor eax, eax
		1399	cld
		1400	rep stosd
		1401
		1402	pop edx ecx eax
		1403	ret
		1404	endp
		1405
		1406	proc azx_init_cmd_io
		1407	pusha
		1408	; CORB set up
		1409	mov eax, [ctrl.rb]
		1410	mov ebx, eax
		1411	call GetPgAddr
		1412	and ebx, 0xFFF
		1413	add eax, ebx
		1414	push eax ; save corb address
		1415	mov edx, ICH6_REG_CORBLBASE
		1416	call azx_writel
		1417	xor eax, eax
		1418	mov edx, ICH6_REG_CORBUBASE
		1419	call azx_writel
		1420
		1421	; set the corb size to 256 entries (ULI requires explicitly)
		1422	mov al, 0x02
		1423	mov edx, ICH6_REG_CORBSIZE
		1424	call azx_writeb
		1425	; set the corb write pointer to 0
		1426	xor ax, ax
		1427	mov edx, ICH6_REG_CORBWP
		1428	call azx_writew
		1429	; reset the corb hw read pointer
		1430	mov ax, ICH6_CORBRP_RST
		1431	mov edx, ICH6_REG_CORBRP
		1432	call azx_writew
		1433	; enable corb dma
		1434	mov al, ICH6_CORBCTL_RUN
		1435	mov edx, ICH6_REG_CORBCTL
		1436	call azx_writeb
		1437
		1438	; RIRB set up
		1439	mov [ctrl.rirb_rp], 0
		1440	mov [ctrl.rirb_wp], 0
		1441	mov [ctrl.rirb_cmd], 0
		1442
		1443	pop eax ; restore corb address
		1444	add eax, 2048
		1445	mov edx, ICH6_REG_RIRBLBASE
		1446	call azx_writel
		1447	xor eax, eax
		1448	mov edx, ICH6_REG_RIRBUBASE
		1449	call azx_writel
		1450
		1451	; set the rirb size to 256 entries (ULI requires explicitly)
		1452	mov al, 0x02
		1453	mov edx, ICH6_REG_RIRBSIZE
		1454	call azx_writeb
		1455	; reset the rirb hw write pointer
		1456	mov ax, ICH6_RIRBWP_RST
		1457	mov edx, ICH6_REG_RIRBWP
		1458	call azx_writew
		1459	; set N=1, get RIRB response interrupt for new entry
		1460	xor ax, ax
		1461	cmp byte [driver_type], AZX_DRIVER_CTX
		1462	jne @f
		1463	mov ax, 0xC0-1
		1464	@@:
		1465	inc ax
		1466	mov edx, ICH6_REG_RINTCNT
		1467	call azx_writew
		1468	; enable rirb dma and response irq
		1469	mov al, ICH6_RBCTL_DMA_EN or ICH6_RBCTL_IRQ_EN
		1470	mov edx, ICH6_REG_RIRBCTL
		1471	call azx_writeb
		1472
		1473	popa
		1474	ret
		1475	endp
		1476
		1477	proc azx_free_cmd_io
		1478	push eax edx
		1479	; disable ringbuffer DMAs
		1480	xor al, al
		1481	mov edx, ICH6_REG_RIRBCTL
		1482	call azx_writeb
		1483	mov edx, ICH6_REG_CORBCTL
		1484	call azx_writeb
		1485	pop edx eax
		1486	ret
		1487	endp
		1488
		1489
		1490	; send a command
		1491	proc azx_corb_send_cmd stdcall, val:dword
		1492	push edx edi
		1493	xor eax, eax
		1494	; add command to corb
		1495	mov edx, ICH6_REG_CORBWP
		1496	call azx_readb
		1497	inc al
		1498	inc dword [ctrl.rirb_cmd]
		1499	mov edi, dword [ctrl.rb]
		1500
		1501	push eax
		1502	shl eax, 2 ;wp=wpsizeof(corb entry)=wp4
		1503	add edi, eax
		1504	mov eax, dword [val]
		1505	stosd
		1506	pop eax
		1507	mov edx, ICH6_REG_CORBWP
		1508	call azx_writel
		1509
		1510	pop edi edx
		1511	xor eax, eax ;Asper+
		1512	ret
		1513	endp
		1514
		1515
		1516	; retrieve RIRB entry - called from interrupt handler
		1517	proc azx_update_rirb
		1518	pusha
		1519	xor eax, eax
		1520	mov edx, ICH6_REG_RIRBWP
		1521	call azx_readb ;call azx_readw
		1522
		1523	cmp ax, [ctrl.rirb_wp]
		1524	je .done
		1525	mov [ctrl.rirb_wp], ax
		1526	mov bx, [ctrl.rirb_rp]
		1527
		1528	.l1:
		1529	cmp bx, [ctrl.rirb_wp]
		1530	je .l3
		1531
		1532	inc bl
		1533	.l2:
		1534	cmp bx, ICH6_MAX_RIRB_ENTRIES
		1535	jl @f
		1536	sub bx, ICH6_MAX_RIRB_ENTRIES
		1537	jmp .l2
		1538	@@:
		1539
		1540	movzx edx, bx
		1541	shl edx, 1 + 2 ; an RIRB entry is 8-bytes
		1542	mov esi, dword [ctrl.rb]
		1543	add esi, 2048
		1544	add esi, edx
		1545	lodsd ; res
		1546	mov edx, eax
		1547	lodsd ; res_ex
		1548
		1549	test eax, ICH6_RIRB_EX_UNSOL_EV
		1550	jz @f
		1551	stdcall snd_hda_queue_unsol_event, edx, eax
		1552	jmp .l1
		1553	@@:
		1554	mov ecx, [ctrl.rirb_cmd]
		1555	test ecx, ecx
		1556	jz @f
		1557	mov [ctrl.rirb_res], edx
		1558	dec dword [ctrl.rirb_cmd]
		1559	jmp .l1
		1560	@@:
		1561	if DEBUG
		1562	push esi
		1563	mov esi, msgSpuriousResponce
		1564	call SysMsgBoardStr
		1565	pop esi
		1566	end if
		1567	jmp .l1
		1568	.l3:
		1569	mov [ctrl.rirb_rp], bx
		1570	.done:
		1571	popa
		1572	ret
		1573	endp
		1574
		1575	; receive a response
		1576	proc azx_rirb_get_response
		1577	locals
		1578	do_poll db 0
		1579	endl
		1580
		1581	push ebx ecx edx
		1582	.again:
		1583	mov ecx, 1000;+1000
		1584	.next_try:
		1585	mov al, [ctrl.polling_mode]
		1586	test al, al
		1587	jnz .poll
		1588	mov ah, [do_poll]
		1589	test ah, ah
		1590	jz @f
		1591	.poll:
		1592	call azx_update_rirb
		1593	@@:
		1594	mov eax, [ctrl.rirb_cmd]
		1595	test eax, eax
		1596	jnz .l1
		1597	mov [ctrl.rirb_error], 0
		1598	mov al, [do_poll]
		1599	test al, al
		1600	jnz @f
		1601	mov [ctrl.poll_count], 0
		1602	@@:
		1603	mov eax, [ctrl.rirb_res] ; the last value
		1604	jmp .out
		1605	.l1:
		1606	push eax
		1607	mov eax, 2000 ; temporary workaround
		1608	call StallExec
		1609	pop eax
		1610	dec ecx
		1611	jnz .next_try
		1612	.no_next_try:
		1613	mov al, [ctrl.polling_mode]
		1614	test al, al
		1615	jnz .no_poll
		1616
		1617	mov al, [ctrl.poll_count]
		1618	cmp al, 2
		1619	jge .poll_count_overflow
		1620	if DEBUG
		1621	push eax esi
		1622	mov esi, msgGetResponceTimeout
		1623	call SysMsgBoardStr
		1624	mov esi, msgPollingCodecOnce
		1625	call SysMsgBoardStr
		1626	pop esi eax
		1627	end if
		1628	mov [do_poll], 1
		1629	inc [ctrl.poll_count]
		1630	jmp .again
		1631
		1632	.poll_count_overflow:
		1633	if DEBUG
		1634	push eax esi
		1635	mov esi, msgGetResponceTimeout
		1636	call SysMsgBoardStr
		1637	mov esi, msgSwitchToPollMode
		1638	call SysMsgBoardStr
		1639	pop esi eax
		1640	end if
		1641	mov [ctrl.polling_mode], 1
		1642	jmp .again
		1643
		1644	.no_poll:
		1645
		1646	mov al, [ctrl.polling_mode]
		1647	test al, al
		1648	jz @f
		1649	mov eax, -1
		1650	jmp .out
		1651	@@:
		1652
		1653
		1654	; a fatal communication error; need either to reset or to fallback
		1655	; to the single_cmd mode
		1656	mov [ctrl.rirb_error], 1
		1657	;Asper~ -? [
		1658	mov [ctrl.response_reset], 1
		1659	mov eax, -1 ; give a chance to retry
		1660	jmp .out
		1661	;Asper~ -? ]
		1662
		1663	;-? mov [ctrl.single_cmd], 1
		1664	mov [ctrl.response_reset], 0
		1665
		1666	; release CORB/RIRB
		1667	call azx_free_cmd_io
		1668	; disable unsolicited responses
		1669	mov edx, ICH6_REG_GCTL
		1670	call azx_readl
		1671	mov ebx, ICH6_GCTL_UNSOL
		1672	xor ebx, -1
		1673	and eax, ebx
		1674	mov edx, ICH6_REG_GCTL
		1675	call azx_writel
		1676	mov eax, -1
		1677	.out:
		1678	pop edx ecx ebx
		1679	ret
		1680	endp
		1681
		1682	;
		1683	; Use the single immediate command instead of CORB/RIRB for simplicity
		1684	;
		1685	; Note: according to Intel, this is not preferred use. The command was
		1686	; intended for the BIOS only, and may get confused with unsolicited
		1687	; responses. So, we shouldn't use it for normal operation from the
		1688	; driver.
		1689	; I left the codes, however, for debugging/testing purposes.
		1690	;
		1691
		1692	; receive a response
		1693	proc azx_single_wait_for_response
		1694	push ecx edx esi
		1695
		1696	mov ecx, 50
		1697	.l1:
		1698	test ecx, ecx
		1699	jz .timeout
		1700
		1701	; check IRV busy bit
		1702	mov edx, ICH6_REG_IRS
		1703	call azx_readw
		1704	test ax, ICH6_IRS_VALID
		1705	jz @f
		1706	; reuse rirb.res as the response return value
		1707	mov edx, ICH6_REG_IR
		1708	call azx_readl
		1709	mov [ctrl.rirb_res], eax
		1710
		1711	pop esi edx ecx
		1712	xor eax, eax
		1713	ret
		1714	@@:
		1715	xor eax, eax
		1716	inc eax
		1717	call StallExec
		1718
		1719	dec ecx
		1720	jmp .l1
		1721	.timeout:
		1722	if DEBUG
		1723	xor eax, eax
		1724	mov edx, ICH6_REG_IRS
		1725	call azx_readw
		1726	mov esi, msgGetResponceTimeout
		1727	call SysMsgBoardStr
		1728	mov esi, msgIRS
		1729	call SysMsgBoardStr
		1730	stdcall fdword2str, 2
		1731	call SysMsgBoardStr
		1732	end if
		1733
		1734	pop esi edx ecx
		1735	mov eax, -1
		1736	mov [ctrl.rirb_res], eax
		1737	ret
		1738	endp
		1739
		1740	; send a command
		1741	proc azx_single_send_cmd stdcall, val:dword
		1742	push ecx edx esi
		1743
		1744	mov ecx, 50
		1745	.l1:
		1746	test ecx, ecx
		1747	jz .timeout
		1748
		1749	; check ICB busy bit
		1750	mov edx, ICH6_REG_IRS
		1751	call azx_readw
		1752	test ax, ICH6_IRS_BUSY
		1753	jnz @f
		1754	; Clear IRV valid bit
		1755	mov edx, ICH6_REG_IRS
		1756	call azx_readw
		1757	or ax, ICH6_IRS_VALID
		1758	mov edx, ICH6_REG_IRS
		1759	call azx_writew
		1760
		1761	mov eax, dword [val]
		1762	mov edx, ICH6_REG_IC
		1763	call azx_writel
		1764
		1765	mov edx, ICH6_REG_IRS
		1766	call azx_readw
		1767	or ax, ICH6_IRS_BUSY
		1768	mov edx, ICH6_REG_IRS
		1769	call azx_writew
		1770
		1771	stdcall azx_single_wait_for_response
		1772	pop esi edx ecx
		1773	ret
		1774	@@:
		1775	dec ecx
		1776	jmp .l1
		1777	.timeout:
		1778	if DEBUG
		1779	xor eax, eax
		1780	mov edx, ICH6_REG_IRS
		1781	call azx_readw
		1782	mov esi, msgSendCmdTimeout
		1783	call SysMsgBoardStr
		1784	stdcall fdword2str, 2
		1785	call SysMsgBoardStr
		1786	mov esi, msgVal
		1787	call SysMsgBoardStr
		1788	mov eax, dword [val]
		1789	stdcall fdword2str, 2
		1790	call SysMsgBoardStr
		1791	end if
		1792
		1793	pop esi edx ecx
		1794	mov eax, -1
		1795	ret
		1796	endp
		1797
		1798	; receive a response
		1799	proc azx_single_get_response
		1800	mov eax, [ctrl.rirb_res]
		1801	ret
		1802	endp
		1803
		1804	;
		1805	; The below are the main callbacks from hda_codec.
		1806	;
		1807	; They are just the skeleton to call sub-callbacks according to the
		1808	; current setting of chip->single_cmd.
		1809	;
		1810
		1811	; send a command
		1812	proc azx_send_cmd stdcall, val:dword
		1813	if USE_SINGLE_MODE
		1814	stdcall azx_single_send_cmd, [val]
		1815	else
		1816	stdcall azx_corb_send_cmd, [val]
		1817	end if
		1818	ret
		1819	endp
		1820
		1821	; get a response
		1822	proc azx_get_response
		1823	if USE_SINGLE_MODE
		1824	call azx_single_get_response
		1825	else
		1826	call azx_rirb_get_response
		1827	end if
		1828	ret
		1829	endp
		1830
		1831
		1832	;;;;;;;;;;;;;;;;;;;;;;;;
		1833	;; Lowlevel interface ;;
		1834	;;;;;;;;;;;;;;;;;;;;;;;;
		1835
		1836	; enable interrupts
		1837	proc azx_int_enable
		1838	push eax edx
		1839	; enable controller CIE and GIE
		1840	mov edx, ICH6_REG_INTCTL
		1841	call azx_readl
		1842	or eax, ICH6_INT_CTRL_EN or ICH6_INT_GLOBAL_EN
		1843	mov edx, ICH6_REG_INTCTL
		1844	call azx_writel
		1845	pop edx eax
		1846	ret
		1847	endp
		1848
		1849	; disable interrupts
		1850	proc azx_int_disable
		1851	push eax ebx edx
		1852
		1853	; disable interrupts in stream descriptor
		1854	mov edx, ICH6_REG_SD_CTL + SDO_OFS
		1855	call azx_readb
		1856	mov bl, SD_INT_MASK
		1857	xor bl, -1
		1858	and al, bl
		1859	mov edx, ICH6_REG_SD_CTL + SDO_OFS
		1860	call azx_writeb
		1861
		1862	; disable SIE for all streams
		1863	xor al, al
		1864	mov edx, ICH6_REG_INTCTL
		1865	call azx_writeb
		1866
		1867	; disable controller CIE and GIE
		1868	mov edx, ICH6_REG_INTCTL
		1869	call azx_readl
		1870	mov ebx, ICH6_INT_CTRL_EN or ICH6_INT_GLOBAL_EN
		1871	xor ebx, -1
		1872	and eax, ebx
		1873	call azx_writel
		1874	pop edx ebx eax
		1875	ret
		1876	endp
		1877
		1878	; clear interrupts
		1879	proc azx_int_clear
		1880	push eax edx
		1881
		1882	; clear stream status
		1883	mov al, SD_INT_MASK
		1884	mov edx, ICH6_REG_SD_STS + SDO_OFS
		1885	call azx_writeb
		1886
		1887	; clear STATESTS
		1888	mov al, STATESTS_INT_MASK
		1889	mov edx, ICH6_REG_STATESTS
		1890	call azx_writeb
		1891
		1892	; clear rirb status
		1893	mov al, RIRB_INT_MASK
		1894	mov edx, ICH6_REG_RIRBSTS
		1895	call azx_writeb
		1896
		1897	; clear int status
		1898	mov eax, ICH6_INT_CTRL_EN or ICH6_INT_ALL_STREAM
		1899	mov edx, ICH6_REG_INTSTS
		1900	call azx_writel
		1901	pop edx eax
		1902	ret
		1903	endp
		1904
		1905
		1906	; start a stream
		1907	proc azx_stream_start
		1908	push eax edx
		1909
		1910	; enable SIE
		1911	mov edx, ICH6_REG_INTCTL
		1912	call azx_readl
		1913
		1914	or eax, 0xC0000000 ;Asper+
		1915	or eax, SDO_INT ; Asper: output stream interrupt index
		1916	mov edx, ICH6_REG_INTCTL
		1917	call azx_writel
		1918	; set DMA start and interrupt mask
		1919	mov edx, ICH6_REG_SD_CTL + SDO_OFS
		1920	call azx_readb
		1921
		1922	or al, SD_CTL_DMA_START or SD_INT_MASK
		1923
		1924	mov edx, ICH6_REG_SD_CTL + SDO_OFS
		1925	call azx_writeb
		1926
		1927	pop edx eax
		1928	ret
		1929	endp
		1930
		1931	; stop DMA
		1932	proc azx_stream_clear
		1933	push eax ebx edx
		1934	mov edx, ICH6_REG_SD_CTL + SDO_OFS
		1935	call azx_readb
		1936	mov bl, SD_CTL_DMA_START or SD_INT_MASK
		1937	xor bl, -1
		1938	and al, bl
		1939	mov edx, ICH6_REG_SD_CTL + SDO_OFS
		1940	call azx_writeb
		1941	mov al, SD_INT_MASK
		1942	mov edx, ICH6_REG_SD_STS + SDO_OFS
		1943	call azx_writeb
		1944	pop edx ebx eax
		1945	ret
		1946	endp
		1947
		1948	; stop a stream
		1949	proc azx_stream_stop
		1950	push eax ebx edx
		1951	call azx_stream_clear
		1952	; disable SIE
		1953	mov edx, ICH6_REG_INTCTL
		1954	call azx_readl
		1955	mov ebx, (SDO_INT)
		1956	xor ebx, -1
		1957	and eax, ebx
		1958	mov edx, ICH6_REG_INTCTL
		1959	call azx_writel
		1960	pop edx ebx eax
		1961	ret
		1962	endp
		1963
		1964	;
		1965	;in: eax = full_reset
		1966	;
		1967	; initialize the chip
		1968	proc azx_init_chip
		1969	push eax
		1970
		1971	; reset controller
		1972	mov eax, 1 ;full reset
		1973	call reset_controller
		1974
		1975	; initialize interrupts
		1976	call azx_int_clear
		1977	call azx_int_enable
		1978
		1979	; initialize the codec command I/O
		1980	if USE_SINGLE_MODE
		1981	else
		1982	call azx_init_cmd_io
		1983	end if
		1984
		1985	; program the position buffer
		1986	mov eax, dword [ctrl.posbuf]
		1987	mov ebx, eax
		1988	call GetPgAddr
		1989	and ebx, 0xFFF
		1990	add eax, ebx
		1991	mov edx, ICH6_REG_DPLBASE
		1992	call azx_writel
		1993	xor eax, eax
		1994	mov edx, ICH6_REG_DPUBASE
		1995	call azx_writel
		1996
		1997	pop eax
		1998	ret
		1999	endp
		2000
		2001
		2002	; initialize the PCI registers
		2003
		2004	; update bits in a PCI register byte
		2005	proc update_pci_byte stdcall, reg:dword, mask:dword, val:dword
		2006	push ax bx
		2007	stdcall PciRead8, [ctrl.bus], [ctrl.devfn], [reg]
		2008	mov bl, byte [mask]
		2009	mov bh, bl
		2010	xor bl, -1
		2011	and al, bl
		2012	shr bx, 8
		2013	and bl, byte [val]
		2014	or al, bl
		2015	stdcall PciWrite8, [ctrl.bus], [ctrl.devfn], [reg], eax
		2016	pop bx ax
		2017	ret
		2018	endp
		2019
		2020
		2021	proc azx_init_pci
		2022	; Clear bits 0-2 of PCI register TCSEL (at offset 0x44)
		2023	; TCSEL == Traffic Class Select Register, which sets PCI express QOS
		2024	; Ensuring these bits are 0 clears playback static on some HD Audio
		2025	; codecs
		2026	push eax
		2027	stdcall update_pci_byte, ICH6_PCIREG_TCSEL, 0x07, 0
		2028
		2029	mov eax, [driver_type]
		2030	cmp eax, AZX_DRIVER_ATI
		2031	jne @f
		2032	; For ATI SB450 azalia HD audio, we need to enable snoop
		2033	stdcall update_pci_byte, ATI_SB450_HDAUDIO_MISC_CNTR2_ADDR, 0x07, ATI_SB450_HDAUDIO_ENABLE_SNOOP
		2034	jmp .done
		2035	@@:
		2036	cmp eax, AZX_DRIVER_NVIDIA
		2037	jne @f
		2038	; For NVIDIA HDA, enable snoop
		2039	stdcall update_pci_byte, NVIDIA_HDA_TRANSREG_ADDR, 0x0f, NVIDIA_HDA_ENABLE_COHBITS
		2040	stdcall update_pci_byte, NVIDIA_HDA_ISTRM_COH, 0x01, NVIDIA_HDA_ENABLE_COHBIT
		2041	stdcall update_pci_byte, NVIDIA_HDA_OSTRM_COH, 0x01, NVIDIA_HDA_ENABLE_COHBIT
		2042	jmp .done
		2043	@@:
		2044	cmp eax, AZX_DRIVER_SCH
		2045	je .l1
		2046	cmp eax, AZX_DRIVER_PCH
		2047	jne @f
		2048	.l1:
		2049	stdcall PciRead16, [ctrl.bus], [ctrl.devfn], dword INTEL_SCH_HDA_DEVC
		2050	test ax, INTEL_SCH_HDA_DEVC_NOSNOOP
		2051	jz @f
		2052	push ebx
		2053	mov ebx, INTEL_SCH_HDA_DEVC_NOSNOOP
		2054	xor ebx, -1
		2055	and eax, ebx
		2056	pop ebx
		2057	stdcall PciWrite16, [ctrl.bus], [ctrl.devfn], dword INTEL_SCH_HDA_DEVC, eax
		2058	stdcall PciRead16, [ctrl.bus], [ctrl.devfn], dword INTEL_SCH_HDA_DEVC
		2059
		2060	if DEBUG
		2061	push esi
		2062	mov esi, msgHDASnoopDisabled
		2063	call SysMsgBoardStr
		2064	mov esi, msg_OK
		2065	test ax, INTEL_SCH_HDA_DEVC_NOSNOOP
		2066	jz .snoop_ok
		2067	mov esi, msg_Fail
		2068	.snoop_ok:
		2069	call SysMsgBoardStr
		2070	pop esi
		2071	end if
		2072	@@:
		2073	.done:
		2074	pop eax
		2075	ret
		2076	endp
		2077
		2078
		2079	; reset stream
		2080	proc azx_stream_reset
		2081	push eax ebx ecx edx
		2082
		2083	call azx_stream_clear
		2084
		2085	mov edx, ICH6_REG_SD_CTL + SDO_OFS
		2086	call azx_readb
		2087	or al, SD_CTL_STREAM_RESET
		2088	mov edx, ICH6_REG_SD_CTL + SDO_OFS
		2089	call azx_writeb
		2090
		2091	mov eax, 3
		2092	call StallExec
		2093
		2094	mov ecx, 300
		2095	.l1:
		2096	mov edx, ICH6_REG_SD_CTL + SDO_OFS
		2097	call azx_readb
		2098	test al, SD_CTL_STREAM_RESET
		2099	jnz @f
		2100	dec ecx
		2101	jnz .l1
		2102	@@:
		2103	mov bl, SD_CTL_STREAM_RESET
		2104	xor bl, -1
		2105	and al, bl
		2106	mov edx, ICH6_REG_SD_CTL + SDO_OFS
		2107	call azx_writeb
		2108
		2109	mov eax, 3
		2110	call StallExec
		2111
		2112	mov ecx, 300
		2113	; waiting for hardware to report that the stream is out of reset
		2114	.l2:
		2115	mov edx, ICH6_REG_SD_CTL + SDO_OFS
		2116	call azx_readb
		2117	test al, SD_CTL_STREAM_RESET
		2118	jnz @f
		2119	dec ecx
		2120	jnz .l2
		2121	@@:
		2122	; reset first position - may not be synced with hw at this time
		2123	mov edx, [ctrl.posbuf]
		2124	mov dword [edx], 0
		2125	pop edx ecx ebx eax
		2126	ret
		2127	endp
		2128
		2129
		2130	; set up the SD for streaming
		2131	proc azx_setup_controller
		2132	push eax ebx ecx edx
		2133	; make sure the run bit is zero for SD
		2134	call azx_stream_clear
		2135
		2136	; program the stream_tag
		2137	mov edx, ICH6_REG_SD_CTL + SDO_OFS
		2138	call azx_readl
		2139	mov ecx, SD_CTL_STREAM_TAG_MASK
		2140	xor ecx, -1
		2141	and eax, ecx
		2142	mov ecx, SDO_TAG
		2143	shl ecx, SD_CTL_STREAM_TAG_SHIFT
		2144	or eax, ecx
		2145	; Asper stream_tag = SDO_TAG
		2146	mov edx, ICH6_REG_SD_CTL + SDO_OFS
		2147	call azx_writel
		2148
		2149	; program the length of samples in cyclic buffer
		2150	mov eax, 0x4000*32
		2151	mov edx, ICH6_REG_SD_CBL + SDO_OFS
		2152	call azx_writel
		2153
		2154	; program the stream format
		2155	; this value needs to be the same as the one programmed
		2156	mov ax, 0x11
		2157	mov edx, ICH6_REG_SD_FORMAT + SDO_OFS
		2158	call azx_writew
		2159
		2160	; program the stream LVI (last valid index) of the BDL
		2161	mov eax, 32-1 ;4-1 ;2-1
		2162	mov [ctrl.lvi_reg], eax
		2163	mov edx, ICH6_REG_SD_LVI + SDO_OFS
		2164	call azx_writew
		2165
		2166	; program the BDL address
		2167	; lower BDL address
		2168	mov eax, [pcmout_bdl]
		2169	mov ebx, eax
		2170	call GetPgAddr
		2171	and ebx, 0xFFF
		2172	add eax, ebx
		2173	mov edx, ICH6_REG_SD_BDLPL + SDO_OFS
		2174	call azx_writel
		2175	; upper BDL address
		2176	xor eax, eax ;upper_32bit(azx_dev->bdl_addr)
		2177	mov edx, ICH6_REG_SD_BDLPU + SDO_OFS
		2178	call azx_writel
		2179
		2180	; enable the position buffer
		2181	cmp [ctrl.position_fix], POS_FIX_LPIB
		2182	jz @f
		2183	mov edx, ICH6_REG_DPLBASE
		2184	call azx_readl
		2185	and eax, ICH6_DPLBASE_ENABLE
		2186	jnz @f
		2187	mov eax, dword [ctrl.posbuf]
		2188	mov ebx, eax
		2189	call GetPgAddr
		2190	and ebx, 0xFFF
		2191	add eax, ebx
		2192	or eax, ICH6_DPLBASE_ENABLE
		2193	mov edx, ICH6_REG_DPLBASE
		2194	call azx_writel
		2195	@@:
		2196
		2197	; set the interrupt enable bits in the descriptor control register
		2198	mov edx, ICH6_REG_SD_CTL + SDO_OFS
		2199	call azx_readl
		2200	or eax, SD_INT_MASK
		2201	mov edx, ICH6_REG_SD_CTL + SDO_OFS
		2202	call azx_writel
		2203
		2204	pop edx ecx ebx eax
		2205	ret
		2206	endp
		2207
		2208
		2209	;(...)
		2210
		2211	; Probe the given codec address
		2212	proc probe_codec, addr:dword
		2213	push edx
		2214	mov eax, [addr]
		2215	shl eax, 28
		2216	mov edx, (AC_NODE_ROOT shl 20) or (AC_VERB_PARAMETERS shl 8) or AC_PAR_VENDOR_ID
		2217	or eax, edx
		2218	stdcall azx_send_cmd, eax
		2219	stdcall azx_get_response
		2220
		2221	cmp eax, -1
		2222	je .out
		2223	mov eax, [addr]
		2224	mov [codec.addr], eax ;Asper+
		2225	if DEBUG
		2226	push esi
		2227	mov esi, msgCodecOK
		2228	call SysMsgBoardStr
		2229	mov esi, msgCAd
		2230	call SysMsgBoardStr
		2231	stdcall fdword2str, 3
		2232	call SysMsgBoardStr
		2233	pop esi
		2234	end if
		2235	xor eax, eax
		2236	.out:
		2237	pop edx
		2238	ret
		2239	endp
		2240
		2241
		2242	proc azx_bus_reset
		2243	call azx_stop_chip
		2244	call azx_init_chip
		2245	endp
		2246
		2247
		2248	; Codec initialization
		2249	proc azx_codec_create
		2250	push ebx ecx edx
		2251	;(...)
		2252	; First try to probe all given codec slots
		2253	; Asper: We asume for now that max slots for codecs = 4
		2254	xor ecx, ecx
		2255	xor edx, edx
		2256	inc edx
		2257	.next_slot:
		2258	test edx, [ctrl.codec_mask]
		2259	jz @f
		2260	stdcall probe_codec, ecx
		2261	test eax, eax
		2262	jz .init ;@f
		2263	; Some BIOSen give you wrong codec addresses that don't exist
		2264	if DEBUG
		2265	mov esi, msgCodecError
		2266	call SysMsgBoardStr
		2267	end if
		2268	mov ebx, edx
		2269	xor ebx, -1
		2270	and [ctrl.codec_mask], ebx
		2271
		2272	; More badly, accessing to a non-existing
		2273	; codec often screws up the controller chip,
		2274	; and disturbs the further communications.
		2275	; Thus if an error occurs during probing,
		2276	; better to reset the controller chip to
		2277	; get back to the sanity state.
		2278	;call azx_bus_reset
		2279	@@:
		2280	shl edx, 1
		2281	inc ecx
		2282	; if USE_FIRST_CODEC
		2283	; cmp ecx, 1
		2284	; else
		2285	cmp ecx, 3
		2286	; end if
		2287	jl .next_slot
		2288	mov eax, -1
		2289	jmp .out
		2290	.init:
		2291	stdcall snd_hda_codec_init
		2292	xor eax, eax
		2293	.out:
		2294	pop edx ecx ebx
		2295	ret
		2296	endp
		2297
		2298
		2299	proc azx_codec_configure
		2300	;(...)
		2301	call snd_hda_codec_configure
		2302	ret
		2303	endp
		2304
		2305
		2306	proc azx_get_position
		2307	test [ctrl.position_fix], POS_FIX_LPIB
		2308	jz @f
		2309	; read LPIB
		2310	mov edx, ICH6_REG_SD_LPIB + SDO_OFS
		2311	call azx_readl
		2312	jmp .out
		2313	@@:
		2314	test [ctrl.position_fix], POS_FIX_VIACOMBO
		2315	jz @f
		2316	; call azx_get_via_position
		2317	; jmp .out
		2318	@@:
		2319	; use the position buffer
		2320	push edx
		2321	mov edx, dword [ctrl.posbuf]
		2322	mov eax, dword [edx]
		2323	pop edx
		2324	.out:
		2325	cmp eax, 0x4000 ; bufsize
		2326	jl @f
		2327	xor eax, eax
		2328	@@:
		2329	ret
		2330	endp
		2331
		2332
		2333	proc azx_stop_chip
		2334	push eax edx
		2335
		2336	; disable interrupts
		2337	call azx_int_disable
		2338	call azx_int_clear
		2339	; disable CORB/RIRB
		2340	call azx_free_cmd_io
		2341	; disable position buffer
		2342	xor eax, eax
		2343	mov edx, ICH6_REG_DPLBASE
		2344	call azx_writel
		2345	mov edx, ICH6_REG_DPUBASE
		2346	call azx_writel
		2347
		2348	pop edx eax
		2349	ret
		2350	endp
		2351
		2352
		2353	; in: eax = volume (-10000 - 0)
		2354	align 4
		2355	set_master_vol:
		2356	mov ecx, 3
		2357	call set_channel_volume
		2358	ret
		2359
		2360
		2361	; out: [pvol] = volume (-10000 - 0)
		2362	align 4
		2363	proc get_master_vol stdcall, pvol:dword
		2364	xor ecx, ecx
		2365	call get_channel_volume
		2366	mov ebx, [pvol]
		2367	mov [ebx], eax
		2368	xor eax, eax
		2369	ret
		2370	endp
		2371
		2372
		2373	; in: ecx = channel mask (1 - Left; 2 - Right; 3-Both)
		2374	; eax = volume (-10000 - 0)
		2375	align 4
		2376	set_channel_volume:
		2377	push eax ebx ecx edx
		2378	mov ebx, [volume.maxDb]
		2379	neg eax
		2380	if 0;DEBUG ;YAHOO
		2381	push eax esi
		2382	mov esi, msgNewVolume
		2383	call SysMsgBoardStr
		2384	stdcall fdword2str, 2
		2385	call SysMsgBoardStr
		2386
		2387	mov esi, msgMaxVolume
		2388	call SysMsgBoardStr
		2389	mov eax, ebx
		2390	stdcall fdword2str, 2
		2391	call SysMsgBoardStr
		2392	pop esi eax
		2393	end if
		2394	test ebx, ebx
		2395	jz .err_out
		2396
		2397	cmp eax, 0
		2398	jg @f
		2399	xor eax, eax
		2400	jmp .set
		2401	@@:
		2402	cmp eax, ebx
		2403	jl .set
		2404	mov eax, ebx
		2405	.set:
		2406	;cdq
		2407	xor edx, edx
		2408	shl eax, 2
		2409	mov ebx, 100
		2410	div bx
		2411	mov bl, [volume.step_size]
		2412	div bl
		2413
		2414	mov edx, [volume.out_amp_node]
		2415	test edx, edx
		2416	jz .out
		2417	movzx ebx, [edx+HDA_GNODE.nid]
		2418
		2419	test ecx, 1 ; Left channel ?
		2420	jz @f
		2421	stdcall put_volume_mute, ebx, 0, HDA_OUTPUT, 0, eax
		2422	@@:
		2423	test ecx, 2 ; Right channel ?
		2424	jz .out
		2425	stdcall put_volume_mute, ebx, 1, HDA_OUTPUT, 0, eax
		2426	.out:
		2427	pop edx ecx ebx eax
		2428	ret
		2429	.err_out:
		2430	if 0;DEBUG ;YAHOO
		2431	push esi
		2432	mov esi, emsgNoVolCtrl
		2433	call SysMsgBoardStr
		2434	pop esi
		2435	end if
		2436	jmp .out
		2437
		2438	; in: ecx = channel (1 - Left; 2 - Right)
		2439	; out: eax = volume (-10000 - 0)
		2440	align 4
		2441	get_channel_volume:
		2442	push ebx ecx edx
		2443	cmp ecx, 2
		2444	jg .out
		2445	dec cl
		2446	xor eax, eax
		2447	mov edx, [volume.out_amp_node]
		2448	test edx, edx
		2449	jz .out
		2450	movzx ebx, [edx+HDA_GNODE.nid]
		2451	stdcall get_volume_mute, ebx, ecx, HDA_OUTPUT, 0
		2452	mov cl, [volume.step_size]
		2453	mul cl
		2454
		2455	mov cx, 100
		2456	mul cx
		2457	shr eax, 2 ; *0.25
		2458	neg eax
		2459	.out:
		2460	pop edx ecx ebx
		2461	ret
		2462
		2463
		2464	; in: ecx = delay
		2465	udelay:
		2466	push eax ecx edx
		2467	test ecx, ecx
		2468	jnz @f
		2469	inc ecx
		2470	@@:
		2471	mov eax, ecx
		2472	mov cx, 500
		2473	mul cl
		2474	mov ecx, edx
		2475	shl ecx, 16
		2476	or ecx, eax
		2477	@@:
		2478	xor eax, eax
		2479	cpuid
		2480	dec ecx
		2481	jz @b
		2482	pop edx ecx eax
		2483	ret
		2484
		2485	align 4
		2486	proc StallExec
		2487	push ecx
		2488	push edx
		2489	push ebx
		2490	push eax
		2491
		2492	mov ecx, CPU_FREQ
		2493	mul ecx
		2494	mov ebx, eax ;low
		2495	mov ecx, edx ;high
		2496	rdtsc
		2497	add ebx, eax
		2498	adc ecx,edx
		2499	@@:
		2500	rdtsc
		2501	sub eax, ebx
		2502	sbb edx, ecx
		2503	js @B
		2504
		2505	pop eax
		2506	pop ebx
		2507	pop edx
		2508	pop ecx
		2509	ret
		2510	endp
		2511
		2512	;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
		2513	; MEMORY MAPPED IO (os depended) ;
		2514	;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
		2515
		2516	align 4
		2517	proc azx_readb
		2518	add edx, [ctrl.ctrl_mem_base]
		2519	mov al, [edx]
		2520	ret
		2521	endp
		2522
		2523	align 4
		2524	proc azx_readw
		2525	add edx, [ctrl.ctrl_mem_base]
		2526	mov ax, [edx]
		2527	ret
		2528	endp
		2529
		2530	align 4
		2531	proc azx_readl
		2532	add edx, [ctrl.ctrl_mem_base]
		2533	mov eax, [edx]
		2534	ret
		2535	endp
		2536
		2537	align 4
		2538	proc azx_writeb
		2539	add edx, [ctrl.ctrl_mem_base]
		2540	mov [edx], al
		2541	ret
		2542	endp
		2543
		2544	align 4
		2545	proc azx_writew
		2546	add edx, [ctrl.ctrl_mem_base]
		2547	mov [edx], ax
		2548	ret
		2549	endp
		2550
		2551	align 4
		2552	proc azx_writel
		2553	add edx, [ctrl.ctrl_mem_base]
		2554	mov [edx], eax
		2555	ret
		2556	endp
		2557
		2558	;_______
		2559
		2560
		2561	;Asper remember to add this functions:
		2562	proc snd_hda_queue_unsol_event stdcall, par1:dword, par2:dword
		2563	if DEBUG
		2564	push esi
		2565	mov esi, msgUnsolEvent
		2566	call SysMsgBoardStr
		2567	pop esi
		2568	end if
		2569	ret
		2570	endp
		2571	;...
		2572
		2573
		2574	align 4
		2575	proc fdword2str stdcall, flags:dword ; bit 0 - skipLeadZeroes; bit 1 - newLine; other bits undefined
		2576	push eax ebx ecx
		2577	mov esi, hex_buff
		2578	mov ecx, -8
		2579	push eax
		2580	@@:
		2581	rol eax, 4
		2582	mov ebx, eax
		2583	and ebx, 0x0F
		2584	mov bl, [ebx+hexletters]
		2585	mov [8+esi+ecx], bl
		2586	inc ecx
		2587	jnz @B
		2588	pop eax
		2589
		2590	mov dword [esi+8], 0
		2591	test [flags], 0x2 ; new line ?
		2592	jz .no_newline
		2593	mov dword [esi+8], 0x00000A0D
		2594	.no_newline:
		2595
		2596	push eax
		2597	test [flags], 0x1 ; skip zero bits ?
		2598	jz .no_skipz
		2599	mov ecx, 8
		2600	@@:
		2601	test eax, 0xF0000000
		2602	jnz .skipz_done
		2603	rol eax, 4
		2604	inc esi
		2605	dec ecx
		2606	jnz @b
		2607	dec esi
		2608	.skipz_done:
		2609	.no_skipz:
		2610	pop eax
		2611
		2612	pop ecx ebx eax
		2613	ret
		2614	endp
		2615
		2616	hexletters db '0123456789ABCDEF'
		2617	hex_buff db 8 dup(0),13,10,0,0
		2618
		2619
3085	leency	2620	include "CODEC.INC"
3083	leency	2621	include "hda_generic.inc"
		2622
		2623	align 4
		2624	devices:
		2625	; Intel
		2626	dd (CTRL_INTEL_SCH2 shl 16)+VID_INTEL,msg_INTEL_SCH2, AZX_DRIVER_SCH
		2627	dd (CTRL_INTEL_HPT shl 16)+VID_INTEL,msg_INTEL_HPT, AZX_DRIVER_SCH
		2628	dd (CTRL_INTEL_CPT shl 16)+VID_INTEL,msg_INTEL_CPT, AZX_DRIVER_PCH
		2629	dd (CTRL_INTEL_PGB shl 16)+VID_INTEL,msg_INTEL_PGB, AZX_DRIVER_PCH
		2630	dd (CTRL_INTEL_PPT1 shl 16)+VID_INTEL,msg_INTEL_PPT1, AZX_DRIVER_PCH
		2631	dd (CTRL_INTEL_82801F shl 16)+VID_INTEL,msg_INTEL_82801F, AZX_DRIVER_ICH
		2632	dd (CTRL_INTEL_63XXESB shl 16)+VID_INTEL,msg_INTEL_63XXESB, AZX_DRIVER_ICH
		2633	dd (CTRL_INTEL_82801G shl 16)+VID_INTEL,msg_INTEL_82801G, AZX_DRIVER_ICH
		2634	dd (CTRL_INTEL_82801H shl 16)+VID_INTEL,msg_INTEL_82801H, AZX_DRIVER_ICH
		2635	dd (CTRL_INTEL_82801_UNK1 shl 16)+VID_INTEL,msg_INTEL_82801_UNK1, AZX_DRIVER_ICH
		2636	dd (CTRL_INTEL_82801I shl 16)+VID_INTEL,msg_INTEL_82801I, AZX_DRIVER_ICH
		2637	dd (CTRL_INTEL_82801_UNK2 shl 16)+VID_INTEL,msg_INTEL_82801_UNK2, AZX_DRIVER_ICH
		2638	dd (CTRL_INTEL_82801JI shl 16)+VID_INTEL,msg_INTEL_82801JI, AZX_DRIVER_ICH
		2639	dd (CTRL_INTEL_82801JD shl 16)+VID_INTEL,msg_INTEL_82801JD, AZX_DRIVER_ICH
		2640	dd (CTRL_INTEL_PCH shl 16)+VID_INTEL,msg_INTEL_PCH, AZX_DRIVER_PCH
		2641	dd (CTRL_INTEL_PCH2 shl 16)+VID_INTEL,msg_INTEL_PCH2, AZX_DRIVER_PCH
		2642	dd (CTRL_INTEL_SCH shl 16)+VID_INTEL,msg_INTEL_SCH, AZX_DRIVER_SCH
		2643	dd (CTRL_INTEL_LPT shl 16)+VID_INTEL,msg_INTEL_LPT, AZX_DRIVER_PCH
		2644	; Nvidia
		2645	dd (CTRL_NVIDIA_MCP51 shl 16)+VID_NVIDIA,msg_NVIDIA_MCP51, AZX_DRIVER_NVIDIA
		2646	dd (CTRL_NVIDIA_MCP55 shl 16)+VID_NVIDIA,msg_NVIDIA_MCP55, AZX_DRIVER_NVIDIA
		2647	dd (CTRL_NVIDIA_MCP61_1 shl 16)+VID_NVIDIA,msg_NVIDIA_MCP61, AZX_DRIVER_NVIDIA
		2648	dd (CTRL_NVIDIA_MCP61_2 shl 16)+VID_NVIDIA,msg_NVIDIA_MCP61, AZX_DRIVER_NVIDIA
		2649	dd (CTRL_NVIDIA_MCP65_1 shl 16)+VID_NVIDIA,msg_NVIDIA_MCP65, AZX_DRIVER_NVIDIA
		2650	dd (CTRL_NVIDIA_MCP65_2 shl 16)+VID_NVIDIA,msg_NVIDIA_MCP65, AZX_DRIVER_NVIDIA
		2651	dd (CTRL_NVIDIA_MCP67_1 shl 16)+VID_NVIDIA,msg_NVIDIA_MCP67, AZX_DRIVER_NVIDIA
		2652	dd (CTRL_NVIDIA_MCP67_2 shl 16)+VID_NVIDIA,msg_NVIDIA_MCP67, AZX_DRIVER_NVIDIA
		2653	dd (CTRL_NVIDIA_MCP73_1 shl 16)+VID_NVIDIA,msg_NVIDIA_MCP73, AZX_DRIVER_NVIDIA
		2654	dd (CTRL_NVIDIA_MCP73_2 shl 16)+VID_NVIDIA,msg_NVIDIA_MCP73, AZX_DRIVER_NVIDIA
		2655	dd (CTRL_NVIDIA_MCP78_1 shl 16)+VID_NVIDIA,msg_NVIDIA_MCP78, AZX_DRIVER_NVIDIA
		2656	dd (CTRL_NVIDIA_MCP78_2 shl 16)+VID_NVIDIA,msg_NVIDIA_MCP78, AZX_DRIVER_NVIDIA
		2657	dd (CTRL_NVIDIA_MCP78_3 shl 16)+VID_NVIDIA,msg_NVIDIA_MCP78, AZX_DRIVER_NVIDIA
		2658	dd (CTRL_NVIDIA_MCP78_4 shl 16)+VID_NVIDIA,msg_NVIDIA_MCP78, AZX_DRIVER_NVIDIA
		2659	dd (CTRL_NVIDIA_MCP79_1 shl 16)+VID_NVIDIA,msg_NVIDIA_MCP79, AZX_DRIVER_NVIDIA
		2660	dd (CTRL_NVIDIA_MCP79_2 shl 16)+VID_NVIDIA,msg_NVIDIA_MCP79, AZX_DRIVER_NVIDIA
		2661	dd (CTRL_NVIDIA_MCP79_3 shl 16)+VID_NVIDIA,msg_NVIDIA_MCP79, AZX_DRIVER_NVIDIA
		2662	dd (CTRL_NVIDIA_MCP79_4 shl 16)+VID_NVIDIA,msg_NVIDIA_MCP79, AZX_DRIVER_NVIDIA
		2663	dd (CTRL_NVIDIA_0BE2 shl 16)+VID_NVIDIA,msg_NVIDIA_0BE2, AZX_DRIVER_NVIDIA
		2664	dd (CTRL_NVIDIA_0BE3 shl 16)+VID_NVIDIA,msg_NVIDIA_0BE3, AZX_DRIVER_NVIDIA
		2665	dd (CTRL_NVIDIA_0BE4 shl 16)+VID_NVIDIA,msg_NVIDIA_0BE4, AZX_DRIVER_NVIDIA
		2666	dd (CTRL_NVIDIA_GT100 shl 16)+VID_NVIDIA,msg_NVIDIA_GT100, AZX_DRIVER_NVIDIA
		2667	dd (CTRL_NVIDIA_GT106 shl 16)+VID_NVIDIA,msg_NVIDIA_GT106, AZX_DRIVER_NVIDIA
		2668	dd (CTRL_NVIDIA_GT108 shl 16)+VID_NVIDIA,msg_NVIDIA_GT108, AZX_DRIVER_NVIDIA
		2669	dd (CTRL_NVIDIA_GT104 shl 16)+VID_NVIDIA,msg_NVIDIA_GT104, AZX_DRIVER_NVIDIA
		2670	dd (CTRL_NVIDIA_GT116 shl 16)+VID_NVIDIA,msg_NVIDIA_GT116, AZX_DRIVER_NVIDIA
		2671	dd (CTRL_NVIDIA_MCP89_1 shl 16)+VID_NVIDIA,msg_NVIDIA_MCP89, AZX_DRIVER_NVIDIA
		2672	dd (CTRL_NVIDIA_MCP89_2 shl 16)+VID_NVIDIA,msg_NVIDIA_MCP89, AZX_DRIVER_NVIDIA
		2673	dd (CTRL_NVIDIA_MCP89_3 shl 16)+VID_NVIDIA,msg_NVIDIA_MCP89, AZX_DRIVER_NVIDIA
		2674	dd (CTRL_NVIDIA_MCP89_4 shl 16)+VID_NVIDIA,msg_NVIDIA_MCP89, AZX_DRIVER_NVIDIA
		2675	dd (CTRL_NVIDIA_GF119 shl 16)+VID_NVIDIA,msg_NVIDIA_GF119, AZX_DRIVER_NVIDIA
		2676	dd (CTRL_NVIDIA_GF110_1 shl 16)+VID_NVIDIA,msg_NVIDIA_GF110, AZX_DRIVER_NVIDIA
		2677	dd (CTRL_NVIDIA_GF110_2 shl 16)+VID_NVIDIA,msg_NVIDIA_GF110, AZX_DRIVER_NVIDIA
		2678	; ATI
		2679	dd (CTRL_ATI_SB450 shl 16)+VID_ATI,msg_ATI_SB450, AZX_DRIVER_ATI
		2680	dd (CTRL_ATI_SB600 shl 16)+VID_ATI,msg_ATI_SB600, AZX_DRIVER_ATI
		2681	dd (CTRL_ATI_RS600 shl 16)+VID_ATI,msg_ATI_RS600, AZX_DRIVER_ATIHDMI
		2682	dd (CTRL_ATI_RS690 shl 16)+VID_ATI,msg_ATI_RS690, AZX_DRIVER_ATIHDMI
		2683	dd (CTRL_ATI_RS780 shl 16)+VID_ATI,msg_ATI_RS780, AZX_DRIVER_ATIHDMI
		2684	dd (CTRL_ATI_RS_UNK1 shl 16)+VID_ATI,msg_ATI_RS_UNK1, AZX_DRIVER_ATIHDMI
		2685	dd (CTRL_ATI_R600 shl 16)+VID_ATI,msg_ATI_R600, AZX_DRIVER_ATIHDMI
		2686	dd (CTRL_ATI_RV610 shl 16)+VID_ATI,msg_ATI_RV610, AZX_DRIVER_ATIHDMI
		2687	dd (CTRL_ATI_RV620 shl 16)+VID_ATI,msg_ATI_RV620, AZX_DRIVER_ATIHDMI
		2688	dd (CTRL_ATI_RV630 shl 16)+VID_ATI,msg_ATI_RV630, AZX_DRIVER_ATIHDMI
		2689	dd (CTRL_ATI_RV635 shl 16)+VID_ATI,msg_ATI_RV635, AZX_DRIVER_ATIHDMI
		2690	dd (CTRL_ATI_RV670 shl 16)+VID_ATI,msg_ATI_RV670, AZX_DRIVER_ATIHDMI
		2691	dd (CTRL_ATI_RV710 shl 16)+VID_ATI,msg_ATI_RV710, AZX_DRIVER_ATIHDMI
		2692	dd (CTRL_ATI_RV730 shl 16)+VID_ATI,msg_ATI_RV730, AZX_DRIVER_ATIHDMI
		2693	dd (CTRL_ATI_RV740 shl 16)+VID_ATI,msg_ATI_RV740, AZX_DRIVER_ATIHDMI
		2694	dd (CTRL_ATI_RV770 shl 16)+VID_ATI,msg_ATI_RV770, AZX_DRIVER_ATIHDMI
		2695	; AMD
		2696	dd (CTRL_AMD_HUDSON shl 16)+VID_AMD,msg_AMD_HUDSON, AZX_DRIVER_GENERIC
		2697	; VIA
		2698	dd (CTRL_VIA_VT82XX shl 16)+VID_VIA,msg_VIA_VT82XX, AZX_DRIVER_VIA
		2699	dd (CTRL_VIA_VT61XX shl 16)+VID_VIA,msg_VIA_VT61XX, AZX_DRIVER_GENERIC
		2700	dd (CTRL_VIA_VT71XX shl 16)+VID_VIA,msg_VIA_VT71XX, AZX_DRIVER_GENERIC
		2701	; SiS
		2702	dd (CTRL_SIS_966 shl 16)+VID_SIS,msg_SIS_966, AZX_DRIVER_SIS
		2703	; ULI
		2704	dd (CTRL_ULI_M5461 shl 16)+VID_ULI,msg_ULI_M5461, AZX_DRIVER_ULI
		2705	; Teradici
		2706	dd (CTRL_TERA_UNK1 shl 16)+VID_ULI,msg_TERA_UNK1, AZX_DRIVER_TERA
		2707	; Creative
		2708	dd (CTRL_CREATIVE_CA0110_IBG shl 16)+VID_CREATIVE,msg_CREATIVE_CA0110_IBG, AZX_DRIVER_CTX
		2709	dd (CTRL_CREATIVE_SOUND_CORE3D_1 shl 16)+VID_CREATIVE,msg_CREATIVE_SOUND_CORE3D, AZX_DRIVER_GENERIC
		2710	dd (CTRL_CREATIVE_SOUND_CORE3D_2 shl 16)+VID_CREATIVE,msg_CREATIVE_SOUND_CORE3D, AZX_DRIVER_GENERIC
		2711	; RDC Semiconductor
		2712	dd (CTRL_RDC_R3010 shl 16)+VID_RDC,msg_RDC_R3010, AZX_DRIVER_GENERIC
		2713	; VMware
		2714	dd (CTRL_VMWARE_UNK1 shl 16)+VID_VMWARE,msg_VMWARE_UNK1, AZX_DRIVER_GENERIC
		2715
		2716	dd 0 ;terminator
		2717
		2718
		2719	version dd (5 shl 16) or (API_VERSION and 0xFFFF)
		2720
		2721	msg_Intel db 'Intel ',0
		2722	msg_INTEL_CPT db 'Cougar Point',13,10,0
		2723	msg_INTEL_PGB db 'Patsburg',13,10,0
		2724	msg_INTEL_PPT1 db 'Panther Point',13,10,0
		2725	msg_INTEL_LPT db 'Lynx Point',13,10,0
		2726	msg_INTEL_HPT db 'Haswell',13,10,0
		2727	msg_INTEL_82801F db '82801F',13,10,0
		2728	msg_INTEL_63XXESB db '631x/632xESB',13,10,0
		2729	msg_INTEL_82801G db '82801G', 13,10,0
		2730	msg_INTEL_82801H db '82801H', 13,10,0
		2731	msg_INTEL_82801I db '82801I', 13,10,0
		2732	msg_INTEL_82801JI db '82801JI',13,10,0
		2733	msg_INTEL_82801JD db '82801JD',13,10,0
		2734	msg_INTEL_PCH db 'PCH',13,10,0
		2735	msg_INTEL_PCH2 db 'PCH2',13,10,0
		2736	msg_INTEL_SCH db 'Poulsbo',13,10,0
		2737	msg_INTEL_SCH2 db 'Oaktrail',13,10,0
		2738	msg_INTEL_82801_UNK1 db '82801_UNK1', 13,10,0
		2739	msg_INTEL_82801_UNK2 db '82801_UNK2', 13,10,0
		2740
		2741	msg_NVidia db 'NVidia ',0
		2742	msg_NVIDIA_MCP51 db 'MCP51', 13,10,0
		2743	msg_NVIDIA_MCP55 db 'MCP55', 13,10,0
		2744	msg_NVIDIA_MCP61 db 'MCP61', 13,10,0
		2745	msg_NVIDIA_MCP65 db 'MCP65', 13,10,0
		2746	msg_NVIDIA_MCP67 db 'MCP67', 13,10,0
		2747	msg_NVIDIA_MCP73 db 'MCP73', 13,10,0
		2748	msg_NVIDIA_MCP78 db 'MCP78', 13,10,0
		2749	msg_NVIDIA_MCP79 db 'MCP79', 13,10,0
		2750	msg_NVIDIA_MCP89 db 'MCP89', 13,10,0
		2751	msg_NVIDIA_0BE2 db '(0x0be2)', 13,10,0
		2752	msg_NVIDIA_0BE3 db '(0x0be3)', 13,10,0
		2753	msg_NVIDIA_0BE4 db '(0x0be4)', 13,10,0
		2754	msg_NVIDIA_GT100 db 'GT100', 13,10,0
		2755	msg_NVIDIA_GT104 db 'GT104', 13,10,0
		2756	msg_NVIDIA_GT106 db 'GT106', 13,10,0
		2757	msg_NVIDIA_GT108 db 'GT108', 13,10,0
		2758	msg_NVIDIA_GT116 db 'GT116', 13,10,0
		2759	msg_NVIDIA_GF119 db 'GF119', 13,10,0
		2760	msg_NVIDIA_GF110 db 'GF110', 13,10,0
		2761
		2762	msg_ATI db 'ATI ',0
		2763	msg_ATI_SB450 db 'SB450', 13,10,0
		2764	msg_ATI_SB600 db 'SB600', 13,10,0
		2765
		2766	msg_ATI_HDMI db 'ATI HDMI ',0
		2767	msg_ATI_RS600 db 'RS600', 13,10,0
		2768	msg_ATI_RS690 db 'RS690', 13,10,0
		2769	msg_ATI_RS780 db 'RS780', 13,10,0
		2770	msg_ATI_RS_UNK1 db 'RS_UNK1', 13,10,0
		2771	msg_ATI_R600 db 'R600', 13,10,0
		2772	msg_ATI_RV610 db 'RV610', 13,10,0
		2773	msg_ATI_RV620 db 'RV620', 13,10,0
		2774	msg_ATI_RV630 db 'RV630', 13,10,0
		2775	msg_ATI_RV635 db 'RV635', 13,10,0
		2776	msg_ATI_RV670 db 'RV670', 13,10,0
		2777	msg_ATI_RV710 db 'RV710', 13,10,0
		2778	msg_ATI_RV730 db 'RV730', 13,10,0
		2779	msg_ATI_RV740 db 'RV740', 13,10,0
		2780	msg_ATI_RV770 db 'RV770', 13,10,0
		2781
		2782	msg_AMD db 'AMD ',0
		2783	msg_AMD_HUDSON db 'Hudson', 13,10,0
		2784
		2785	msg_VIA db 'VIA ',0
		2786	msg_VIA_VT82XX db 'VT8251/8237A', 13,10,0
		2787	msg_VIA_VT61XX db 'GFX VT6122/VX11', 13,10,0
		2788	msg_VIA_VT71XX db 'GFX VT7122/VX900', 13,10,0
		2789
		2790	msg_SIS db 'SIS ',0
		2791	msg_SIS_966 db '966', 13,10,0
		2792
		2793	msg_ULI db 'ULI ',0
		2794	msg_ULI_M5461 db 'M5461', 13,10,0
		2795
		2796	msg_TERA db 'Teradici ',0
		2797	msg_TERA_UNK1 db 'UNK1', 13,10,0
		2798
		2799	msg_CREATIVE db 'Creative ',0
		2800	msg_CREATIVE_CA0110_IBG db 'CA0110-IBG',13,10,0 ;SB X-Fi Xtreme Audio
		2801	msg_CREATIVE_SOUND_CORE3D db 'Sound Core3D'
		2802
		2803	msg_RDC db 'RDC ',0
		2804	msg_RDC_R3010 db 'R3010', 13,10,0
		2805
		2806	msg_VMWARE db 'VMware ',0
		2807	msg_VMWARE_UNK1 db 'UNK1', 13,10,0
		2808
		2809	szKernel db 'KERNEL',0
		2810	sz_sound_srv db 'SOUND',0
		2811
		2812	msgInit db 'detect hardware...',13,10,0
		2813	msgFail db 'device not found',13,10,0
		2814	msgAttchIRQ db 'IRQ line not supported', 13,10,0
		2815	msgInvIRQ db 'IRQ line not assigned or invalid', 13,10,0
		2816	msgPlay db 'start play', 13,10,0
		2817	msgStop db 'stop play', 13,10,0
		2818	msgSetChannelVolume db 'Set Channel Volume', 13,10,0
		2819	msgIRQ db 'HDA IRQ', 13,10,0
		2820	msgInitCtrl db 'init controller',13,10,0
		2821	msgPrimBuff db 'create primary buffer ...',0
		2822	msgDone db 'done',13,10,0
		2823	msgRemap db 'Remap IRQ',13,10,0
		2824	msgOk db 'service installed',13,10,0
		2825	msgCold db 'cold reset',13,10,0
		2826	msgHDARFail db 'controller not ready',13,10,0
		2827	msgCFail db 'codec not ready',13,10,0
		2828	msgResetOk db 'reset complete',13,10,0
		2829	msgPciCmd db 'PCI command ',0
		2830	msgPciStat db 'PCI status ',0
		2831	msgHDALowMMIo db 'lower mmio base ',0
		2832	msgHDAUpMMIo db 'upper mmio base ',0
		2833	msgIrqMap db 'HDA irq map as ',0
		2834
		2835	;Asper [
		2836	if DEBUG
		2837	msgCodecMask db 'codec_mask = ',0
		2838	msgNoCodecsFound db 'no codecs found!',13,10,0
		2839	msgHDASnoopDisabled db 'HDA snoop disabled, enabling ... ',0
		2840	msg_OK db 'OK',13,10,0
		2841	msg_Fail db 'Failed',13,10,0
		2842	msgSpuriousResponce db 'spurious responce ',0
		2843	emsgInvalidAFGSubtree db 'Invalid AFG subtree',13,10,0
		2844	emsgConnListNotAvailable db 'connection list not available for ',0
		2845	msgUnmuteOut db 'UNMUTE OUT: NID=',0
		2846	msgUnmuteIn db 'UNMUTE IN: NID=',0
		2847	msgGetResponceTimeout db 'get_response timeout: ',0
		2848	msgVal db ' val=',0
		2849	emsgBusResetFatalComm db 'resetting BUS due to fatal communication error',13,10,0
		2850	msgCodecOK db 'codec probed OK',13,10,0
		2851	msgCodecError db 'codec probe error disabling it...',13,10,0
		2852	emsgNoAFGorMFGFound db 'no AFG or MFG node found',13,10,0
		2853	emsgNoMem db 'hda_codec: cannot malloc',13,10,0
		2854	msgConnect db 'CONNECT: NID=',0
		2855	msgIdx db ' IDX=',0
		2856	msgSkipDigitalOutNode db 'Skip Digital OUT node ',0
		2857	msgAudOutFound db 'AUD_OUT found ',0
		2858	emsgNoParserAvailable db 'No codec parser is available',13,10,0
		2859	emsgNoProperOutputPathFound db 'hda_generic: no proper output path found',13,10,0
		2860	emsgInvConnList db 'hda_codec: invalid CONNECT_LIST verb ',0
		2861	emsgInvDepRangeVal db 'hda_codec: invalid dep_range_val ',0
		2862	emsgTooManyConns db 'Too many connections',13,10,0
		2863	emsgNoVolCtrl db 'No volume control',13,10,0
		2864	msgHDACodecSetupStream db 'hda_codec_setup_stream: NID=',0
		2865	msgStream db 'stream=',0
		2866	msgChannel db 'channel=',0
		2867	msgFormat db 'format=',0
		2868
		2869	msgPollingCodecOnce db 'polling the codec once',13,10,0 ;Asper~
		2870	msgSwitchToPollMode db 'switching to polling mode',13,10,0 ;Asper~
		2871
		2872	msgUnsolEvent db 'Unsolicited event!',13,10,0
		2873	strSemicolon db ':',0
		2874	msgSETUP_FG_NODES db 'Setup FG nodes = start_nid:total_nodes = ',0
		2875	msgFG_TYPE db 'FG type = ',0
		2876	msgPinCfgs db 'Pin configurations:',13,10,0
		2877	msgWCaps db 'Widget capabilities:',13,10,0
		2878	msgCAd db 'CAd = ',0
		2879	msgTCSEL db 'PCI TCSEL ',0
		2880	msgTV db 'HDA test version ',TEST_VERSION_NUMBER,13,10,0
		2881	msgGCap db 'GCAP = ',0
		2882	end if
		2883
		2884	if USE_SINGLE_MODE
		2885	msgSingleMode db 'Single mode !',13,10,0
		2886	msgIRS db 'IRS=',0
		2887	msgSendCmdTimeout db 'send_cmd timeout: IRS=',0
		2888	else
		2889	msgNormalMode db 'Normal mode !',13,10,0
		2890	end if
		2891
		2892	if DEBUG
		2893	msgYAHOO2 db 'YAHOO2: ',0
		2894	msgMaxVolume db 'MaxVolume: ',0
		2895	msgNewVolume db 'NewVolume: ',0
		2896
		2897	msgVerbQuery db 'Q: ',0
		2898	msgVerbAnswer db 'A: ',0
		2899	msgPin_Nid db 'Pin Nid = ',0
		2900	msgPin_Ctl db 'Pin Control = ',0
		2901	msgPin_Caps db 'Pin Capabilities = ',0
		2902	msgDef_Cfg db 'Pin def_cfg = ',0
		2903	msgAmp_Out_Caps db 'Pin Amp Out caps = ',0
		2904	msgAmpVal db 'Amp val = ',0
		2905	msgEnableEAPD db 'Enable EAPD: NID=',0
		2906	msgBeeperNid db 'Beeper found: NID=',0
		2907	msgBeeperValue db 'Beeper initial value: ',0
		2908	msgBeepNow db 'Beep!',13,10,0
		2909	end if
		2910
		2911	;] Asper
		2912
		2913
		2914	section '.data' data readable writable align 16
		2915
		2916
		2917	codec CODEC
		2918	ctrl AC_CNTRL
		2919
		2920	;Asper: BDL must be aligned to 128 according to HDA specification.
		2921	pcmout_bdl rd 1
		2922	buff_list rd 32
		2923
		2924	driver_type rd 1

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(root)/drivers/audio/intel_hda/intel_hda.asm – Rev 3170