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| Rev | Author | Line No. | Line |
|---|---|---|---|
| 9503 | turbocat | 1 | #ifndef _GEODE_PCI_ |
| 2 | #define _GEODE_PCI_ |
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| 981 | serge | 3 | |
| 1692 | serge | 4 | typedef int Bool; |
| 9503 | turbocat | 5 | typedef unsigned char u8_t; |
| 6 | typedef unsigned short u16_t; |
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| 7 | typedef unsigned int u32_t; |
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| 981 | serge | 8 | |
| 1692 | serge | 9 | #define TRUE 1 |
| 10 | #define FALSE 0 |
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| 11 | |||
| 981 | serge | 12 | #pragma pack(push, 1) |
| 13 | typedef struct |
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| 14 | { |
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| 15 | u16_t device; |
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| 16 | u16_t ChipSet; |
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| 17 | }PciChipset_t; |
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| 18 | #pragma pack(pop) |
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| 19 | |||
| 20 | #define VENDOR_ATI 0x1002 |
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| 21 | |||
| 22 | |||
| 23 | #define PCI_CLASS_DISPLAY_VGA 0x0300 |
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| 24 | /* |
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| 25 | * Under PCI, each device has 256 bytes of configuration address space, |
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| 26 | * of which the first 64 bytes are standardized as follows: |
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| 27 | */ |
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| 28 | #define PCI_VENDOR_ID 0x00 /* 16 bits */ |
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| 29 | #define PCI_DEVICE_ID 0x02 /* 16 bits */ |
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| 30 | #define PCI_COMMAND 0x04 /* 16 bits */ |
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| 31 | #define PCI_COMMAND_IO 0x01 /* Enable response in I/O space */ |
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| 32 | #define PCI_COMMAND_MEMORY 0x02 /* Enable response in Memory space */ |
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| 33 | #define PCI_COMMAND_MASTER 0x04 /* Enable bus mastering */ |
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| 34 | #define PCI_COMMAND_SPECIAL 0x08 /* Enable response to special cycles */ |
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| 35 | #define PCI_COMMAND_INVALIDATE 0x10 /* Use memory write and invalidate */ |
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| 36 | #define PCI_COMMAND_VGA_PALETTE 0x20 /* Enable palette snooping */ |
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| 37 | #define PCI_COMMAND_PARITY 0x40 /* Enable parity checking */ |
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| 38 | #define PCI_COMMAND_WAIT 0x80 /* Enable address/data stepping */ |
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| 39 | #define PCI_COMMAND_SERR 0x100 /* Enable SERR */ |
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| 40 | #define PCI_COMMAND_FAST_BACK 0x200 /* Enable back-to-back writes */ |
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| 41 | #define PCI_COMMAND_INTX_DISABLE 0x400 /* INTx Emulation Disable */ |
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| 42 | |||
| 43 | #define PCI_STATUS 0x06 /* 16 bits */ |
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| 44 | #define PCI_STATUS_CAP_LIST 0x10 /* Support Capability List */ |
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| 45 | #define PCI_STATUS_66MHZ 0x20 /* Support 66 Mhz PCI 2.1 bus */ |
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| 46 | #define PCI_STATUS_UDF 0x40 /* Support User Definable Features [obsolete] */ |
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| 47 | #define PCI_STATUS_FAST_BACK 0x80 /* Accept fast-back to back */ |
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| 48 | #define PCI_STATUS_PARITY 0x100 /* Detected parity error */ |
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| 49 | #define PCI_STATUS_DEVSEL_MASK 0x600 /* DEVSEL timing */ |
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| 50 | #define PCI_STATUS_DEVSEL_FAST 0x000 |
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| 51 | #define PCI_STATUS_DEVSEL_MEDIUM 0x200 |
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| 52 | #define PCI_STATUS_DEVSEL_SLOW 0x400 |
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| 53 | #define PCI_STATUS_SIG_TARGET_ABORT 0x800 /* Set on target abort */ |
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| 54 | #define PCI_STATUS_REC_TARGET_ABORT 0x1000 /* Master ack of " */ |
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| 55 | #define PCI_STATUS_REC_MASTER_ABORT 0x2000 /* Set on master abort */ |
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| 56 | #define PCI_STATUS_SIG_SYSTEM_ERROR 0x4000 /* Set when we drive SERR */ |
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| 57 | #define PCI_STATUS_DETECTED_PARITY 0x8000 /* Set on parity error */ |
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| 58 | |||
| 59 | #define PCI_CLASS_REVISION 0x08 /* High 24 bits are class, low 8 revision */ |
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| 60 | #define PCI_REVISION_ID 0x08 /* Revision ID */ |
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| 61 | #define PCI_CLASS_PROG 0x09 /* Reg. Level Programming Interface */ |
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| 62 | #define PCI_CLASS_DEVICE 0x0a /* Device class */ |
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| 63 | |||
| 64 | #define PCI_CACHE_LINE_SIZE 0x0c /* 8 bits */ |
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| 65 | #define PCI_LATENCY_TIMER 0x0d /* 8 bits */ |
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| 66 | #define PCI_HEADER_TYPE 0x0e /* 8 bits */ |
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| 67 | #define PCI_HEADER_TYPE_NORMAL 0 |
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| 68 | #define PCI_HEADER_TYPE_BRIDGE 1 |
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| 69 | #define PCI_HEADER_TYPE_CARDBUS 2 |
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| 70 | |||
| 71 | #define PCI_BIST 0x0f /* 8 bits */ |
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| 72 | #define PCI_BIST_CODE_MASK 0x0f /* Return result */ |
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| 73 | #define PCI_BIST_START 0x40 /* 1 to start BIST, 2 secs or less */ |
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| 74 | #define PCI_BIST_CAPABLE 0x80 /* 1 if BIST capable */ |
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| 75 | |||
| 76 | #define PCI_CAPABILITY_LIST 0x34 /* Offset of first capability list entry */ |
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| 77 | #define PCI_CB_CAPABILITY_LIST 0x14 |
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| 78 | /* Capability lists */ |
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| 79 | |||
| 80 | #define PCI_CAP_LIST_ID 0 /* Capability ID */ |
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| 81 | #define PCI_CAP_ID_PM 0x01 /* Power Management */ |
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| 82 | #define PCI_CAP_ID_AGP 0x02 /* Accelerated Graphics Port */ |
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| 83 | #define PCI_CAP_ID_VPD 0x03 /* Vital Product Data */ |
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| 84 | #define PCI_CAP_ID_SLOTID 0x04 /* Slot Identification */ |
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| 85 | #define PCI_CAP_ID_MSI 0x05 /* Message Signalled Interrupts */ |
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| 86 | #define PCI_CAP_ID_CHSWP 0x06 /* CompactPCI HotSwap */ |
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| 87 | #define PCI_CAP_ID_PCIX 0x07 /* PCI-X */ |
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| 88 | #define PCI_CAP_ID_HT 0x08 /* HyperTransport */ |
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| 89 | #define PCI_CAP_ID_VNDR 0x09 /* Vendor specific capability */ |
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| 90 | #define PCI_CAP_ID_SHPC 0x0C /* PCI Standard Hot-Plug Controller */ |
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| 91 | #define PCI_CAP_ID_EXP 0x10 /* PCI Express */ |
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| 92 | #define PCI_CAP_ID_MSIX 0x11 /* MSI-X */ |
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| 93 | #define PCI_CAP_LIST_NEXT 1 /* Next capability in the list */ |
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| 94 | #define PCI_CAP_FLAGS 2 /* Capability defined flags (16 bits) */ |
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| 95 | #define PCI_CAP_SIZEOF 4 |
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| 96 | |||
| 97 | |||
| 98 | /* AGP registers */ |
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| 99 | |||
| 100 | #define PCI_AGP_VERSION 2 /* BCD version number */ |
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| 101 | #define PCI_AGP_RFU 3 /* Rest of capability flags */ |
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| 102 | #define PCI_AGP_STATUS 4 /* Status register */ |
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| 103 | #define PCI_AGP_STATUS_RQ_MASK 0xff000000 /* Maximum number of requests - 1 */ |
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| 104 | #define PCI_AGP_STATUS_SBA 0x0200 /* Sideband addressing supported */ |
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| 105 | #define PCI_AGP_STATUS_64BIT 0x0020 /* 64-bit addressing supported */ |
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| 106 | #define PCI_AGP_STATUS_FW 0x0010 /* FW transfers supported */ |
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| 107 | #define PCI_AGP_STATUS_RATE4 0x0004 /* 4x transfer rate supported */ |
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| 108 | #define PCI_AGP_STATUS_RATE2 0x0002 /* 2x transfer rate supported */ |
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| 109 | #define PCI_AGP_STATUS_RATE1 0x0001 /* 1x transfer rate supported */ |
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| 110 | #define PCI_AGP_COMMAND 8 /* Control register */ |
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| 111 | #define PCI_AGP_COMMAND_RQ_MASK 0xff000000 /* Master: Maximum number of requests */ |
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| 112 | #define PCI_AGP_COMMAND_SBA 0x0200 /* Sideband addressing enabled */ |
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| 113 | #define PCI_AGP_COMMAND_AGP 0x0100 /* Allow processing of AGP transactions */ |
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| 114 | #define PCI_AGP_COMMAND_64BIT 0x0020 /* Allow processing of 64-bit addresses */ |
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| 115 | #define PCI_AGP_COMMAND_FW 0x0010 /* Force FW transfers */ |
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| 116 | #define PCI_AGP_COMMAND_RATE4 0x0004 /* Use 4x rate */ |
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| 117 | #define PCI_AGP_COMMAND_RATE2 0x0002 /* Use 2x rate */ |
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| 118 | #define PCI_AGP_COMMAND_RATE1 0x0001 /* Use 1x rate */ |
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| 119 | #define PCI_AGP_SIZEOF 12 |
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| 120 | |||
| 121 | |||
| 122 | #define PCI_MAP_REG_START 0x10 |
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| 123 | #define PCI_MAP_REG_END 0x28 |
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| 124 | #define PCI_MAP_ROM_REG 0x30 |
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| 125 | |||
| 126 | #define PCI_MAP_MEMORY 0x00000000 |
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| 127 | #define PCI_MAP_IO 0x00000001 |
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| 128 | |||
| 129 | #define PCI_MAP_MEMORY_TYPE 0x00000007 |
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| 130 | #define PCI_MAP_IO_TYPE 0x00000003 |
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| 131 | |||
| 132 | #define PCI_MAP_MEMORY_TYPE_32BIT 0x00000000 |
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| 133 | #define PCI_MAP_MEMORY_TYPE_32BIT_1M 0x00000002 |
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| 134 | #define PCI_MAP_MEMORY_TYPE_64BIT 0x00000004 |
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| 135 | #define PCI_MAP_MEMORY_TYPE_MASK 0x00000006 |
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| 136 | #define PCI_MAP_MEMORY_CACHABLE 0x00000008 |
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| 137 | #define PCI_MAP_MEMORY_ATTR_MASK 0x0000000e |
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| 138 | #define PCI_MAP_MEMORY_ADDRESS_MASK 0xfffffff0 |
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| 139 | |||
| 140 | #define PCI_MAP_IO_ATTR_MASK 0x00000003 |
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| 141 | |||
| 142 | #define PCI_MAP_IS_IO(b) ((b) & PCI_MAP_IO) |
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| 143 | #define PCI_MAP_IS_MEM(b) (!PCI_MAP_IS_IO(b)) |
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| 144 | |||
| 145 | #define PCI_MAP_IS64BITMEM(b) \ |
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| 146 | (((b) & PCI_MAP_MEMORY_TYPE_MASK) == PCI_MAP_MEMORY_TYPE_64BIT) |
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| 147 | |||
| 148 | #define PCIGETMEMORY(b) ((b) & PCI_MAP_MEMORY_ADDRESS_MASK) |
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| 149 | #define PCIGETMEMORY64HIGH(b) (*((CARD32*)&b + 1)) |
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| 150 | #define PCIGETMEMORY64(b) \ |
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| 151 | (PCIGETMEMORY(b) | ((CARD64)PCIGETMEMORY64HIGH(b) << 32)) |
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| 152 | |||
| 153 | #define PCI_MAP_IO_ADDRESS_MASK 0xfffffffc |
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| 154 | |||
| 155 | #define PCIGETIO(b) ((b) & PCI_MAP_IO_ADDRESS_MASK) |
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| 156 | |||
| 157 | #define PCI_MAP_ROM_DECODE_ENABLE 0x00000001 |
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| 158 | #define PCI_MAP_ROM_ADDRESS_MASK 0xfffff800 |
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| 159 | |||
| 160 | #define PCIGETROM(b) ((b) & PCI_MAP_ROM_ADDRESS_MASK) |
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| 161 | |||
| 162 | |||
| 163 | #ifndef PCI_DOM_MASK |
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| 164 | # define PCI_DOM_MASK 0x0ffu |
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| 165 | #endif |
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| 166 | #define PCI_DOMBUS_MASK (((PCI_DOM_MASK) << 8) | 0x0ffu) |
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| 167 | |||
| 168 | #define PCI_MAKE_TAG(b,d,f) ((((b) & (PCI_DOMBUS_MASK)) << 16) | \ |
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| 169 | (((d) & 0x00001fu) << 11) | \ |
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| 170 | (((f) & 0x000007u) << 8)) |
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| 171 | |||
| 172 | #define PCI_BUS_FROM_TAG(tag) (((tag) >> 16) & (PCI_DOMBUS_MASK)) |
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| 173 | #define PCI_DEV_FROM_TAG(tag) (((tag) & 0x0000f800u) >> 11) |
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| 174 | #define PCI_FUNC_FROM_TAG(tag) (((tag) & 0x00000700u) >> 8) |
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| 175 | #define PCI_DFN_FROM_TAG(tag) (((tag) & 0x0000ff00u) >> 8) |
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| 176 | |||
| 177 | |||
| 178 | typedef unsigned int PCITAG; |
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| 179 | |||
| 180 | extern inline PCITAG |
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| 181 | pciTag(int busnum, int devnum, int funcnum) |
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| 182 | { |
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| 183 | return(PCI_MAKE_TAG(busnum,devnum,funcnum)); |
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| 184 | } |
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| 185 | |||
| 186 | const PciChipset_t *PciDevMatch(u16_t dev,const PciChipset_t *list); |
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| 187 | u32_t pciGetBaseSize(int bus, int devfn, int index, Bool destructive, Bool *min); |
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| 188 | |||
| 189 | #define PCI_ANY_ID (~0) |
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| 190 | |||
| 191 | #define for_each_pci_dev(d) while ((d = pci_get_device(PCI_ANY_ID, PCI_ANY_ID, d))!=-1) |
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| 9503 | turbocat | 192 | |
| 193 | #endif // _GEODE_PCI_ |