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/* Definitions of target machine for GCC for IA-32.

   Copyright (C) 1988-2015 Free Software Foundation, Inc.

This file is part of GCC.

GCC is free software; you can redistribute it and/or modify

it under the terms of the GNU General Public License as published by

the Free Software Foundation; either version 3, or (at your option)

any later version.

GCC is distributed in the hope that it will be useful,

but WITHOUT ANY WARRANTY; without even the implied warranty of

MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the

GNU General Public License for more details.

Under Section 7 of GPL version 3, you are granted additional

permissions described in the GCC Runtime Library Exception, version

3.1, as published by the Free Software Foundation.

You should have received a copy of the GNU General Public License and

a copy of the GCC Runtime Library Exception along with this program;

see the files COPYING3 and COPYING.RUNTIME respectively.  If not, see

.  */

/* The purpose of this file is to define the characteristics of the i386,

   independent of assembler syntax or operating system.

   Three other files build on this one to describe a specific assembler syntax:

   bsd386.h, att386.h, and sun386.h.

   The actual tm.h file for a particular system should include

   this file, and then the file for the appropriate assembler syntax.

   Many macros that specify assembler syntax are omitted entirely from

   this file because they really belong in the files for particular

   assemblers.  These include RP, IP, LPREFIX, PUT_OP_SIZE, USE_STAR,

   ADDR_BEG, ADDR_END, PRINT_IREG, PRINT_SCALE, PRINT_B_I_S, and many

   that start with ASM_ or end in ASM_OP.  */

/* Redefines for option macros.  */

#define TARGET_64BIT	TARGET_ISA_64BIT

#define TARGET_64BIT_P(x)	TARGET_ISA_64BIT_P(x)

#define TARGET_MMX	TARGET_ISA_MMX

#define TARGET_MMX_P(x)	TARGET_ISA_MMX_P(x)

#define TARGET_3DNOW	TARGET_ISA_3DNOW

#define TARGET_3DNOW_P(x)	TARGET_ISA_3DNOW_P(x)

#define TARGET_3DNOW_A	TARGET_ISA_3DNOW_A

#define TARGET_3DNOW_A_P(x)	TARGET_ISA_3DNOW_A_P(x)

#define TARGET_SSE	TARGET_ISA_SSE

#define TARGET_SSE_P(x)	TARGET_ISA_SSE_P(x)

#define TARGET_SSE2	TARGET_ISA_SSE2

#define TARGET_SSE2_P(x)	TARGET_ISA_SSE2_P(x)

#define TARGET_SSE3	TARGET_ISA_SSE3

#define TARGET_SSE3_P(x)	TARGET_ISA_SSE3_P(x)

#define TARGET_SSSE3	TARGET_ISA_SSSE3

#define TARGET_SSSE3_P(x)	TARGET_ISA_SSSE3_P(x)

#define TARGET_SSE4_1	TARGET_ISA_SSE4_1

#define TARGET_SSE4_1_P(x)	TARGET_ISA_SSE4_1_P(x)

#define TARGET_SSE4_2	TARGET_ISA_SSE4_2

#define TARGET_SSE4_2_P(x)	TARGET_ISA_SSE4_2_P(x)

#define TARGET_AVX	TARGET_ISA_AVX

#define TARGET_AVX_P(x)	TARGET_ISA_AVX_P(x)

#define TARGET_AVX2	TARGET_ISA_AVX2

#define TARGET_AVX2_P(x)	TARGET_ISA_AVX2_P(x)

#define TARGET_AVX512F	TARGET_ISA_AVX512F

#define TARGET_AVX512F_P(x)	TARGET_ISA_AVX512F_P(x)

#define TARGET_AVX512PF	TARGET_ISA_AVX512PF

#define TARGET_AVX512PF_P(x)	TARGET_ISA_AVX512PF_P(x)

#define TARGET_AVX512ER	TARGET_ISA_AVX512ER

#define TARGET_AVX512ER_P(x)	TARGET_ISA_AVX512ER_P(x)

#define TARGET_AVX512CD	TARGET_ISA_AVX512CD

#define TARGET_AVX512CD_P(x)	TARGET_ISA_AVX512CD_P(x)

#define TARGET_AVX512DQ	TARGET_ISA_AVX512DQ

#define TARGET_AVX512DQ_P(x)	TARGET_ISA_AVX512DQ_P(x)

#define TARGET_AVX512BW	TARGET_ISA_AVX512BW

#define TARGET_AVX512BW_P(x)	TARGET_ISA_AVX512BW_P(x)

#define TARGET_AVX512VL	TARGET_ISA_AVX512VL

#define TARGET_AVX512VL_P(x)	TARGET_ISA_AVX512VL_P(x)

#define TARGET_AVX512VBMI	TARGET_ISA_AVX512VBMI

#define TARGET_AVX512VBMI_P(x)	TARGET_ISA_AVX512VBMI_P(x)

#define TARGET_AVX512IFMA	TARGET_ISA_AVX512IFMA

#define TARGET_AVX512IFMA_P(x)	TARGET_ISA_AVX512IFMA_P(x)

#define TARGET_FMA	TARGET_ISA_FMA

#define TARGET_FMA_P(x)	TARGET_ISA_FMA_P(x)

#define TARGET_SSE4A	TARGET_ISA_SSE4A

#define TARGET_SSE4A_P(x)	TARGET_ISA_SSE4A_P(x)

#define TARGET_FMA4	TARGET_ISA_FMA4

#define TARGET_FMA4_P(x)	TARGET_ISA_FMA4_P(x)

#define TARGET_XOP	TARGET_ISA_XOP

#define TARGET_XOP_P(x)	TARGET_ISA_XOP_P(x)

#define TARGET_LWP	TARGET_ISA_LWP

#define TARGET_LWP_P(x)	TARGET_ISA_LWP_P(x)

#define TARGET_ROUND	TARGET_ISA_ROUND

#define TARGET_ABM	TARGET_ISA_ABM

#define TARGET_ABM_P(x)	TARGET_ISA_ABM_P(x)

#define TARGET_BMI	TARGET_ISA_BMI

#define TARGET_BMI_P(x)	TARGET_ISA_BMI_P(x)

#define TARGET_BMI2	TARGET_ISA_BMI2

#define TARGET_BMI2_P(x)	TARGET_ISA_BMI2_P(x)

#define TARGET_LZCNT	TARGET_ISA_LZCNT

#define TARGET_LZCNT_P(x)	TARGET_ISA_LZCNT_P(x)

#define TARGET_TBM	TARGET_ISA_TBM

#define TARGET_TBM_P(x)	TARGET_ISA_TBM_P(x)

#define TARGET_POPCNT	TARGET_ISA_POPCNT

#define TARGET_POPCNT_P(x)	TARGET_ISA_POPCNT_P(x)

#define TARGET_SAHF	TARGET_ISA_SAHF

#define TARGET_SAHF_P(x)	TARGET_ISA_SAHF_P(x)

#define TARGET_MOVBE	TARGET_ISA_MOVBE

#define TARGET_MOVBE_P(x)	TARGET_ISA_MOVBE_P(x)

#define TARGET_CRC32	TARGET_ISA_CRC32

#define TARGET_CRC32_P(x)	TARGET_ISA_CRC32_P(x)

#define TARGET_AES	TARGET_ISA_AES

#define TARGET_AES_P(x)	TARGET_ISA_AES_P(x)

#define TARGET_SHA	TARGET_ISA_SHA

#define TARGET_SHA_P(x)	TARGET_ISA_SHA_P(x)

#define TARGET_CLFLUSHOPT	TARGET_ISA_CLFLUSHOPT

#define TARGET_CLFLUSHOPT_P(x)	TARGET_ISA_CLFLUSHOPT_P(x)

#define TARGET_XSAVEC	TARGET_ISA_XSAVEC

#define TARGET_XSAVEC_P(x)	TARGET_ISA_XSAVEC_P(x)

#define TARGET_XSAVES	TARGET_ISA_XSAVES

#define TARGET_XSAVES_P(x)	TARGET_ISA_XSAVES_P(x)

#define TARGET_PCLMUL	TARGET_ISA_PCLMUL

#define TARGET_PCLMUL_P(x)	TARGET_ISA_PCLMUL_P(x)

#define TARGET_CMPXCHG16B	TARGET_ISA_CX16

#define TARGET_CMPXCHG16B_P(x)	TARGET_ISA_CX16_P(x)

#define TARGET_FSGSBASE	TARGET_ISA_FSGSBASE

#define TARGET_FSGSBASE_P(x)	TARGET_ISA_FSGSBASE_P(x)

#define TARGET_RDRND	TARGET_ISA_RDRND

#define TARGET_RDRND_P(x)	TARGET_ISA_RDRND_P(x)

#define TARGET_F16C	TARGET_ISA_F16C

#define TARGET_F16C_P(x)	TARGET_ISA_F16C_P(x)

#define TARGET_RTM	TARGET_ISA_RTM

#define TARGET_RTM_P(x)	TARGET_ISA_RTM_P(x)

#define TARGET_HLE	TARGET_ISA_HLE

#define TARGET_HLE_P(x)	TARGET_ISA_HLE_P(x)

#define TARGET_RDSEED	TARGET_ISA_RDSEED

#define TARGET_RDSEED_P(x)	TARGET_ISA_RDSEED_P(x)

#define TARGET_PRFCHW	TARGET_ISA_PRFCHW

#define TARGET_PRFCHW_P(x)	TARGET_ISA_PRFCHW_P(x)

#define TARGET_ADX	TARGET_ISA_ADX

#define TARGET_ADX_P(x)	TARGET_ISA_ADX_P(x)

#define TARGET_FXSR	TARGET_ISA_FXSR

#define TARGET_FXSR_P(x)	TARGET_ISA_FXSR_P(x)

#define TARGET_XSAVE	TARGET_ISA_XSAVE

#define TARGET_XSAVE_P(x)	TARGET_ISA_XSAVE_P(x)

#define TARGET_XSAVEOPT	TARGET_ISA_XSAVEOPT

#define TARGET_XSAVEOPT_P(x)	TARGET_ISA_XSAVEOPT_P(x)

#define TARGET_PREFETCHWT1	TARGET_ISA_PREFETCHWT1

#define TARGET_PREFETCHWT1_P(x)	TARGET_ISA_PREFETCHWT1_P(x)

#define TARGET_MPX	TARGET_ISA_MPX

#define TARGET_MPX_P(x)	TARGET_ISA_MPX_P(x)

#define TARGET_PCOMMIT	TARGET_ISA_PCOMMIT

#define TARGET_PCOMMIT_P(x)	TARGET_ISA_PCOMMIT_P(x)

#define TARGET_CLWB	TARGET_ISA_CLWB

#define TARGET_CLWB_P(x)	TARGET_ISA_CLWB_P(x)

#define TARGET_MWAITX	TARGET_ISA_MWAITX

#define TARGET_MWAITX_P(x)	TARGET_ISA_MWAITX_P(x)

#define TARGET_LP64	TARGET_ABI_64

#define TARGET_LP64_P(x)	TARGET_ABI_64_P(x)

#define TARGET_X32	TARGET_ABI_X32

#define TARGET_X32_P(x)	TARGET_ABI_X32_P(x)

#define TARGET_16BIT	TARGET_CODE16

#define TARGET_16BIT_P(x)	TARGET_CODE16_P(x)

/* SSE4.1 defines round instructions */

#define	OPTION_MASK_ISA_ROUND	OPTION_MASK_ISA_SSE4_1

#define	TARGET_ISA_ROUND	((ix86_isa_flags & OPTION_MASK_ISA_ROUND) != 0)

#include "config/vxworks-dummy.h"

#include "config/i386/i386-opts.h"

#define MAX_STRINGOP_ALGS 4

/* Specify what algorithm to use for stringops on known size.

   When size is unknown, the UNKNOWN_SIZE alg is used.  When size is

   known at compile time or estimated via feedback, the SIZE array

   is walked in order until MAX is greater then the estimate (or -1

   means infinity).  Corresponding ALG is used then.

   When NOALIGN is true the code guaranting the alignment of the memory

   block is skipped.

   For example initializer:

    {{256, loop}, {-1, rep_prefix_4_byte}}

   will use loop for blocks smaller or equal to 256 bytes, rep prefix will

   be used otherwise.  */

struct stringop_algs

{

  const enum stringop_alg unknown_size;

  const struct stringop_strategy {

    const int max;

    const enum stringop_alg alg;

    int noalign;

  } size [MAX_STRINGOP_ALGS];

};

/* Define the specific costs for a given cpu */

struct processor_costs {

  const int add;		/* cost of an add instruction */

  const int lea;		/* cost of a lea instruction */

  const int shift_var;		/* variable shift costs */

  const int shift_const;	/* constant shift costs */

  const int mult_init[5];	/* cost of starting a multiply

				   in QImode, HImode, SImode, DImode, TImode*/

  const int mult_bit;		/* cost of multiply per each bit set */

  const int divide[5];		/* cost of a divide/mod

				   in QImode, HImode, SImode, DImode, TImode*/

  int movsx;			/* The cost of movsx operation.  */

  int movzx;			/* The cost of movzx operation.  */

  const int large_insn;		/* insns larger than this cost more */

  const int move_ratio;		/* The threshold of number of scalar

				   memory-to-memory move insns.  */

  const int movzbl_load;	/* cost of loading using movzbl */

  const int int_load[3];	/* cost of loading integer registers

				   in QImode, HImode and SImode relative

				   to reg-reg move (2).  */

  const int int_store[3];	/* cost of storing integer register

				   in QImode, HImode and SImode */

  const int fp_move;		/* cost of reg,reg fld/fst */

  const int fp_load[3];		/* cost of loading FP register

				   in SFmode, DFmode and XFmode */

  const int fp_store[3];	/* cost of storing FP register

				   in SFmode, DFmode and XFmode */

  const int mmx_move;		/* cost of moving MMX register.  */

  const int mmx_load[2];	/* cost of loading MMX register

				   in SImode and DImode */

  const int mmx_store[2];	/* cost of storing MMX register

				   in SImode and DImode */

  const int sse_move;		/* cost of moving SSE register.  */

  const int sse_load[3];	/* cost of loading SSE register

				   in SImode, DImode and TImode*/

  const int sse_store[3];	/* cost of storing SSE register

				   in SImode, DImode and TImode*/

  const int mmxsse_to_integer;	/* cost of moving mmxsse register to

				   integer and vice versa.  */

  const int l1_cache_size;	/* size of l1 cache, in kilobytes.  */

  const int l2_cache_size;	/* size of l2 cache, in kilobytes.  */

  const int prefetch_block;	/* bytes moved to cache for prefetch.  */

  const int simultaneous_prefetches; /* number of parallel prefetch

				   operations.  */

  const int branch_cost;	/* Default value for BRANCH_COST.  */

  const int fadd;		/* cost of FADD and FSUB instructions.  */

  const int fmul;		/* cost of FMUL instruction.  */

  const int fdiv;		/* cost of FDIV instruction.  */

  const int fabs;		/* cost of FABS instruction.  */

  const int fchs;		/* cost of FCHS instruction.  */

  const int fsqrt;		/* cost of FSQRT instruction.  */

				/* Specify what algorithm

				   to use for stringops on unknown size.  */

  struct stringop_algs *memcpy, *memset;

  const int scalar_stmt_cost;   /* Cost of any scalar operation, excluding

				   load and store.  */

  const int scalar_load_cost;   /* Cost of scalar load.  */

  const int scalar_store_cost;  /* Cost of scalar store.  */

  const int vec_stmt_cost;      /* Cost of any vector operation, excluding

                                   load, store, vector-to-scalar and

                                   scalar-to-vector operation.  */

  const int vec_to_scalar_cost;    /* Cost of vect-to-scalar operation.  */

  const int scalar_to_vec_cost;    /* Cost of scalar-to-vector operation.  */

  const int vec_align_load_cost;   /* Cost of aligned vector load.  */

  const int vec_unalign_load_cost; /* Cost of unaligned vector load.  */

  const int vec_store_cost;        /* Cost of vector store.  */

  const int cond_taken_branch_cost;    /* Cost of taken branch for vectorizer

					  cost model.  */

  const int cond_not_taken_branch_cost;/* Cost of not taken branch for

					  vectorizer cost model.  */

};

extern const struct processor_costs *ix86_cost;

extern const struct processor_costs ix86_size_cost;

#define ix86_cur_cost() \

  (optimize_insn_for_size_p () ? &ix86_size_cost: ix86_cost)

/* Macros used in the machine description to test the flags.  */

/* configure can arrange to change it.  */

#ifndef TARGET_CPU_DEFAULT

#define TARGET_CPU_DEFAULT PROCESSOR_GENERIC

#endif

#ifndef TARGET_FPMATH_DEFAULT

#define TARGET_FPMATH_DEFAULT \

  (TARGET_64BIT && TARGET_SSE ? FPMATH_SSE : FPMATH_387)

#endif

#ifndef TARGET_FPMATH_DEFAULT_P

#define TARGET_FPMATH_DEFAULT_P(x) \

  (TARGET_64BIT_P(x) && TARGET_SSE_P(x) ? FPMATH_SSE : FPMATH_387)

#endif

#define TARGET_FLOAT_RETURNS_IN_80387 TARGET_FLOAT_RETURNS

#define TARGET_FLOAT_RETURNS_IN_80387_P(x) TARGET_FLOAT_RETURNS_P(x)

/* 64bit Sledgehammer mode.  For libgcc2 we make sure this is a

   compile-time constant.  */

#ifdef IN_LIBGCC2

#undef TARGET_64BIT

#ifdef __x86_64__

#define TARGET_64BIT 1

#else

#define TARGET_64BIT 0

#endif

#else

#ifndef TARGET_BI_ARCH

#undef TARGET_64BIT

#undef TARGET_64BIT_P

#if TARGET_64BIT_DEFAULT

#define TARGET_64BIT 1

#define TARGET_64BIT_P(x) 1

#else

#define TARGET_64BIT 0

#define TARGET_64BIT_P(x) 0

#endif

#endif

#endif

#define HAS_LONG_COND_BRANCH 1

#define HAS_LONG_UNCOND_BRANCH 1

#define TARGET_386 (ix86_tune == PROCESSOR_I386)

#define TARGET_486 (ix86_tune == PROCESSOR_I486)

#define TARGET_PENTIUM (ix86_tune == PROCESSOR_PENTIUM)

#define TARGET_PENTIUMPRO (ix86_tune == PROCESSOR_PENTIUMPRO)

#define TARGET_GEODE (ix86_tune == PROCESSOR_GEODE)

#define TARGET_K6 (ix86_tune == PROCESSOR_K6)

#define TARGET_ATHLON (ix86_tune == PROCESSOR_ATHLON)

#define TARGET_PENTIUM4 (ix86_tune == PROCESSOR_PENTIUM4)

#define TARGET_K8 (ix86_tune == PROCESSOR_K8)

#define TARGET_ATHLON_K8 (TARGET_K8 || TARGET_ATHLON)

#define TARGET_NOCONA (ix86_tune == PROCESSOR_NOCONA)

#define TARGET_CORE2 (ix86_tune == PROCESSOR_CORE2)

#define TARGET_NEHALEM (ix86_tune == PROCESSOR_NEHALEM)

#define TARGET_SANDYBRIDGE (ix86_tune == PROCESSOR_SANDYBRIDGE)

#define TARGET_HASWELL (ix86_tune == PROCESSOR_HASWELL)

#define TARGET_BONNELL (ix86_tune == PROCESSOR_BONNELL)

#define TARGET_SILVERMONT (ix86_tune == PROCESSOR_SILVERMONT)

#define TARGET_KNL (ix86_tune == PROCESSOR_KNL)

#define TARGET_INTEL (ix86_tune == PROCESSOR_INTEL)

#define TARGET_GENERIC (ix86_tune == PROCESSOR_GENERIC)

#define TARGET_AMDFAM10 (ix86_tune == PROCESSOR_AMDFAM10)

#define TARGET_BDVER1 (ix86_tune == PROCESSOR_BDVER1)

#define TARGET_BDVER2 (ix86_tune == PROCESSOR_BDVER2)

#define TARGET_BDVER3 (ix86_tune == PROCESSOR_BDVER3)

#define TARGET_BDVER4 (ix86_tune == PROCESSOR_BDVER4)

#define TARGET_BTVER1 (ix86_tune == PROCESSOR_BTVER1)

#define TARGET_BTVER2 (ix86_tune == PROCESSOR_BTVER2)

/* Feature tests against the various tunings.  */

enum ix86_tune_indices {

#undef DEF_TUNE

#define DEF_TUNE(tune, name, selector) tune,

#include "x86-tune.def"

#undef DEF_TUNE

X86_TUNE_LAST

};

extern unsigned char ix86_tune_features[X86_TUNE_LAST];

#define TARGET_USE_LEAVE	ix86_tune_features[X86_TUNE_USE_LEAVE]

#define TARGET_PUSH_MEMORY	ix86_tune_features[X86_TUNE_PUSH_MEMORY]

#define TARGET_ZERO_EXTEND_WITH_AND \

	ix86_tune_features[X86_TUNE_ZERO_EXTEND_WITH_AND]

#define TARGET_UNROLL_STRLEN	ix86_tune_features[X86_TUNE_UNROLL_STRLEN]

#define TARGET_BRANCH_PREDICTION_HINTS \

	ix86_tune_features[X86_TUNE_BRANCH_PREDICTION_HINTS]

#define TARGET_DOUBLE_WITH_ADD	ix86_tune_features[X86_TUNE_DOUBLE_WITH_ADD]

#define TARGET_USE_SAHF		ix86_tune_features[X86_TUNE_USE_SAHF]

#define TARGET_MOVX		ix86_tune_features[X86_TUNE_MOVX]

#define TARGET_PARTIAL_REG_STALL ix86_tune_features[X86_TUNE_PARTIAL_REG_STALL]

#define TARGET_PARTIAL_FLAG_REG_STALL \

	ix86_tune_features[X86_TUNE_PARTIAL_FLAG_REG_STALL]

#define TARGET_LCP_STALL \

	ix86_tune_features[X86_TUNE_LCP_STALL]

#define TARGET_USE_HIMODE_FIOP	ix86_tune_features[X86_TUNE_USE_HIMODE_FIOP]

#define TARGET_USE_SIMODE_FIOP	ix86_tune_features[X86_TUNE_USE_SIMODE_FIOP]

#define TARGET_USE_MOV0		ix86_tune_features[X86_TUNE_USE_MOV0]

#define TARGET_USE_CLTD		ix86_tune_features[X86_TUNE_USE_CLTD]

#define TARGET_USE_XCHGB	ix86_tune_features[X86_TUNE_USE_XCHGB]

#define TARGET_SPLIT_LONG_MOVES	ix86_tune_features[X86_TUNE_SPLIT_LONG_MOVES]

#define TARGET_READ_MODIFY_WRITE ix86_tune_features[X86_TUNE_READ_MODIFY_WRITE]

#define TARGET_READ_MODIFY	ix86_tune_features[X86_TUNE_READ_MODIFY]

#define TARGET_PROMOTE_QImode	ix86_tune_features[X86_TUNE_PROMOTE_QIMODE]

#define TARGET_FAST_PREFIX	ix86_tune_features[X86_TUNE_FAST_PREFIX]

#define TARGET_SINGLE_STRINGOP	ix86_tune_features[X86_TUNE_SINGLE_STRINGOP]

#define TARGET_MISALIGNED_MOVE_STRING_PRO_EPILOGUES \

	ix86_tune_features[X86_TUNE_MISALIGNED_MOVE_STRING_PRO_EPILOGUES]

#define TARGET_QIMODE_MATH	ix86_tune_features[X86_TUNE_QIMODE_MATH]

#define TARGET_HIMODE_MATH	ix86_tune_features[X86_TUNE_HIMODE_MATH]

#define TARGET_PROMOTE_QI_REGS	ix86_tune_features[X86_TUNE_PROMOTE_QI_REGS]

#define TARGET_PROMOTE_HI_REGS	ix86_tune_features[X86_TUNE_PROMOTE_HI_REGS]

#define TARGET_SINGLE_POP	ix86_tune_features[X86_TUNE_SINGLE_POP]

#define TARGET_DOUBLE_POP	ix86_tune_features[X86_TUNE_DOUBLE_POP]

#define TARGET_SINGLE_PUSH	ix86_tune_features[X86_TUNE_SINGLE_PUSH]

#define TARGET_DOUBLE_PUSH	ix86_tune_features[X86_TUNE_DOUBLE_PUSH]

#define TARGET_INTEGER_DFMODE_MOVES \

	ix86_tune_features[X86_TUNE_INTEGER_DFMODE_MOVES]

#define TARGET_PARTIAL_REG_DEPENDENCY \

	ix86_tune_features[X86_TUNE_PARTIAL_REG_DEPENDENCY]

#define TARGET_SSE_PARTIAL_REG_DEPENDENCY \

	ix86_tune_features[X86_TUNE_SSE_PARTIAL_REG_DEPENDENCY]

#define TARGET_SSE_UNALIGNED_LOAD_OPTIMAL \

	ix86_tune_features[X86_TUNE_SSE_UNALIGNED_LOAD_OPTIMAL]

#define TARGET_SSE_UNALIGNED_STORE_OPTIMAL \

	ix86_tune_features[X86_TUNE_SSE_UNALIGNED_STORE_OPTIMAL]

#define TARGET_SSE_PACKED_SINGLE_INSN_OPTIMAL \

	ix86_tune_features[X86_TUNE_SSE_PACKED_SINGLE_INSN_OPTIMAL]

#define TARGET_SSE_SPLIT_REGS	ix86_tune_features[X86_TUNE_SSE_SPLIT_REGS]

#define TARGET_SSE_TYPELESS_STORES \

	ix86_tune_features[X86_TUNE_SSE_TYPELESS_STORES]

#define TARGET_SSE_LOAD0_BY_PXOR ix86_tune_features[X86_TUNE_SSE_LOAD0_BY_PXOR]

#define TARGET_MEMORY_MISMATCH_STALL \

	ix86_tune_features[X86_TUNE_MEMORY_MISMATCH_STALL]

#define TARGET_PROLOGUE_USING_MOVE \

	ix86_tune_features[X86_TUNE_PROLOGUE_USING_MOVE]

#define TARGET_EPILOGUE_USING_MOVE \

	ix86_tune_features[X86_TUNE_EPILOGUE_USING_MOVE]

#define TARGET_SHIFT1		ix86_tune_features[X86_TUNE_SHIFT1]

#define TARGET_USE_FFREEP	ix86_tune_features[X86_TUNE_USE_FFREEP]

#define TARGET_INTER_UNIT_MOVES_TO_VEC \

	ix86_tune_features[X86_TUNE_INTER_UNIT_MOVES_TO_VEC]

#define TARGET_INTER_UNIT_MOVES_FROM_VEC \

	ix86_tune_features[X86_TUNE_INTER_UNIT_MOVES_FROM_VEC]

#define TARGET_INTER_UNIT_CONVERSIONS \

	ix86_tune_features[X86_TUNE_INTER_UNIT_CONVERSIONS]

#define TARGET_FOUR_JUMP_LIMIT	ix86_tune_features[X86_TUNE_FOUR_JUMP_LIMIT]

#define TARGET_SCHEDULE		ix86_tune_features[X86_TUNE_SCHEDULE]

#define TARGET_USE_BT		ix86_tune_features[X86_TUNE_USE_BT]

#define TARGET_USE_INCDEC	ix86_tune_features[X86_TUNE_USE_INCDEC]

#define TARGET_PAD_RETURNS	ix86_tune_features[X86_TUNE_PAD_RETURNS]

#define TARGET_PAD_SHORT_FUNCTION \

	ix86_tune_features[X86_TUNE_PAD_SHORT_FUNCTION]

#define TARGET_EXT_80387_CONSTANTS \

	ix86_tune_features[X86_TUNE_EXT_80387_CONSTANTS]

#define TARGET_AVOID_VECTOR_DECODE \

	ix86_tune_features[X86_TUNE_AVOID_VECTOR_DECODE]

#define TARGET_TUNE_PROMOTE_HIMODE_IMUL \

	ix86_tune_features[X86_TUNE_PROMOTE_HIMODE_IMUL]

#define TARGET_SLOW_IMUL_IMM32_MEM \

	ix86_tune_features[X86_TUNE_SLOW_IMUL_IMM32_MEM]

#define TARGET_SLOW_IMUL_IMM8	ix86_tune_features[X86_TUNE_SLOW_IMUL_IMM8]

#define	TARGET_MOVE_M1_VIA_OR	ix86_tune_features[X86_TUNE_MOVE_M1_VIA_OR]

#define TARGET_NOT_UNPAIRABLE	ix86_tune_features[X86_TUNE_NOT_UNPAIRABLE]

#define TARGET_NOT_VECTORMODE	ix86_tune_features[X86_TUNE_NOT_VECTORMODE]

#define TARGET_USE_VECTOR_FP_CONVERTS \

	ix86_tune_features[X86_TUNE_USE_VECTOR_FP_CONVERTS]

#define TARGET_USE_VECTOR_CONVERTS \

	ix86_tune_features[X86_TUNE_USE_VECTOR_CONVERTS]

#define TARGET_SLOW_PSHUFB \

	ix86_tune_features[X86_TUNE_SLOW_PSHUFB]

#define TARGET_VECTOR_PARALLEL_EXECUTION \

	ix86_tune_features[X86_TUNE_VECTOR_PARALLEL_EXECUTION]

#define TARGET_AVOID_4BYTE_PREFIXES \

	ix86_tune_features[X86_TUNE_AVOID_4BYTE_PREFIXES]

#define TARGET_FUSE_CMP_AND_BRANCH_32 \

	ix86_tune_features[X86_TUNE_FUSE_CMP_AND_BRANCH_32]

#define TARGET_FUSE_CMP_AND_BRANCH_64 \

	ix86_tune_features[X86_TUNE_FUSE_CMP_AND_BRANCH_64]

#define TARGET_FUSE_CMP_AND_BRANCH \

	(TARGET_64BIT ? TARGET_FUSE_CMP_AND_BRANCH_64 \

	 : TARGET_FUSE_CMP_AND_BRANCH_32)

#define TARGET_FUSE_CMP_AND_BRANCH_SOFLAGS \

	ix86_tune_features[X86_TUNE_FUSE_CMP_AND_BRANCH_SOFLAGS]

#define TARGET_FUSE_ALU_AND_BRANCH \

	ix86_tune_features[X86_TUNE_FUSE_ALU_AND_BRANCH]

#define TARGET_OPT_AGU ix86_tune_features[X86_TUNE_OPT_AGU]

#define TARGET_AVOID_LEA_FOR_ADDR \

	ix86_tune_features[X86_TUNE_AVOID_LEA_FOR_ADDR]

#define TARGET_VECTORIZE_DOUBLE \

	ix86_tune_features[X86_TUNE_VECTORIZE_DOUBLE]

#define TARGET_SOFTWARE_PREFETCHING_BENEFICIAL \

	ix86_tune_features[X86_TUNE_SOFTWARE_PREFETCHING_BENEFICIAL]

#define TARGET_AVX128_OPTIMAL \

	ix86_tune_features[X86_TUNE_AVX128_OPTIMAL]

#define TARGET_REASSOC_INT_TO_PARALLEL \

	ix86_tune_features[X86_TUNE_REASSOC_INT_TO_PARALLEL]

#define TARGET_REASSOC_FP_TO_PARALLEL \

	ix86_tune_features[X86_TUNE_REASSOC_FP_TO_PARALLEL]

#define TARGET_GENERAL_REGS_SSE_SPILL \

	ix86_tune_features[X86_TUNE_GENERAL_REGS_SSE_SPILL]

#define TARGET_AVOID_MEM_OPND_FOR_CMOVE \

	ix86_tune_features[X86_TUNE_AVOID_MEM_OPND_FOR_CMOVE]

#define TARGET_SPLIT_MEM_OPND_FOR_FP_CONVERTS \

	ix86_tune_features[X86_TUNE_SPLIT_MEM_OPND_FOR_FP_CONVERTS]

#define TARGET_ADJUST_UNROLL \

    ix86_tune_features[X86_TUNE_ADJUST_UNROLL]

#define TARGET_AVOID_FALSE_DEP_FOR_BMI \

	ix86_tune_features[X86_TUNE_AVOID_FALSE_DEP_FOR_BMI]

/* Feature tests against the various architecture variations.  */

enum ix86_arch_indices {

  X86_ARCH_CMOV,

  X86_ARCH_CMPXCHG,

  X86_ARCH_CMPXCHG8B,

  X86_ARCH_XADD,

  X86_ARCH_BSWAP,

  X86_ARCH_LAST

};

extern unsigned char ix86_arch_features[X86_ARCH_LAST];

#define TARGET_CMOV		ix86_arch_features[X86_ARCH_CMOV]

#define TARGET_CMPXCHG		ix86_arch_features[X86_ARCH_CMPXCHG]

#define TARGET_CMPXCHG8B	ix86_arch_features[X86_ARCH_CMPXCHG8B]

#define TARGET_XADD		ix86_arch_features[X86_ARCH_XADD]

#define TARGET_BSWAP		ix86_arch_features[X86_ARCH_BSWAP]

/* For sane SSE instruction set generation we need fcomi instruction.

   It is safe to enable all CMOVE instructions.  Also, RDRAND intrinsic

   expands to a sequence that includes conditional move. */

#define TARGET_CMOVE		(TARGET_CMOV || TARGET_SSE || TARGET_RDRND)

#define TARGET_FISTTP		(TARGET_SSE3 && TARGET_80387)

extern unsigned char x86_prefetch_sse;

#define TARGET_PREFETCH_SSE	x86_prefetch_sse

#define ASSEMBLER_DIALECT	(ix86_asm_dialect)

#define TARGET_SSE_MATH		((ix86_fpmath & FPMATH_SSE) != 0)

#define TARGET_MIX_SSE_I387 \

 ((ix86_fpmath & (FPMATH_SSE | FPMATH_387)) == (FPMATH_SSE | FPMATH_387))

#define TARGET_GNU_TLS		(ix86_tls_dialect == TLS_DIALECT_GNU)

#define TARGET_GNU2_TLS		(ix86_tls_dialect == TLS_DIALECT_GNU2)

#define TARGET_ANY_GNU_TLS	(TARGET_GNU_TLS || TARGET_GNU2_TLS)

#define TARGET_SUN_TLS		0

#ifndef TARGET_64BIT_DEFAULT

#define TARGET_64BIT_DEFAULT 0

#endif

#ifndef TARGET_TLS_DIRECT_SEG_REFS_DEFAULT

#define TARGET_TLS_DIRECT_SEG_REFS_DEFAULT 0

#endif

#define TARGET_SSP_GLOBAL_GUARD (ix86_stack_protector_guard == SSP_GLOBAL)

#define TARGET_SSP_TLS_GUARD    (ix86_stack_protector_guard == SSP_TLS)

/* Fence to use after loop using storent.  */

extern tree x86_mfence;

#define FENCE_FOLLOWING_MOVNT x86_mfence

/* Once GDB has been enhanced to deal with functions without frame

   pointers, we can change this to allow for elimination of

   the frame pointer in leaf functions.  */

#define TARGET_DEFAULT 0

/* Extra bits to force.  */

#define TARGET_SUBTARGET_DEFAULT 0

#define TARGET_SUBTARGET_ISA_DEFAULT 0

/* Extra bits to force on w/ 32-bit mode.  */

#define TARGET_SUBTARGET32_DEFAULT 0

#define TARGET_SUBTARGET32_ISA_DEFAULT 0

/* Extra bits to force on w/ 64-bit mode.  */

#define TARGET_SUBTARGET64_DEFAULT 0

#define TARGET_SUBTARGET64_ISA_DEFAULT 0

/* Replace MACH-O, ifdefs by in-line tests, where possible.

   (a) Macros defined in config/i386/darwin.h  */

#define TARGET_MACHO 0

#define TARGET_MACHO_BRANCH_ISLANDS 0

#define MACHOPIC_ATT_STUB 0

/* (b) Macros defined in config/darwin.h  */

#define MACHO_DYNAMIC_NO_PIC_P 0

#define MACHOPIC_INDIRECT 0

#define MACHOPIC_PURE 0

/* For the RDOS  */

#define TARGET_RDOS 0

/* For the Windows 64-bit ABI.  */

#define TARGET_64BIT_MS_ABI (TARGET_64BIT && ix86_cfun_abi () == MS_ABI)

/* For the Windows 32-bit ABI.  */

#define TARGET_32BIT_MS_ABI (!TARGET_64BIT && ix86_cfun_abi () == MS_ABI)

/* This is re-defined by cygming.h.  */

#define TARGET_SEH 0

/* This is re-defined by cygming.h.  */

#define TARGET_PECOFF 0

/* The default abi used by target.  */

#define DEFAULT_ABI SYSV_ABI

/* The default TLS segment register used by target.  */

#define DEFAULT_TLS_SEG_REG (TARGET_64BIT ? SEG_FS : SEG_GS)

/* Subtargets may reset this to 1 in order to enable 96-bit long double

   with the rounding mode forced to 53 bits.  */

#define TARGET_96_ROUND_53_LONG_DOUBLE 0

/* -march=native handling only makes sense with compiler running on

   an x86 or x86_64 chip.  If changing this condition, also change

   the condition in driver-i386.c.  */

#if defined(__i386__) || defined(__x86_64__)

/* In driver-i386.c.  */

extern const char *host_detect_local_cpu (int argc, const char **argv);

#define EXTRA_SPEC_FUNCTIONS \

  { "local_cpu_detect", host_detect_local_cpu },

#define HAVE_LOCAL_CPU_DETECT

#endif

#if TARGET_64BIT_DEFAULT

#define OPT_ARCH64 "!m32"

#define OPT_ARCH32 "m32"

#else

#define OPT_ARCH64 "m64|mx32"

#define OPT_ARCH32 "m64|mx32:;"

#endif

/* Support for configure-time defaults of some command line options.

   The order here is important so that -march doesn't squash the

   tune or cpu values.  */

#define OPTION_DEFAULT_SPECS					   \

  {"tune", "%{!mtune=*:%{!mcpu=*:%{!march=*:-mtune=%(VALUE)}}}" }, \

  {"tune_32", "%{" OPT_ARCH32 ":%{!mtune=*:%{!mcpu=*:%{!march=*:-mtune=%(VALUE)}}}}" }, \

  {"tune_64", "%{" OPT_ARCH64 ":%{!mtune=*:%{!mcpu=*:%{!march=*:-mtune=%(VALUE)}}}}" }, \

  {"cpu", "%{!mtune=*:%{!mcpu=*:%{!march=*:-mtune=%(VALUE)}}}" },  \

  {"cpu_32", "%{" OPT_ARCH32 ":%{!mtune=*:%{!mcpu=*:%{!march=*:-mtune=%(VALUE)}}}}" }, \

  {"cpu_64", "%{" OPT_ARCH64 ":%{!mtune=*:%{!mcpu=*:%{!march=*:-mtune=%(VALUE)}}}}" }, \

  {"arch", "%{!march=*:-march=%(VALUE)}"},			   \

  {"arch_32", "%{" OPT_ARCH32 ":%{!march=*:-march=%(VALUE)}}"},	   \

  {"arch_64", "%{" OPT_ARCH64 ":%{!march=*:-march=%(VALUE)}}"},

/* Specs for the compiler proper */

#ifndef CC1_CPU_SPEC

#define CC1_CPU_SPEC_1 ""

#ifndef HAVE_LOCAL_CPU_DETECT

#define CC1_CPU_SPEC CC1_CPU_SPEC_1

#else

#define CC1_CPU_SPEC CC1_CPU_SPEC_1 \

"%{march=native:%>march=native %:local_cpu_detect(arch) \

  %{!mtune=*:%>mtune=native %:local_cpu_detect(tune)}} \

%{mtune=native:%>mtune=native %:local_cpu_detect(tune)}"

#endif

#endif

/* Target CPU builtins.  */

#define TARGET_CPU_CPP_BUILTINS() ix86_target_macros ()

/* Target Pragmas.  */

#define REGISTER_TARGET_PRAGMAS() ix86_register_pragmas ()

#ifndef CC1_SPEC

#define CC1_SPEC "%(cc1_cpu) "

#endif

/* This macro defines names of additional specifications to put in the

   specs that can be used in various specifications like CC1_SPEC.  Its

   definition is an initializer with a subgrouping for each command option.

   Each subgrouping contains a string constant, that defines the

   specification name, and a string constant that used by the GCC driver

   program.

   Do not define this macro if it does not need to do anything.  */

#ifndef SUBTARGET_EXTRA_SPECS

#define SUBTARGET_EXTRA_SPECS

#endif

#define EXTRA_SPECS							\

  { "cc1_cpu",  CC1_CPU_SPEC },						\

  SUBTARGET_EXTRA_SPECS

/* Set the value of FLT_EVAL_METHOD in float.h.  When using only the

   FPU, assume that the fpcw is set to extended precision; when using

   only SSE, rounding is correct; when using both SSE and the FPU,

   the rounding precision is indeterminate, since either may be chosen

   apparently at random.  */

#define TARGET_FLT_EVAL_METHOD \

  (TARGET_MIX_SSE_I387 ? -1 : TARGET_SSE_MATH ? 0 : 2)

/* Whether to allow x87 floating-point arithmetic on MODE (one of

   SFmode, DFmode and XFmode) in the current excess precision

   configuration.  */

#define X87_ENABLE_ARITH(MODE) \

  (flag_excess_precision == EXCESS_PRECISION_FAST || (MODE) == XFmode)

/* Likewise, whether to allow direct conversions from integer mode

   IMODE (HImode, SImode or DImode) to MODE.  */

#define X87_ENABLE_FLOAT(MODE, IMODE)			\

  (flag_excess_precision == EXCESS_PRECISION_FAST	\

   || (MODE) == XFmode					\

   || ((MODE) == DFmode && (IMODE) == SImode)		\

   || (IMODE) == HImode)

/* target machine storage layout */

#define SHORT_TYPE_SIZE 16

#define INT_TYPE_SIZE 32

#define LONG_TYPE_SIZE (TARGET_X32 ? 32 : BITS_PER_WORD)

#define POINTER_SIZE (TARGET_X32 ? 32 : BITS_PER_WORD)

#define LONG_LONG_TYPE_SIZE 64

#define FLOAT_TYPE_SIZE 32

#define DOUBLE_TYPE_SIZE 64

#define LONG_DOUBLE_TYPE_SIZE \

  (TARGET_LONG_DOUBLE_64 ? 64 : (TARGET_LONG_DOUBLE_128 ? 128 : 80))

#define WIDEST_HARDWARE_FP_SIZE 80

#if defined (TARGET_BI_ARCH) || TARGET_64BIT_DEFAULT

#define MAX_BITS_PER_WORD 64

#else

#define MAX_BITS_PER_WORD 32

#endif

/* Define this if most significant byte of a word is the lowest numbered.  */

/* That is true on the 80386.  */

#define BITS_BIG_ENDIAN 0

/* Define this if most significant byte of a word is the lowest numbered.  */

/* That is not true on the 80386.  */

#define BYTES_BIG_ENDIAN 0

/* Define this if most significant word of a multiword number is the lowest

   numbered.  */

/* Not true for 80386 */

#define WORDS_BIG_ENDIAN 0

/* Width of a word, in units (bytes).  */

#define UNITS_PER_WORD		(TARGET_64BIT ? 8 : 4)

#ifndef IN_LIBGCC2

#define MIN_UNITS_PER_WORD	4

#endif

/* Allocation boundary (in *bits*) for storing arguments in argument list.  */

#define PARM_BOUNDARY BITS_PER_WORD

/* Boundary (in *bits*) on which stack pointer should be aligned.  */

#define STACK_BOUNDARY \

 (TARGET_64BIT && ix86_abi == MS_ABI ? 128 : BITS_PER_WORD)

/* Stack boundary of the main function guaranteed by OS.  */

#define MAIN_STACK_BOUNDARY (TARGET_64BIT ? 128 : 32)

/* Minimum stack boundary.  */

#define MIN_STACK_BOUNDARY BITS_PER_WORD

/* Boundary (in *bits*) on which the stack pointer prefers to be

   aligned; the compiler cannot rely on having this alignment.  */

#define PREFERRED_STACK_BOUNDARY ix86_preferred_stack_boundary

/* It should be MIN_STACK_BOUNDARY.  But we set it to 128 bits for

   both 32bit and 64bit, to support codes that need 128 bit stack

   alignment for SSE instructions, but can't realign the stack.  */

#define PREFERRED_STACK_BOUNDARY_DEFAULT 128

/* 1 if -mstackrealign should be turned on by default.  It will

   generate an alternate prologue and epilogue that realigns the

   runtime stack if nessary.  This supports mixing codes that keep a

   4-byte aligned stack, as specified by i386 psABI, with codes that

   need a 16-byte aligned stack, as required by SSE instructions.  */

#define STACK_REALIGN_DEFAULT 0

/* Boundary (in *bits*) on which the incoming stack is aligned.  */

#define INCOMING_STACK_BOUNDARY ix86_incoming_stack_boundary

/* According to Windows x64 software convention, the maximum stack allocatable

   in the prologue is 4G - 8 bytes.  Furthermore, there is a limited set of

   instructions allowed to adjust the stack pointer in the epilog, forcing the

   use of frame pointer for frames larger than 2 GB.  This theorical limit

   is reduced by 256, an over-estimated upper bound for the stack use by the

   prologue.

   We define only one threshold for both the prolog and the epilog.  When the

   frame size is larger than this threshold, we allocate the area to save SSE

   regs, then save them, and then allocate the remaining.  There is no SEH

   unwind info for this later allocation.  */

#define SEH_MAX_FRAME_SIZE ((2U << 30) - 256)

/* Target OS keeps a vector-aligned (128-bit, 16-byte) stack.  This is

   mandatory for the 64-bit ABI, and may or may not be true for other

   operating systems.  */

#define TARGET_KEEPS_VECTOR_ALIGNED_STACK TARGET_64BIT

/* Minimum allocation boundary for the code of a function.  */

#define FUNCTION_BOUNDARY 8

/* C++ stores the virtual bit in the lowest bit of function pointers.  */

#define TARGET_PTRMEMFUNC_VBIT_LOCATION ptrmemfunc_vbit_in_pfn

/* Minimum size in bits of the largest boundary to which any

   and all fundamental data types supported by the hardware

   might need to be aligned. No data type wants to be aligned

   rounder than this.

   Pentium+ prefers DFmode values to be aligned to 64 bit boundary

   and Pentium Pro XFmode values at 128 bit boundaries.

   When increasing the maximum, also update

   TARGET_ABSOLUTE_BIGGEST_ALIGNMENT.  */

#define BIGGEST_ALIGNMENT \

  (TARGET_AVX512F ? 512 : (TARGET_AVX ? 256 : 128))

/* Maximum stack alignment.  */

#define MAX_STACK_ALIGNMENT MAX_OFILE_ALIGNMENT

/* Alignment value for attribute ((aligned)).  It is a constant since

   it is the part of the ABI.  We shouldn't change it with -mavx.  */

#define ATTRIBUTE_ALIGNED_VALUE 128

/* Decide whether a variable of mode MODE should be 128 bit aligned.  */

#define ALIGN_MODE_128(MODE) \

 ((MODE) == XFmode || SSE_REG_MODE_P (MODE))

/* The published ABIs say that doubles should be aligned on word

   boundaries, so lower the alignment for structure fields unless

   -malign-double is set.  */

/* ??? Blah -- this macro is used directly by libobjc.  Since it

   supports no vector modes, cut out the complexity and fall back

   on BIGGEST_FIELD_ALIGNMENT.  */

#ifdef IN_TARGET_LIBS

#ifdef __x86_64__

#define BIGGEST_FIELD_ALIGNMENT 128

#else

#define BIGGEST_FIELD_ALIGNMENT 32

#endif

#else

#define ADJUST_FIELD_ALIGN(FIELD, COMPUTED) \

   x86_field_alignment (FIELD, COMPUTED)

#endif

/* If defined, a C expression to compute the alignment given to a

   constant that is being placed in memory.  EXP is the constant

   and ALIGN is the alignment that the object would ordinarily have.

   The value of this macro is used instead of that alignment to align

   the object.

   If this macro is not defined, then ALIGN is used.

   The typical use of this macro is to increase alignment for string

   constants to be word aligned so that `strcpy' calls that copy

   constants can be done inline.  */

#define CONSTANT_ALIGNMENT(EXP, ALIGN) ix86_constant_alignment ((EXP), (ALIGN))

/* If defined, a C expression to compute the alignment for a static

   variable.  TYPE is the data type, and ALIGN is the alignment that

   the object would ordinarily have.  The value of this macro is used

   instead of that alignment to align the object.

   If this macro is not defined, then ALIGN is used.

   One use of this macro is to increase alignment of medium-size

   data to make it all fit in fewer cache lines.  Another is to

   cause character arrays to be word-aligned so that `strcpy' calls

   that copy constants to character arrays can be done inline.  */

#define DATA_ALIGNMENT(TYPE, ALIGN) \

  ix86_data_alignment ((TYPE), (ALIGN), true)

/* Similar to DATA_ALIGNMENT, but for the cases where the ABI mandates

   some alignment increase, instead of optimization only purposes.  E.g.

   AMD x86-64 psABI says that variables with array type larger than 15 bytes

   must be aligned to 16 byte boundaries.

   If this macro is not defined, then ALIGN is used.  */

#define DATA_ABI_ALIGNMENT(TYPE, ALIGN) \

  ix86_data_alignment ((TYPE), (ALIGN), false)

/* If defined, a C expression to compute the alignment for a local

   variable.  TYPE is the data type, and ALIGN is the alignment that

   the object would ordinarily have.  The value of this macro is used

   instead of that alignment to align the object.

   If this macro is not defined, then ALIGN is used.

   One use of this macro is to increase alignment of medium-size

   data to make it all fit in fewer cache lines.  */

#define LOCAL_ALIGNMENT(TYPE, ALIGN) \

  ix86_local_alignment ((TYPE), VOIDmode, (ALIGN))

/* If defined, a C expression to compute the alignment for stack slot.

   TYPE is the data type, MODE is the widest mode available, and ALIGN

   is the alignment that the slot would ordinarily have.  The value of

   this macro is used instead of that alignment to align the slot.

   If this macro is not defined, then ALIGN is used when TYPE is NULL,

   Otherwise, LOCAL_ALIGNMENT will be used.

   One use of this macro is to set alignment of stack slot to the

   maximum alignment of all possible modes which the slot may have.  */

#define STACK_SLOT_ALIGNMENT(TYPE, MODE, ALIGN) \

  ix86_local_alignment ((TYPE), (MODE), (ALIGN))

/* If defined, a C expression to compute the alignment for a local

   variable DECL.

   If this macro is not defined, then

   LOCAL_ALIGNMENT (TREE_TYPE (DECL), DECL_ALIGN (DECL)) will be used.

   One use of this macro is to increase alignment of medium-size

   data to make it all fit in fewer cache lines.  */

#define LOCAL_DECL_ALIGNMENT(DECL) \

  ix86_local_alignment ((DECL), VOIDmode, DECL_ALIGN (DECL))

/* If defined, a C expression to compute the minimum required alignment

   for dynamic stack realignment purposes for EXP (a TYPE or DECL),

   MODE, assuming normal alignment ALIGN.

   If this macro is not defined, then (ALIGN) will be used.  */

#define MINIMUM_ALIGNMENT(EXP, MODE, ALIGN) \

  ix86_minimum_alignment (EXP, MODE, ALIGN)

/* Set this nonzero if move instructions will actually fail to work

   when given unaligned data.  */

#define STRICT_ALIGNMENT 0

/* If bit field type is int, don't let it cross an int,

   and give entire struct the alignment of an int.  */

/* Required on the 386 since it doesn't have bit-field insns.  */

#define PCC_BITFIELD_TYPE_MATTERS 1

/* Standard register usage.  */

/* This processor has special stack-like registers.  See reg-stack.c

   for details.  */

#define STACK_REGS

#define IS_STACK_MODE(MODE)					\

  (((MODE) == SFmode && !(TARGET_SSE && TARGET_SSE_MATH))	\

   || ((MODE) == DFmode && !(TARGET_SSE2 && TARGET_SSE_MATH))	\

   || (MODE) == XFmode)

/* Number of actual hardware registers.

   The hardware registers are assigned numbers for the compiler

   from 0 to just below FIRST_PSEUDO_REGISTER.

   All registers that the compiler knows about must be given numbers,

   even those that are not normally considered general registers.

   In the 80386 we give the 8 general purpose registers the numbers 0-7.

   We number the floating point registers 8-15.

   Note that registers 0-7 can be accessed as a  short or int,

   while only 0-3 may be used with byte `mov' instructions.

   Reg 16 does not correspond to any hardware register, but instead

   appears in the RTL as an argument pointer prior to reload, and is

   eliminated during reloading in favor of either the stack or frame

   pointer.  */

#define FIRST_PSEUDO_REGISTER 81

/* Number of hardware registers that go into the DWARF-2 unwind info.

   If not defined, equals FIRST_PSEUDO_REGISTER.  */

#define DWARF_FRAME_REGISTERS 17

/* 1 for registers that have pervasive standard uses

   and are not available for the register allocator.

   On the 80386, the stack pointer is such, as is the arg pointer.

   REX registers are disabled for 32bit targets in

   TARGET_CONDITIONAL_REGISTER_USAGE.  */

#define FIXED_REGISTERS						\

/*ax,dx,cx,bx,si,di,bp,sp,st,st1,st2,st3,st4,st5,st6,st7*/	\

{  0, 0, 0, 0, 0, 0, 0, 1, 0,  0,  0,  0,  0,  0,  0,  0,	\

/*arg,flags,fpsr,fpcr,frame*/					\

    1,    1,   1,   1,    1,					\

/*xmm0,xmm1,xmm2,xmm3,xmm4,xmm5,xmm6,xmm7*/			\

     0,   0,   0,   0,   0,   0,   0,   0,			\

/* mm0, mm1, mm2, mm3, mm4, mm5, mm6, mm7*/			\

     0,   0,   0,   0,   0,   0,   0,   0,			\

/*  r8,  r9, r10, r11, r12, r13, r14, r15*/			\

     0,   0,   0,   0,   0,   0,   0,   0,			\

/*xmm8,xmm9,xmm10,xmm11,xmm12,xmm13,xmm14,xmm15*/		\

     0,   0,    0,    0,    0,    0,    0,    0,		\

/*xmm16,xmm17,xmm18,xmm19,xmm20,xmm21,xmm22,xmm23*/		\

     0,   0,    0,    0,    0,    0,    0,    0,		\

/*xmm24,xmm25,xmm26,xmm27,xmm28,xmm29,xmm30,xmm31*/		\

     0,   0,    0,    0,    0,    0,    0,    0,		\

/*  k0,  k1, k2, k3, k4, k5, k6, k7*/				\

     0,  0,   0,  0,  0,  0,  0,  0,				\

/*   b0, b1, b2, b3*/						\

     0,  0,  0,  0 }

/* 1 for registers not available across function calls.

   These must include the FIXED_REGISTERS and also any

   registers that can be used without being saved.

   The latter must include the registers where values are returned

   and the register where structure-value addresses are passed.

   Aside from that, you can include as many other registers as you like.

   Value is set to 1 if the register is call used unconditionally.

   Bit one is set if the register is call used on TARGET_32BIT ABI.

   Bit two is set if the register is call used on TARGET_64BIT ABI.

   Bit three is set if the register is call used on TARGET_64BIT_MS_ABI.

   Proper values are computed in TARGET_CONDITIONAL_REGISTER_USAGE.  */

#define CALL_USED_REGISTERS					\

/*ax,dx,cx,bx,si,di,bp,sp,st,st1,st2,st3,st4,st5,st6,st7*/	\

{  1, 1, 1, 0, 4, 4, 0, 1, 1,  1,  1,  1,  1,  1,  1,  1,	\

/*arg,flags,fpsr,fpcr,frame*/					\

    1,   1,    1,   1,    1,					\

/*xmm0,xmm1,xmm2,xmm3,xmm4,xmm5,xmm6,xmm7*/			\

     1,   1,   1,   1,   1,   1,   6,   6,			\

/* mm0, mm1, mm2, mm3, mm4, mm5, mm6, mm7*/			\

     1,   1,   1,   1,   1,   1,   1,   1,			\

/*  r8,  r9, r10, r11, r12, r13, r14, r15*/			\

     1,   1,   1,   1,   2,   2,   2,   2,			\

/*xmm8,xmm9,xmm10,xmm11,xmm12,xmm13,xmm14,xmm15*/		\

     6,   6,    6,    6,    6,    6,    6,    6,		\

/*xmm16,xmm17,xmm18,xmm19,xmm20,xmm21,xmm22,xmm23*/		\

     6,    6,     6,    6,    6,    6,    6,    6,		\

/*xmm24,xmm25,xmm26,xmm27,xmm28,xmm29,xmm30,xmm31*/		\

     6,    6,     6,    6,    6,    6,    6,    6,		\

 /* k0,  k1,  k2,  k3,  k4,  k5,  k6,  k7*/			\

     1,   1,   1,   1,   1,   1,   1,   1,			\

/*   b0, b1, b2, b3*/						\

     1,  1,  1,  1 }

/* Order in which to allocate registers.  Each register must be

   listed once, even those in FIXED_REGISTERS.  List frame pointer

   late and fixed registers last.  Note that, in general, we prefer

   registers listed in CALL_USED_REGISTERS, keeping the others

   available for storage of persistent values.

   The ADJUST_REG_ALLOC_ORDER actually overwrite the order,

   so this is just empty initializer for array.  */

#define REG_ALLOC_ORDER 					\

{  0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17,\

   18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32,	\

   33, 34, 35, 36, 37, 38, 39, 40, 41, 42, 43, 44, 45, 46, 47,  \

   48, 49, 50, 51, 52, 53, 54, 55, 56, 57, 58, 59, 60, 61, 62,	\

   63, 64, 65, 66, 67, 68, 69, 70, 71, 72, 73, 74, 75, 76, 77,  \

   78, 79, 80 }

/* ADJUST_REG_ALLOC_ORDER is a macro which permits reg_alloc_order

   to be rearranged based on a particular function.  When using sse math,

   we want to allocate SSE before x87 registers and vice versa.  */

#define ADJUST_REG_ALLOC_ORDER x86_order_regs_for_local_alloc ()

#define OVERRIDE_ABI_FORMAT(FNDECL) ix86_call_abi_override (FNDECL)

/* Return number of consecutive hard regs needed starting at reg REGNO

   to hold something of mode MODE.

   This is ordinarily the length in words of a value of mode MODE

   but can be less for certain modes in special long registers.

   Actually there are no two word move instructions for consecutive

   registers.  And only registers 0-3 may have mov byte instructions

   applied to them.  */

#define HARD_REGNO_NREGS(REGNO, MODE)					\

  (STACK_REGNO_P (REGNO) || SSE_REGNO_P (REGNO) || MMX_REGNO_P (REGNO)	\

   || MASK_REGNO_P (REGNO) || BND_REGNO_P (REGNO)			\

   ? (COMPLEX_MODE_P (MODE) ? 2 : 1)					\

   : ((MODE) == XFmode							\

      ? (TARGET_64BIT ? 2 : 3)						\

      : (MODE) == XCmode						\

      ? (TARGET_64BIT ? 4 : 6)						\

      : ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD)))

#define HARD_REGNO_NREGS_HAS_PADDING(REGNO, MODE)			\

  ((TARGET_128BIT_LONG_DOUBLE && !TARGET_64BIT)				\

   ? (STACK_REGNO_P (REGNO) || SSE_REGNO_P (REGNO) || MMX_REGNO_P (REGNO) \

      ? 0								\

      : ((MODE) == XFmode || (MODE) == XCmode))				\

   : 0)

#define HARD_REGNO_NREGS_WITH_PADDING(REGNO, MODE) ((MODE) == XFmode ? 4 : 8)

#define VALID_AVX256_REG_MODE(MODE)					\

  ((MODE) == V32QImode || (MODE) == V16HImode || (MODE) == V8SImode	\

   || (MODE) == V4DImode || (MODE) == V2TImode || (MODE) == V8SFmode	\

   || (MODE) == V4DFmode)

#define VALID_AVX256_REG_OR_OI_MODE(MODE)		\

  (VALID_AVX256_REG_MODE (MODE) || (MODE) == OImode)

#define VALID_AVX512F_SCALAR_MODE(MODE)					\

  ((MODE) == DImode || (MODE) == DFmode || (MODE) == SImode		\

   || (MODE) == SFmode)

#define VALID_AVX512F_REG_MODE(MODE)					\

  ((MODE) == V8DImode || (MODE) == V8DFmode || (MODE) == V64QImode	\

   || (MODE) == V16SImode || (MODE) == V16SFmode || (MODE) == V32HImode \

   || (MODE) == V4TImode)

#define VALID_AVX512VL_128_REG_MODE(MODE)					\

  ((MODE) == V2DImode || (MODE) == V2DFmode || (MODE) == V16QImode	\

   || (MODE) == V4SImode || (MODE) == V4SFmode || (MODE) == V8HImode)

#define VALID_SSE2_REG_MODE(MODE)					\

  ((MODE) == V16QImode || (MODE) == V8HImode || (MODE) == V2DFmode	\

   || (MODE) == V2DImode || (MODE) == DFmode)

#define VALID_SSE_REG_MODE(MODE)					\

  ((MODE) == V1TImode || (MODE) == TImode				\

   || (MODE) == V4SFmode || (MODE) == V4SImode				\

   || (MODE) == SFmode || (MODE) == TFmode)

#define VALID_MMX_REG_MODE_3DNOW(MODE) \

  ((MODE) == V2SFmode || (MODE) == SFmode)

#define VALID_MMX_REG_MODE(MODE)					\

  ((MODE == V1DImode) || (MODE) == DImode				\

   || (MODE) == V2SImode || (MODE) == SImode				\

   || (MODE) == V4HImode || (MODE) == V8QImode)

#define VALID_BND_REG_MODE(MODE) \

  (TARGET_64BIT ? (MODE) == BND64mode : (MODE) == BND32mode)