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Rev | Author | Line No. | Line |
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6324 | serge | 1 | /* Opcode table header for Visium. |
2 | |||
3 | Copyright (C) 2003-2015 Free Software Foundation, Inc. |
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4 | |||
5 | This file is part of GDB, GAS, and GNU binutils. |
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6 | |||
7 | GDB, GAS and the GNU binutils are free software; you can redistribute |
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8 | them and/or modify them under the terms of the GNU General Public |
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9 | License as published by the Free Software Foundation; either version 3, |
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10 | or (at your option) any later version. |
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11 | |||
12 | GDB, GAS, and the GNU binutils are distributed in the hope that they |
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13 | will be useful, but WITHOUT ANY WARRANTY; without even the implied |
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14 | warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See |
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15 | the GNU General Public License for more details. |
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16 | |||
17 | You should have received a copy of the GNU General Public License |
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18 | along with this file; see the file COPYING3. If not, write to the Free |
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19 | Software Foundation, 51 Franklin Street - Fifth Floor, Boston, |
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20 | MA 02110-1301, USA. */ |
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21 | |||
22 | enum visium_opcode_arch_val |
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23 | { |
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24 | VISIUM_OPCODE_ARCH_DEF = 0, |
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25 | VISIUM_OPCODE_ARCH_GR5, |
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26 | VISIUM_OPCODE_ARCH_GR6, |
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27 | VISIUM_OPCODE_ARCH_BAD |
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28 | }; |
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29 | |||
30 | /* The highest architecture in the table. */ |
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31 | #define VISIUM_OPCODE_ARCH_MAX (VISIUM_OPCODE_ARCH_BAD - 1) |
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32 | |||
33 | /* Given an enum visium_opcode_arch_val, return the bitmask to use in |
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34 | insn encoding/decoding. */ |
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35 | #define VISIUM_OPCODE_ARCH_MASK(arch) (1 << (arch)) |
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36 | |||
37 | /* Some defines to make life easy. */ |
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38 | #define MASK_DEF VISIUM_OPCODE_ARCH_MASK (VISIUM_OPCODE_ARCH_DEF) |
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39 | #define MASK_GR5 VISIUM_OPCODE_ARCH_MASK (VISIUM_OPCODE_ARCH_GR5) |
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40 | #define MASK_GR6 VISIUM_OPCODE_ARCH_MASK (VISIUM_OPCODE_ARCH_GR6) |
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41 | |||
42 | /* Bit masks of architectures supporting the insn. */ |
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43 | #define def (MASK_DEF | MASK_GR5 | MASK_GR6) |
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44 | #define gr5 (MASK_GR5 | MASK_GR6) |
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45 | #define gr6 (MASK_GR6) |
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46 | |||
47 | /* The condition code field is not used (zero) for most instructions. |
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48 | BRR and BRA make normal use of it. Floating point instructions use |
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49 | it as a sub-opcode. */ |
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50 | #define CC_MASK (0xf << 27) |
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51 | |||
52 | /* It seems a shame not to use these bits in a class 0 instruction, |
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53 | since they could be used to extend the range of the branch. */ |
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54 | #define CLASS0_UNUSED_MASK (0x1f << 16) |
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55 | |||
56 | /* For class 1 instructions the following bit is unused. */ |
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57 | #define CLASS1_UNUSED_MASK (1 << 9) |
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58 | |||
59 | /* For class 1 instructions this field gives the index for a write |
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60 | instruction, the specific operation for an EAM instruction, or |
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61 | the floating point destination register for a floating point |
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62 | instruction. */ |
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63 | #define CLASS1_INDEX_MASK (0x1f << 10) |
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64 | |||
65 | /* For class 3 instructions the following field gives the destination |
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66 | general register. */ |
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67 | #define CLASS3_DEST_MASK (0x1f << 10) |
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68 | |||
69 | /* For class 1 and class 3 instructions the following bit selects an |
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70 | EAM write/read rather than a memory write/read. */ |
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71 | #define EAM_SELECT_MASK (1 << 15) |
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72 | |||
73 | /* Floating point instructions are distinguished from general EAM |
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74 | instructions by the following bit. */ |
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75 | #define FP_SELECT_MASK (1 << 3) |
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76 | |||
77 | /* For both class 1 and class 3 the following fields give, where |
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78 | appropriate the srcA and srcB registers whether floating point |
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79 | or general. */ |
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80 | #define SRCA_MASK (0x1f << 16) |
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81 | #define SRCB_MASK (0x1f << 4) |
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82 | |||
83 | /* The class 3 interrupt bit. It turns a BRA into a SYS1, and an |
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84 | RFLAG into a SYS2. This bit should not be set in the user's |
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85 | class 3 instructions. This bit is also used in class 3 |
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86 | to distinguish between floating point and other EAM operations. |
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87 | (see FP_SELECT_MASK). */ |
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88 | #define CLASS3_INT (1 << 3) |
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89 | |||
90 | /* Class 3 shift instructions use this bit to indicate that the |
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91 | srcB field is a 5 bit immediate shift count rather than a |
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92 | register number. */ |
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93 | #define CLASS3_SOURCEB_IMMED (1 << 9) |
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94 | |||
95 | #define BMD 0x02630004 |
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96 | #define BMI 0x82230004 |
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97 | #define DSI 0x82800004 |
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98 | #define ENI 0x02a00004 |
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99 | #define RFI 0x82fe01d4 |
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100 | |||
101 | struct reg_entry |
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102 | { |
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103 | char *name; |
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104 | unsigned char code; |
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105 | }; |
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106 | |||
107 | static const struct reg_entry gen_reg_table[] = |
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108 | { |
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109 | {"fp", 0x16}, |
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110 | {"r0", 0x0}, |
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111 | {"r1", 0x1}, |
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112 | {"r10", 0xA}, |
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113 | {"r11", 0xB}, |
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114 | {"r12", 0xC}, |
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115 | {"r13", 0xD}, |
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116 | {"r14", 0xE}, |
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117 | {"r15", 0xF}, |
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118 | {"r16", 0x10}, |
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119 | {"r17", 0x11}, |
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120 | {"r18", 0x12}, |
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121 | {"r19", 0x13}, |
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122 | {"r2", 0x2}, |
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123 | {"r20", 0x14}, |
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124 | {"r21", 0x15}, |
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125 | {"r22", 0x16}, |
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126 | {"r23", 0x17}, |
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127 | {"r24", 0x18}, |
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128 | {"r25", 0x19}, |
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129 | {"r26", 0x1a}, |
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130 | {"r27", 0x1b}, |
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131 | {"r28", 0x1c}, |
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132 | {"r29", 0x1d}, |
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133 | {"r3", 0x3}, |
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134 | {"r30", 0x1e}, |
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135 | {"r31", 0x1f}, |
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136 | {"r4", 0x4}, |
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137 | {"r5", 0x5}, |
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138 | {"r6", 0x6}, |
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139 | {"r7", 0x7}, |
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140 | {"r8", 0x8}, |
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141 | {"r9", 0x9}, |
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142 | {"sp", 0x17}, |
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143 | }; |
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144 | |||
145 | static const struct reg_entry fp_reg_table[] = |
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146 | { |
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147 | {"f0", 0x0}, |
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148 | {"f1", 0x1}, |
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149 | {"f10", 0xa}, |
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150 | {"f11", 0xb}, |
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151 | {"f12", 0xc}, |
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152 | {"f13", 0xd}, |
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153 | {"f14", 0xe}, |
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154 | {"f15", 0xf}, |
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155 | {"f2", 0x2}, |
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156 | {"f3", 0x3}, |
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157 | {"f4", 0x4}, |
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158 | {"f5", 0x5}, |
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159 | {"f6", 0x6}, |
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160 | {"f7", 0x7}, |
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161 | {"f8", 0x8}, |
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162 | {"f9", 0x9}, |
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163 | }; |
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164 | |||
165 | static const struct cc_entry |
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166 | { |
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167 | char *name; |
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168 | int code; |
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169 | } cc_table [] = |
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170 | { |
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171 | {"cc", 6}, |
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172 | {"cs", 2}, |
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173 | {"eq", 1}, |
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174 | {"fa", 0}, |
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175 | {"ge", 9}, |
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176 | {"gt", 10}, |
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177 | {"hi", 11}, |
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178 | {"le", 12}, |
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179 | {"ls", 13}, |
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180 | {"lt", 14}, |
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181 | {"nc", 8}, |
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182 | {"ne", 5}, |
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183 | {"ns", 4}, |
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184 | {"oc", 7}, |
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185 | {"os", 3}, |
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186 | {"tr", 15}, |
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187 | }; |
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188 | |||
189 | enum addressing_mode |
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190 | { |
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191 | mode_d, /* register := */ |
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192 | mode_a, /* op= register */ |
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193 | mode_da, /* register := register */ |
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194 | mode_ab, /* register * register */ |
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195 | mode_dab, /* register := register * register */ |
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196 | mode_iab, /* 5-bit immediate * register * register */ |
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197 | mode_0ab, /* zero * register * register */ |
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198 | mode_da0, /* register := register * zero */ |
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199 | mode_cad, /* condition * register * register */ |
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200 | mode_das, /* register := register * 5-bit immed/register shift count */ |
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201 | mode_di, /* register := 5-bit immediate */ |
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202 | mode_ir, /* 5-bit immediate * register */ |
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203 | mode_ai, /* register 16-bit unsigned immediate */ |
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204 | mode_i, /* 16-bit unsigned immediate */ |
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205 | mode_bax, /* register * register * 5-bit immediate */ |
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206 | mode_dax, /* register := register * 5-bit immediate */ |
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207 | mode_s, /* special mode */ |
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208 | mode_sr, /* special mode with register */ |
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209 | mode_ci, /* condition * 16-bit signed word displacement */ |
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210 | mode_fdab, /* float := float * float */ |
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211 | mode_ifdab, /* fpinst: 4-bit immediate * float * float * float */ |
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212 | mode_idfab, /* fpuread: 4-bit immediate * register * float * float */ |
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213 | mode_fda, /* float := float */ |
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214 | mode_fdra, /* float := register */ |
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215 | mode_rdfab, /* register := float * float */ |
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216 | mode_rdfa, /* register := float */ |
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217 | mode_rrr, /* 3 register sources and destinations (block move) */ |
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218 | }; |
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219 | |||
220 | #define class0 (0<<25) |
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221 | #define class1 (1<<25) |
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222 | #define class2 (2<<25) |
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223 | #define class3 (3<<25) |
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224 | |||
225 | static const struct opcode_entry |
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226 | { |
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227 | char *mnem; |
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228 | enum addressing_mode mode; |
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229 | unsigned code; |
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230 | char flags; |
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231 | } |
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232 | opcode_table[] = |
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233 | { |
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234 | { "adc.b", mode_dab, class3|(1<<21)|(1), def }, |
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235 | { "adc.l", mode_dab, class3|(1<<21)|(4), def }, |
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236 | { "adc.w", mode_dab, class3|(1<<21)|(2), def }, |
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237 | { "add.b", mode_dab, class3|(0<<21)|(1), def }, |
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238 | { "add.l", mode_dab, class3|(0<<21)|(4), def }, |
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239 | { "add.w", mode_dab, class3|(0<<21)|(2), def }, |
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240 | { "addi", mode_ai, class2, def }, |
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241 | { "and.b", mode_dab, class3|(10<<21)|(1), def}, |
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242 | { "and.l", mode_dab, class3|(10<<21)|(4), def }, |
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243 | { "and.w", mode_dab, class3|(10<<21)|(2), def }, |
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244 | { "asl.b", mode_das, class3|(7<<21)|(1), def }, |
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245 | { "asl.l", mode_das, class3|(7<<21)|(4), def }, |
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246 | { "asl.w", mode_das, class3|(7<<21)|(2), def }, |
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247 | { "asld", mode_a, class1|(15<<21)|(1<<15)|(11<<10)|(4), def }, |
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248 | { "asr.b", mode_das, class3|(5<<21)|(1), def }, |
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249 | { "asr.l", mode_das, class3|(5<<21)|(4), def }, |
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250 | { "asr.w", mode_das, class3|(5<<21)|(2), def }, |
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251 | { "asrd", mode_a, class1|(15<<21)|(1<<15)|(9<<10)|(4), def }, |
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252 | { "bmd", mode_rrr, class1|(3<<21)|(3<<16)|(4), gr6 }, |
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253 | { "bmi", mode_rrr, class1|(1<<21)|(3<<16)|(4), gr6 }, |
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254 | { "bra", mode_cad, class3|(12<<21)|(4), def }, |
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255 | { "brr", mode_ci, class0, def }, |
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256 | { "cmp.b", mode_0ab, class3|(2<<21)|(1), def }, |
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257 | { "cmp.l", mode_0ab, class3|(2<<21)|(4), def }, |
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258 | { "cmp.w", mode_0ab, class3|(2<<21)|(2), def }, |
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259 | { "cmpc.b", mode_0ab, class3|(3<<21)|(1), def }, |
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260 | { "cmpc.l", mode_0ab, class3|(3<<21)|(4), def }, |
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261 | { "cmpc.w", mode_0ab, class3|(3<<21)|(2), def }, |
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262 | { "divds", mode_a, class1|(15<<21)|(1<<15)|(6<<10)|(4), def }, |
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263 | { "divdu", mode_a, class1|(15<<21)|(1<<15)|(7<<10)|(4), def }, |
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264 | { "divs", mode_a, class1|(15<<21)|(1<<15)|(2<<10)|(4), def }, |
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265 | { "divu", mode_a, class1|(15<<21)|(1<<15)|(3<<10)|(4), def }, |
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266 | { "dsi", mode_s, class1|(4<<21)|(4), def }, |
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267 | { "eamread", mode_di, class3|(15<<21)|(1<<15)|(1<<9)|(4), def }, |
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268 | { "eamwrite", mode_iab, class1|(15<<21)|(1<<15)|(4), def }, |
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269 | { "eni", mode_s, class1|(5<<21)|(4), def }, |
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270 | { "extb.b", mode_da, class3|(14<<21)|(1), def }, |
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271 | { "extb.l", mode_da, class3|(14<<21)|(4), def }, |
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272 | { "extb.w", mode_da, class3|(14<<21)|(2), def }, |
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273 | { "extw.l", mode_da, class3|(4<<21)|(4), def }, |
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274 | { "extw.w", mode_da, class3|(4<<21)|(2), def }, |
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275 | { "fabs", mode_fda, class1|(7<<27)|(15<<21)|(1<<15)|(1<<3)|(4), gr5 }, |
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276 | { "fadd", mode_fdab, class1|(1<<27)|(15<<21)|(1<<15)|(1<<3)|(4), gr5 }, |
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277 | { "fcmp", mode_rdfab,class3|(10<<27)|(15<<21)|(1<<15)|(1<<9)|(1<<3)|(4), gr5 }, |
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278 | { "fcmpe", mode_rdfab,class3|(11<<27)|(15<<21)|(1<<15)|(1<<9)|(1<<3)|(4), gr5 }, |
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279 | { "fdiv", mode_fdab, class1|(4<<27)|(15<<21)|(1<<15)|(1<<3)|(4), gr5 }, |
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280 | { "fload", mode_fdra, class1|(15<<21)|(1<<15)|(1<<3)|(4), gr5 }, |
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281 | { "fmove", mode_fda, class1|(12<<27)|(15<<21)|(1<<15)|(1<<3)|(4), gr5}, |
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282 | { "fmult", mode_fdab, class1|(3<<27)|(15<<21)|(1<<15)|(1<<3)|(4), gr5 }, |
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283 | { "fneg", mode_fda, class1|(6<<27)|(15<<21)|(1<<15)|(1<<3)|(4), gr5 }, |
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284 | { "fpinst", mode_ifdab,class1|(15<<21)|(1<<15)|(1<<3)|(4), gr5 }, |
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285 | { "fpuread", mode_idfab,class3|(15<<21)|(1<<15)|(1<<9)|(1<<3)|(4), gr5 }, |
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286 | { "fsqrt", mode_fda, class1|(5<<27)|(15<<21)|(1<<15)|(1<<3)|(4), gr5 }, |
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287 | { "fstore", mode_rdfa, class3|(15<<21)|(1<<15)|(1<<9)|(1<<3)|(4), gr5 }, |
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288 | { "fsub", mode_fdab, class1|(2<<27)|(15<<21)|(1<<15)|(1<<3)|(4), gr5 }, |
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289 | { "ftoi", mode_fda, class1|(8<<27)|(15<<21)|(1<<15)|(1<<3)|(4), gr5 }, |
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290 | { "itof", mode_fda, class1|(9<<27)|(15<<21)|(1<<15)|(1<<3)|(4), gr5 }, |
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291 | { "lsr.b", mode_das, class3|(6<<21)|(1), def }, |
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292 | { "lsr.l", mode_das, class3|(6<<21)|(4), def }, |
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293 | { "lsr.w", mode_das, class3|(6<<21)|(2), def }, |
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294 | { "lsrd", mode_a, class1|(15<<21)|(1<<15)|(10<<10)|(4), def }, |
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295 | { "move.b", mode_da0, class3|(9<<21)|(1), def }, |
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296 | { "move.l", mode_da0, class3|(9<<21)|(4), def }, |
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297 | { "move.w", mode_da0, class3|(9<<21)|(2), def }, |
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298 | { "movil", mode_ai, class2|(4<<21), def }, |
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299 | { "moviq", mode_ai, class2|(6<<21), def }, |
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300 | { "moviu", mode_ai, class2|(5<<21), def }, |
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301 | { "mults", mode_ab, class1|(15<<21)|(1<<15)|(0<<10)|(4), def }, |
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302 | { "multu", mode_ab, class1|(15<<21)|(1<<15)|(1<<10)|(4), def }, |
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303 | { "nop", mode_s, class0, def }, |
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304 | { "not.b", mode_da, class3|(11<<21)|(1), def }, |
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305 | { "not.l", mode_da, class3|(11<<21)|(4), def }, |
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306 | { "not.w", mode_da, class3|(11<<21)|(2), def }, |
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307 | { "or.b", mode_dab, class3|(9<<21)|(1), def }, |
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308 | { "or.l", mode_dab, class3|(9<<21)|(4), def }, |
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309 | { "or.w", mode_dab, class3|(9<<21)|(2), def }, |
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310 | { "read.b", mode_dax, class3|(15<<21)|(1<<9)|(1), def }, |
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311 | { "read.l", mode_dax, class3|(15<<21)|(1<<9)|(4), def }, |
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312 | { "read.w", mode_dax, class3|(15<<21)|(1<<9)|(2), def }, |
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313 | { "readmda", mode_d, class3|(15<<21)|(1<<15)|(1<<9)|(4), def }, |
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314 | { "readmdb", mode_d, class3|(15<<21)|(1<<15)|(1<<9)|(1<<4)|(4), def }, |
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315 | { "readmdc", mode_d, class3|(15<<21)|(1<<15)|(1<<9)|(2<<4)|(4), def }, |
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316 | { "rfi", mode_s, class1|(7<<21)|(30<<16)|(29<<4)|(4), def }, |
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317 | { "rflag", mode_d, class3|(13<<21)|(4), def }, |
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318 | { "stop", mode_ir, class1|(0<<21)|(4), def }, |
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319 | { "sub.b", mode_dab, class3|(2<<21)|(1), def }, |
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320 | { "sub.l", mode_dab, class3|(2<<21)|(4), def }, |
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321 | { "sub.w", mode_dab, class3|(2<<21)|(2), def }, |
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322 | { "subc.b", mode_dab, class3|(3<<21)|(1), def }, |
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323 | { "subc.l", mode_dab, class3|(3<<21)|(4), def }, |
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324 | { "subc.w", mode_dab, class3|(3<<21)|(2), def }, |
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325 | { "subi", mode_ai, class2|(2<<21), def }, |
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326 | { "trace", mode_ir, class1|(13<<21), def }, |
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327 | { "write.b", mode_bax, class1|(15<<21)|(1), def }, |
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328 | { "write.l", mode_bax, class1|(15<<21)|(4), def }, |
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329 | { "write.w", mode_bax, class1|(15<<21)|(2), def }, |
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330 | { "writemd", mode_ab, class1|(15<<21)|(1<<15)|(4<<10)|(4), def }, |
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331 | { "writemdc", mode_a, class1|(15<<21)|(1<<15)|(5<<10)|(4), def }, |
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332 | { "wrtl", mode_i, class2|(8<<21), gr6 }, |
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333 | { "wrtu", mode_i, class2|(9<<21), gr6 }, |
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334 | { "xor.b", mode_dab, class3|(8<<21)|(1), def }, |
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335 | { "xor.l", mode_dab, class3|(8<<21)|(4), def }, |
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336 | { "xor.w", mode_dab, class3|(8<<21)|(2), def }, |
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337 | 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|