Rev 5191 | Details | Compare with Previous | Last modification | View Log | RSS feed
Rev | Author | Line No. | Line |
---|---|---|---|
5191 | serge | 1 | /* Definitions for opcode table for the sparc. |
6324 | serge | 2 | Copyright (C) 1989-2015 Free Software Foundation, Inc. |
5191 | serge | 3 | |
4 | This file is part of GAS, the GNU Assembler, GDB, the GNU debugger, and |
||
5 | the GNU Binutils. |
||
6 | |||
7 | GAS/GDB is free software; you can redistribute it and/or modify |
||
8 | it under the terms of the GNU General Public License as published by |
||
9 | the Free Software Foundation; either version 3, or (at your option) |
||
10 | any later version. |
||
11 | |||
12 | GAS/GDB is distributed in the hope that it will be useful, |
||
13 | but WITHOUT ANY WARRANTY; without even the implied warranty of |
||
14 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
||
15 | GNU General Public License for more details. |
||
16 | |||
17 | You should have received a copy of the GNU General Public License |
||
18 | along with GAS or GDB; see the file COPYING3. If not, write to |
||
19 | the Free Software Foundation, 51 Franklin Street - Fifth Floor, |
||
20 | Boston, MA 02110-1301, USA. */ |
||
21 | |||
22 | #include "ansidecl.h" |
||
23 | |||
24 | /* The SPARC opcode table (and other related data) is defined in |
||
25 | the opcodes library in sparc-opc.c. If you change anything here, make |
||
26 | sure you fix up that file, and vice versa. */ |
||
27 | |||
28 | /* FIXME-someday: perhaps the ,a's and such should be embedded in the |
||
29 | instruction's name rather than the args. This would make gas faster, pinsn |
||
30 | slower, but would mess up some macros a bit. xoxorich. */ |
||
31 | |||
32 | /* List of instruction sets variations. |
||
33 | These values are such that each element is either a superset of a |
||
34 | preceding each one or they conflict in which case SPARC_OPCODE_CONFLICT_P |
||
35 | returns non-zero. |
||
36 | The values are indices into `sparc_opcode_archs' defined in sparc-opc.c. |
||
37 | Don't change this without updating sparc-opc.c. */ |
||
38 | |||
39 | enum sparc_opcode_arch_val |
||
40 | { |
||
41 | SPARC_OPCODE_ARCH_V6 = 0, |
||
42 | SPARC_OPCODE_ARCH_V7, |
||
43 | SPARC_OPCODE_ARCH_V8, |
||
44 | SPARC_OPCODE_ARCH_LEON, |
||
45 | SPARC_OPCODE_ARCH_SPARCLET, |
||
46 | SPARC_OPCODE_ARCH_SPARCLITE, |
||
47 | /* V9 variants must appear last. */ |
||
48 | SPARC_OPCODE_ARCH_V9, |
||
49 | SPARC_OPCODE_ARCH_V9A, /* V9 with ultrasparc additions. */ |
||
50 | SPARC_OPCODE_ARCH_V9B, /* V9 with ultrasparc and cheetah additions. */ |
||
51 | SPARC_OPCODE_ARCH_BAD /* Error return from sparc_opcode_lookup_arch. */ |
||
52 | }; |
||
53 | |||
54 | /* The highest architecture in the table. */ |
||
55 | #define SPARC_OPCODE_ARCH_MAX (SPARC_OPCODE_ARCH_BAD - 1) |
||
56 | |||
57 | /* Given an enum sparc_opcode_arch_val, return the bitmask to use in |
||
58 | insn encoding/decoding. */ |
||
59 | #define SPARC_OPCODE_ARCH_MASK(arch) (1 << (arch)) |
||
60 | |||
61 | /* Given a valid sparc_opcode_arch_val, return non-zero if it's v9. */ |
||
62 | #define SPARC_OPCODE_ARCH_V9_P(arch) ((arch) >= SPARC_OPCODE_ARCH_V9) |
||
63 | |||
64 | /* Table of cpu variants. */ |
||
65 | |||
66 | typedef struct sparc_opcode_arch |
||
67 | { |
||
68 | const char *name; |
||
69 | /* Mask of sparc_opcode_arch_val's supported. |
||
70 | EG: For v7 this would be |
||
71 | (SPARC_OPCODE_ARCH_MASK (..._V6) | SPARC_OPCODE_ARCH_MASK (..._V7)). |
||
72 | These are short's because sparc_opcode.architecture is. */ |
||
73 | short supported; |
||
74 | } sparc_opcode_arch; |
||
75 | |||
76 | extern const struct sparc_opcode_arch sparc_opcode_archs[]; |
||
77 | |||
78 | /* Given architecture name, look up it's sparc_opcode_arch_val value. */ |
||
79 | extern enum sparc_opcode_arch_val sparc_opcode_lookup_arch (const char *); |
||
80 | |||
81 | /* Return the bitmask of supported architectures for ARCH. */ |
||
82 | #define SPARC_OPCODE_SUPPORTED(ARCH) (sparc_opcode_archs[ARCH].supported) |
||
83 | |||
84 | /* Non-zero if ARCH1 conflicts with ARCH2. |
||
85 | IE: ARCH1 as a supported bit set that ARCH2 doesn't, and vice versa. */ |
||
86 | #define SPARC_OPCODE_CONFLICT_P(ARCH1, ARCH2) \ |
||
87 | (((SPARC_OPCODE_SUPPORTED (ARCH1) & SPARC_OPCODE_SUPPORTED (ARCH2)) \ |
||
88 | != SPARC_OPCODE_SUPPORTED (ARCH1)) \ |
||
89 | && ((SPARC_OPCODE_SUPPORTED (ARCH1) & SPARC_OPCODE_SUPPORTED (ARCH2)) \ |
||
90 | != SPARC_OPCODE_SUPPORTED (ARCH2))) |
||
91 | |||
92 | /* Structure of an opcode table entry. */ |
||
93 | |||
94 | typedef struct sparc_opcode |
||
95 | { |
||
96 | const char *name; |
||
97 | unsigned long match; /* Bits that must be set. */ |
||
98 | unsigned long lose; /* Bits that must not be set. */ |
||
99 | const char *args; |
||
100 | /* This was called "delayed" in versions before the flags. */ |
||
101 | unsigned int flags; |
||
102 | unsigned int hwcaps; |
||
6324 | serge | 103 | unsigned int hwcaps2; |
5191 | serge | 104 | short architecture; /* Bitmask of sparc_opcode_arch_val's. */ |
105 | } sparc_opcode; |
||
106 | |||
107 | /* FIXME: Add F_ANACHRONISTIC flag for v9. */ |
||
108 | #define F_DELAYED 0x00000001 /* Delayed branch. */ |
||
109 | #define F_ALIAS 0x00000002 /* Alias for a "real" instruction. */ |
||
110 | #define F_UNBR 0x00000004 /* Unconditional branch. */ |
||
111 | #define F_CONDBR 0x00000008 /* Conditional branch. */ |
||
112 | #define F_JSR 0x00000010 /* Subroutine call. */ |
||
113 | #define F_FLOAT 0x00000020 /* Floating point instruction (not a branch). */ |
||
114 | #define F_FBR 0x00000040 /* Floating point branch. */ |
||
115 | #define F_PREFERRED 0x00000080 /* A preferred alias. */ |
||
116 | |||
117 | #define F_PREF_ALIAS (F_ALIAS|F_PREFERRED) |
||
118 | |||
6324 | serge | 119 | /* These must match the ELF_SPARC_HWCAP_* and ELF_SPARC_HWCAP2_* |
120 | values precisely. See include/elf/sparc.h. */ |
||
5191 | serge | 121 | #define HWCAP_MUL32 0x00000001 /* umul/umulcc/smul/smulcc insns */ |
122 | #define HWCAP_DIV32 0x00000002 /* udiv/udivcc/sdiv/sdivcc insns */ |
||
123 | #define HWCAP_FSMULD 0x00000004 /* 'fsmuld' insn */ |
||
124 | #define HWCAP_V8PLUS 0x00000008 /* v9 insns available to 32bit */ |
||
125 | #define HWCAP_POPC 0x00000010 /* 'popc' insn */ |
||
126 | #define HWCAP_VIS 0x00000020 /* VIS insns */ |
||
127 | #define HWCAP_VIS2 0x00000040 /* VIS2 insns */ |
||
128 | #define HWCAP_ASI_BLK_INIT \ |
||
129 | 0x00000080 /* block init ASIs */ |
||
130 | #define HWCAP_FMAF 0x00000100 /* fused multiply-add */ |
||
131 | #define HWCAP_VIS3 0x00000400 /* VIS3 insns */ |
||
132 | #define HWCAP_HPC 0x00000800 /* HPC insns */ |
||
133 | #define HWCAP_RANDOM 0x00001000 /* 'random' insn */ |
||
134 | #define HWCAP_TRANS 0x00002000 /* transaction insns */ |
||
135 | #define HWCAP_FJFMAU 0x00004000 /* unfused multiply-add */ |
||
136 | #define HWCAP_IMA 0x00008000 /* integer multiply-add */ |
||
137 | #define HWCAP_ASI_CACHE_SPARING \ |
||
138 | 0x00010000 /* cache sparing ASIs */ |
||
139 | #define HWCAP_AES 0x00020000 /* AES crypto insns */ |
||
140 | #define HWCAP_DES 0x00040000 /* DES crypto insns */ |
||
141 | #define HWCAP_KASUMI 0x00080000 /* KASUMI crypto insns */ |
||
142 | #define HWCAP_CAMELLIA 0x00100000 /* CAMELLIA crypto insns */ |
||
143 | #define HWCAP_MD5 0x00200000 /* MD5 hashing insns */ |
||
144 | #define HWCAP_SHA1 0x00400000 /* SHA1 hashing insns */ |
||
145 | #define HWCAP_SHA256 0x00800000 /* SHA256 hashing insns */ |
||
146 | #define HWCAP_SHA512 0x01000000 /* SHA512 hashing insns */ |
||
147 | #define HWCAP_MPMUL 0x02000000 /* Multiple Precision Multiply */ |
||
148 | #define HWCAP_MONT 0x04000000 /* Montgomery Mult/Sqrt */ |
||
149 | #define HWCAP_PAUSE 0x08000000 /* Pause insn */ |
||
150 | #define HWCAP_CBCOND 0x10000000 /* Compare and Branch insns */ |
||
151 | #define HWCAP_CRC32C 0x20000000 /* CRC32C insn */ |
||
152 | |||
6324 | serge | 153 | #define HWCAP2_FJATHPLUS 0x00000001 /* Fujitsu Athena+ */ |
154 | #define HWCAP2_VIS3B 0x00000002 /* Subset of VIS3 present on sparc64 X+. */ |
||
155 | #define HWCAP2_ADP 0x00000004 /* Application Data Protection */ |
||
156 | #define HWCAP2_SPARC5 0x00000008 /* The 29 new fp and sub instructions */ |
||
157 | #define HWCAP2_MWAIT 0x00000010 /* mwait instruction and load/monitor ASIs */ |
||
158 | #define HWCAP2_XMPMUL 0x00000020 /* XOR multiple precision multiply */ |
||
159 | #define HWCAP2_XMONT 0x00000040 /* XOR Montgomery mult/sqr instructions */ |
||
160 | #define HWCAP2_NSEC \ |
||
161 | 0x00000080 /* pause insn with support for nsec timings */ |
||
162 | #define HWCAP2_FJATHHPC 0x00001000 /* Fujitsu HPC instrs */ |
||
163 | #define HWCAP2_FJDES 0x00002000 /* Fujitsu DES instrs */ |
||
164 | #define HWCAP2_FJAES 0x00010000 /* Fujitsu AES instrs */ |
||
165 | |||
166 | |||
5191 | serge | 167 | /* All sparc opcodes are 32 bits, except for the `set' instruction (really a |
168 | macro), which is 64 bits. It is handled as a special case. |
||
169 | |||
170 | The match component is a mask saying which bits must match a particular |
||
171 | opcode in order for an instruction to be an instance of that opcode. |
||
172 | |||
173 | The args component is a string containing one character for each operand of the |
||
174 | instruction. |
||
175 | |||
176 | Kinds of operands: |
||
177 | # Number used by optimizer. It is ignored. |
||
178 | 1 rs1 register. |
||
179 | 2 rs2 register. |
||
180 | d rd register. |
||
181 | e frs1 floating point register. |
||
182 | v frs1 floating point register (double/even). |
||
183 | V frs1 floating point register (quad/multiple of 4). |
||
184 | f frs2 floating point register. |
||
185 | B frs2 floating point register (double/even). |
||
186 | R frs2 floating point register (quad/multiple of 4). |
||
187 | 4 frs3 floating point register. |
||
188 | 5 frs3 floating point register (doube/even). |
||
189 | g frsd floating point register. |
||
190 | H frsd floating point register (double/even). |
||
191 | J frsd floating point register (quad/multiple of 4). |
||
6324 | serge | 192 | } frsd floating point register (double/even) that is == frs2 |
5191 | serge | 193 | b crs1 coprocessor register |
194 | c crs2 coprocessor register |
||
195 | D crsd coprocessor register |
||
196 | m alternate space register (asr) in rd |
||
197 | M alternate space register (asr) in rs1 |
||
198 | h 22 high bits. |
||
199 | X 5 bit unsigned immediate |
||
200 | Y 6 bit unsigned immediate |
||
201 | 3 SIAM mode (3 bits). (v9b) |
||
202 | K MEMBAR mask (7 bits). (v9) |
||
203 | j 10 bit Immediate. (v9) |
||
204 | I 11 bit Immediate. (v9) |
||
205 | i 13 bit Immediate. |
||
206 | n 22 bit immediate. |
||
207 | k 2+14 bit PC relative immediate. (v9) |
||
208 | G 19 bit PC relative immediate. (v9) |
||
209 | l 22 bit PC relative immediate. |
||
210 | L 30 bit PC relative immediate. |
||
211 | a Annul. The annul bit is set. |
||
212 | A Alternate address space. Stored as 8 bits. |
||
213 | C Coprocessor state register. |
||
214 | F floating point state register. |
||
215 | p Processor state register. |
||
216 | N Branch predict clear ",pn" (v9) |
||
217 | T Branch predict set ",pt" (v9) |
||
218 | z %icc. (v9) |
||
219 | Z %xcc. (v9) |
||
220 | q Floating point queue. |
||
221 | r Single register that is both rs1 and rd. |
||
222 | O Single register that is both rs2 and rd. |
||
223 | Q Coprocessor queue. |
||
224 | S Special case. |
||
225 | t Trap base register. |
||
226 | w Window invalid mask register. |
||
227 | y Y register. |
||
228 | u sparclet coprocessor registers in rd position |
||
229 | U sparclet coprocessor registers in rs1 position |
||
230 | E %ccr. (v9) |
||
231 | s %fprs. (v9) |
||
232 | P %pc. (v9) |
||
233 | W %tick. (v9) |
||
6324 | serge | 234 | { %mcdper. (v9b) |
5191 | serge | 235 | o %asi. (v9) |
236 | 6 %fcc0. (v9) |
||
237 | 7 %fcc1. (v9) |
||
238 | 8 %fcc2. (v9) |
||
239 | 9 %fcc3. (v9) |
||
240 | ! Privileged Register in rd (v9) |
||
241 | ? Privileged Register in rs1 (v9) |
||
242 | * Prefetch function constant. (v9) |
||
243 | x OPF field (v9 impdep). |
||
244 | |||
245 | _ Ancillary state register in rd (v9a) |
||
246 | / Ancillary state register in rs1 (v9a) |
||
247 | ( entire floating point state register (%efsr) |
||
248 | ) 5 bit immediate placed in RS3 field |
||
249 | = 2+8 bit PC relative immediate. (v9) */ |
||
250 | |||
251 | #define OP2(x) (((x) & 0x7) << 22) /* Op2 field of format2 insns. */ |
||
252 | #define OP3(x) (((x) & 0x3f) << 19) /* Op3 field of format3 insns. */ |
||
253 | #define OP(x) ((unsigned) ((x) & 0x3) << 30) /* Op field of all insns. */ |
||
254 | #define OPF(x) (((x) & 0x1ff) << 5) /* Opf field of float insns. */ |
||
255 | #define OPF_LOW5(x) OPF ((x) & 0x1f) /* V9. */ |
||
256 | #define OPF_LOW4(x) OPF ((x) & 0xf) /* V9. */ |
||
257 | #define F3F(x, y, z) (OP (x) | OP3 (y) | OPF (z)) /* Format3 float insns. */ |
||
258 | #define F3F4(x, y, z) (OP (x) | OP3 (y) | OPF_LOW4 (z)) |
||
259 | #define F3I(x) (((x) & 0x1) << 13) /* Immediate field of format 3 insns. */ |
||
260 | #define F2(x, y) (OP (x) | OP2(y)) /* Format 2 insns. */ |
||
261 | #define F3(x, y, z) (OP (x) | OP3(y) | F3I(z)) /* Format3 insns. */ |
||
262 | #define F1(x) (OP (x)) |
||
263 | #define DISP30(x) ((x) & 0x3fffffff) |
||
264 | #define ASI(x) (((x) & 0xff) << 5) /* Asi field of format3 insns. */ |
||
265 | #define RS2(x) ((x) & 0x1f) /* Rs2 field. */ |
||
266 | #define SIMM13(x) ((x) & 0x1fff) /* Simm13 field. */ |
||
267 | #define RD(x) (((x) & 0x1f) << 25) /* Destination register field. */ |
||
268 | #define RS1(x) (((x) & 0x1f) << 14) /* Rs1 field. */ |
||
269 | #define RS3(x) (((x) & 0x1f) << 9) /* Rs3 field. */ |
||
270 | #define ASI_RS2(x) (SIMM13 (x)) |
||
271 | #define MEMBAR(x) ((x) & 0x7f) |
||
272 | #define SLCPOP(x) (((x) & 0x7f) << 6) /* Sparclet cpop. */ |
||
273 | |||
274 | #define ANNUL (1 << 29) |
||
275 | #define BPRED (1 << 19) /* V9. */ |
||
276 | #define IMMED F3I (1) |
||
277 | #define RD_G0 RD (~0) |
||
278 | #define RS1_G0 RS1 (~0) |
||
279 | #define RS2_G0 RS2 (~0) |
||
280 | |||
281 | extern const struct sparc_opcode sparc_opcodes[]; |
||
282 | extern const int sparc_num_opcodes; |
||
283 | |||
284 | extern int sparc_encode_asi (const char *); |
||
285 | extern const char *sparc_decode_asi (int); |
||
286 | extern int sparc_encode_membar (const char *); |
||
287 | extern const char *sparc_decode_membar (int); |
||
288 | extern int sparc_encode_prefetch (const char *); |
||
289 | extern const char *sparc_decode_prefetch (int); |
||
290 | extern int sparc_encode_sparclet_cpreg (const char *); |
||
291 | extern const char *sparc_decode_sparclet_cpreg (int); |
||
292 | |||
293 | /* Local Variables: |
||
294 | fill-column: 131 |
||
295 | comment-column: 0 |
||
296 | End: */><>><>><>><>><>><>><>><>><>><>><>><>><> |
||
297 |