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5191 | serge | 1 | /* ppc.h -- Header file for PowerPC opcode table |
2 | Copyright 1994, 1995, 1999, 2000, 2001, 2002, 2003, 2004, 2005, 2006, |
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3 | 2007, 2008, 2009, 2010, 2012 Free Software Foundation, Inc. |
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4 | Written by Ian Lance Taylor, Cygnus Support |
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5 | |||
6 | This file is part of GDB, GAS, and the GNU binutils. |
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7 | |||
8 | GDB, GAS, and the GNU binutils are free software; you can redistribute |
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9 | them and/or modify them under the terms of the GNU General Public |
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10 | License as published by the Free Software Foundation; either version 3, |
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11 | or (at your option) any later version. |
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12 | |||
13 | GDB, GAS, and the GNU binutils are distributed in the hope that they |
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14 | will be useful, but WITHOUT ANY WARRANTY; without even the implied |
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15 | warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See |
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16 | the GNU General Public License for more details. |
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17 | |||
18 | You should have received a copy of the GNU General Public License |
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19 | along with this file; see the file COPYING3. If not, write to the Free |
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20 | Software Foundation, 51 Franklin Street - Fifth Floor, Boston, |
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21 | MA 02110-1301, USA. */ |
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22 | |||
23 | #ifndef PPC_H |
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24 | #define PPC_H |
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25 | |||
26 | #include "bfd_stdint.h" |
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27 | |||
28 | typedef uint64_t ppc_cpu_t; |
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29 | |||
30 | /* The opcode table is an array of struct powerpc_opcode. */ |
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31 | |||
32 | struct powerpc_opcode |
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33 | { |
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34 | /* The opcode name. */ |
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35 | const char *name; |
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36 | |||
37 | /* The opcode itself. Those bits which will be filled in with |
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38 | operands are zeroes. */ |
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39 | unsigned long opcode; |
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40 | |||
41 | /* The opcode mask. This is used by the disassembler. This is a |
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42 | mask containing ones indicating those bits which must match the |
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43 | opcode field, and zeroes indicating those bits which need not |
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44 | match (and are presumably filled in by operands). */ |
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45 | unsigned long mask; |
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46 | |||
47 | /* One bit flags for the opcode. These are used to indicate which |
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48 | specific processors support the instructions. The defined values |
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49 | are listed below. */ |
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50 | ppc_cpu_t flags; |
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51 | |||
52 | /* One bit flags for the opcode. These are used to indicate which |
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53 | specific processors no longer support the instructions. The defined |
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54 | values are listed below. */ |
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55 | ppc_cpu_t deprecated; |
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56 | |||
57 | /* An array of operand codes. Each code is an index into the |
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58 | operand table. They appear in the order which the operands must |
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59 | appear in assembly code, and are terminated by a zero. */ |
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60 | unsigned char operands[8]; |
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61 | }; |
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62 | |||
63 | /* The table itself is sorted by major opcode number, and is otherwise |
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64 | in the order in which the disassembler should consider |
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65 | instructions. */ |
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66 | extern const struct powerpc_opcode powerpc_opcodes[]; |
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67 | extern const int powerpc_num_opcodes; |
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68 | extern const struct powerpc_opcode vle_opcodes[]; |
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69 | extern const int vle_num_opcodes; |
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70 | |||
71 | /* Values defined for the flags field of a struct powerpc_opcode. */ |
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72 | |||
73 | /* Opcode is defined for the PowerPC architecture. */ |
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74 | #define PPC_OPCODE_PPC 1 |
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75 | |||
76 | /* Opcode is defined for the POWER (RS/6000) architecture. */ |
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77 | #define PPC_OPCODE_POWER 2 |
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78 | |||
79 | /* Opcode is defined for the POWER2 (Rios 2) architecture. */ |
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80 | #define PPC_OPCODE_POWER2 4 |
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81 | |||
82 | /* Opcode is supported by the Motorola PowerPC 601 processor. The 601 |
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83 | is assumed to support all PowerPC (PPC_OPCODE_PPC) instructions, |
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84 | but it also supports many additional POWER instructions. */ |
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85 | #define PPC_OPCODE_601 8 |
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86 | |||
87 | /* Opcode is supported in both the Power and PowerPC architectures |
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88 | (ie, compiler's -mcpu=common or assembler's -mcom). More than just |
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89 | the intersection of PPC_OPCODE_PPC with the union of PPC_OPCODE_POWER |
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90 | and PPC_OPCODE_POWER2 because many instructions changed mnemonics |
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91 | between POWER and POWERPC. */ |
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92 | #define PPC_OPCODE_COMMON 0x10 |
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93 | |||
94 | /* Opcode is supported for any Power or PowerPC platform (this is |
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95 | for the assembler's -many option, and it eliminates duplicates). */ |
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96 | #define PPC_OPCODE_ANY 0x20 |
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97 | |||
98 | /* Opcode is only defined on 64 bit architectures. */ |
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99 | #define PPC_OPCODE_64 0x40 |
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100 | |||
101 | /* Opcode is supported as part of the 64-bit bridge. */ |
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102 | #define PPC_OPCODE_64_BRIDGE 0x80 |
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103 | |||
104 | /* Opcode is supported by Altivec Vector Unit */ |
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105 | #define PPC_OPCODE_ALTIVEC 0x100 |
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106 | |||
107 | /* Opcode is supported by PowerPC 403 processor. */ |
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108 | #define PPC_OPCODE_403 0x200 |
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109 | |||
110 | /* Opcode is supported by PowerPC BookE processor. */ |
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111 | #define PPC_OPCODE_BOOKE 0x400 |
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112 | |||
113 | /* Opcode is supported by PowerPC 440 processor. */ |
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114 | #define PPC_OPCODE_440 0x800 |
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115 | |||
116 | /* Opcode is only supported by Power4 architecture. */ |
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117 | #define PPC_OPCODE_POWER4 0x1000 |
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118 | |||
119 | /* Opcode is only supported by Power7 architecture. */ |
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120 | #define PPC_OPCODE_POWER7 0x2000 |
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121 | |||
122 | /* Opcode is only supported by e500x2 Core. */ |
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123 | #define PPC_OPCODE_SPE 0x4000 |
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124 | |||
125 | /* Opcode is supported by e500x2 Integer select APU. */ |
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126 | #define PPC_OPCODE_ISEL 0x8000 |
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127 | |||
128 | /* Opcode is an e500 SPE floating point instruction. */ |
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129 | #define PPC_OPCODE_EFS 0x10000 |
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130 | |||
131 | /* Opcode is supported by branch locking APU. */ |
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132 | #define PPC_OPCODE_BRLOCK 0x20000 |
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133 | |||
134 | /* Opcode is supported by performance monitor APU. */ |
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135 | #define PPC_OPCODE_PMR 0x40000 |
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136 | |||
137 | /* Opcode is supported by cache locking APU. */ |
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138 | #define PPC_OPCODE_CACHELCK 0x80000 |
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139 | |||
140 | /* Opcode is supported by machine check APU. */ |
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141 | #define PPC_OPCODE_RFMCI 0x100000 |
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142 | |||
143 | /* Opcode is only supported by Power5 architecture. */ |
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144 | #define PPC_OPCODE_POWER5 0x200000 |
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145 | |||
146 | /* Opcode is supported by PowerPC e300 family. */ |
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147 | #define PPC_OPCODE_E300 0x400000 |
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148 | |||
149 | /* Opcode is only supported by Power6 architecture. */ |
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150 | #define PPC_OPCODE_POWER6 0x800000 |
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151 | |||
152 | /* Opcode is only supported by PowerPC Cell family. */ |
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153 | #define PPC_OPCODE_CELL 0x1000000 |
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154 | |||
155 | /* Opcode is supported by CPUs with paired singles support. */ |
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156 | #define PPC_OPCODE_PPCPS 0x2000000 |
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157 | |||
158 | /* Opcode is supported by Power E500MC */ |
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159 | #define PPC_OPCODE_E500MC 0x4000000 |
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160 | |||
161 | /* Opcode is supported by PowerPC 405 processor. */ |
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162 | #define PPC_OPCODE_405 0x8000000 |
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163 | |||
164 | /* Opcode is supported by Vector-Scalar (VSX) Unit */ |
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165 | #define PPC_OPCODE_VSX 0x10000000 |
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166 | |||
167 | /* Opcode is supported by A2. */ |
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168 | #define PPC_OPCODE_A2 0x20000000 |
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169 | |||
170 | /* Opcode is supported by PowerPC 476 processor. */ |
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171 | #define PPC_OPCODE_476 0x40000000 |
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172 | |||
173 | /* Opcode is supported by AppliedMicro Titan core */ |
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174 | #define PPC_OPCODE_TITAN 0x80000000 |
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175 | |||
176 | /* Opcode which is supported by the e500 family */ |
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177 | #define PPC_OPCODE_E500 0x100000000ull |
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178 | |||
179 | /* Opcode is supported by Extended Altivec Vector Unit */ |
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180 | #define PPC_OPCODE_ALTIVEC2 0x200000000ull |
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181 | |||
182 | /* Opcode is supported by Power E6500 */ |
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183 | #define PPC_OPCODE_E6500 0x400000000ull |
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184 | |||
185 | /* Opcode is supported by Thread management APU */ |
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186 | #define PPC_OPCODE_TMR 0x800000000ull |
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187 | |||
188 | /* Opcode which is supported by the VLE extension. */ |
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189 | #define PPC_OPCODE_VLE 0x1000000000ull |
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190 | |||
191 | /* Opcode is only supported by Power8 architecture. */ |
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192 | #define PPC_OPCODE_POWER8 0x2000000000ull |
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193 | |||
194 | /* Opcode which is supported by the Hardware Transactional Memory extension. */ |
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195 | /* Currently, this is the same as the POWER8 mask. If another cpu comes out |
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196 | that isn't a superset of POWER8, we can define this to its own mask. */ |
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197 | #define PPC_OPCODE_HTM PPC_OPCODE_POWER8 |
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198 | |||
199 | /* A macro to extract the major opcode from an instruction. */ |
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200 | #define PPC_OP(i) (((i) >> 26) & 0x3f) |
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201 | |||
202 | /* A macro to determine if the instruction is a 2-byte VLE insn. */ |
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203 | #define PPC_OP_SE_VLE(m) ((m) <= 0xffff) |
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204 | |||
205 | /* A macro to extract the major opcode from a VLE instruction. */ |
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206 | #define VLE_OP(i,m) (((i) >> ((m) <= 0xffff ? 10 : 26)) & 0x3f) |
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207 | |||
208 | /* A macro to convert a VLE opcode to a VLE opcode segment. */ |
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209 | #define VLE_OP_TO_SEG(i) ((i) >> 1) |
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210 | |||
211 | /* The operands table is an array of struct powerpc_operand. */ |
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212 | |||
213 | struct powerpc_operand |
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214 | { |
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215 | /* A bitmask of bits in the operand. */ |
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216 | unsigned int bitm; |
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217 | |||
218 | /* The shift operation to be applied to the operand. No shift |
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219 | is made if this is zero. For positive values, the operand |
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220 | is shifted left by SHIFT. For negative values, the operand |
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221 | is shifted right by -SHIFT. Use PPC_OPSHIFT_INV to indicate |
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222 | that BITM and SHIFT cannot be used to determine where the |
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223 | operand goes in the insn. */ |
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224 | int shift; |
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225 | |||
226 | /* Insertion function. This is used by the assembler. To insert an |
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227 | operand value into an instruction, check this field. |
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228 | |||
229 | If it is NULL, execute |
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230 | if (o->shift >= 0) |
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231 | i |= (op & o->bitm) << o->shift; |
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232 | else |
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233 | i |= (op & o->bitm) >> -o->shift; |
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234 | (i is the instruction which we are filling in, o is a pointer to |
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235 | this structure, and op is the operand value). |
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236 | |||
237 | If this field is not NULL, then simply call it with the |
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238 | instruction and the operand value. It will return the new value |
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239 | of the instruction. If the ERRMSG argument is not NULL, then if |
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240 | the operand value is illegal, *ERRMSG will be set to a warning |
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241 | string (the operand will be inserted in any case). If the |
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242 | operand value is legal, *ERRMSG will be unchanged (most operands |
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243 | can accept any value). */ |
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244 | unsigned long (*insert) |
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245 | (unsigned long instruction, long op, ppc_cpu_t dialect, const char **errmsg); |
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246 | |||
247 | /* Extraction function. This is used by the disassembler. To |
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248 | extract this operand type from an instruction, check this field. |
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249 | |||
250 | If it is NULL, compute |
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251 | if (o->shift >= 0) |
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252 | op = (i >> o->shift) & o->bitm; |
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253 | else |
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254 | op = (i << -o->shift) & o->bitm; |
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255 | if ((o->flags & PPC_OPERAND_SIGNED) != 0) |
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256 | sign_extend (op); |
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257 | (i is the instruction, o is a pointer to this structure, and op |
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258 | is the result). |
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259 | |||
260 | If this field is not NULL, then simply call it with the |
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261 | instruction value. It will return the value of the operand. If |
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262 | the INVALID argument is not NULL, *INVALID will be set to |
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263 | non-zero if this operand type can not actually be extracted from |
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264 | this operand (i.e., the instruction does not match). If the |
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265 | operand is valid, *INVALID will not be changed. */ |
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266 | long (*extract) (unsigned long instruction, ppc_cpu_t dialect, int *invalid); |
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267 | |||
268 | /* One bit syntax flags. */ |
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269 | unsigned long flags; |
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270 | }; |
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271 | |||
272 | /* Elements in the table are retrieved by indexing with values from |
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273 | the operands field of the powerpc_opcodes table. */ |
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274 | |||
275 | extern const struct powerpc_operand powerpc_operands[]; |
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276 | extern const unsigned int num_powerpc_operands; |
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277 | |||
278 | /* Use with the shift field of a struct powerpc_operand to indicate |
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279 | that BITM and SHIFT cannot be used to determine where the operand |
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280 | goes in the insn. */ |
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281 | #define PPC_OPSHIFT_INV (-1 << 31) |
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282 | |||
283 | /* Values defined for the flags field of a struct powerpc_operand. */ |
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284 | |||
285 | /* This operand takes signed values. */ |
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286 | #define PPC_OPERAND_SIGNED (0x1) |
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287 | |||
288 | /* This operand takes signed values, but also accepts a full positive |
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289 | range of values when running in 32 bit mode. That is, if bits is |
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290 | 16, it takes any value from -0x8000 to 0xffff. In 64 bit mode, |
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291 | this flag is ignored. */ |
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292 | #define PPC_OPERAND_SIGNOPT (0x2) |
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293 | |||
294 | /* This operand does not actually exist in the assembler input. This |
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295 | is used to support extended mnemonics such as mr, for which two |
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296 | operands fields are identical. The assembler should call the |
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297 | insert function with any op value. The disassembler should call |
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298 | the extract function, ignore the return value, and check the value |
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299 | placed in the valid argument. */ |
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300 | #define PPC_OPERAND_FAKE (0x4) |
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301 | |||
302 | /* The next operand should be wrapped in parentheses rather than |
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303 | separated from this one by a comma. This is used for the load and |
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304 | store instructions which want their operands to look like |
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305 | reg,displacement(reg) |
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306 | */ |
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307 | #define PPC_OPERAND_PARENS (0x8) |
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308 | |||
309 | /* This operand may use the symbolic names for the CR fields, which |
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310 | are |
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311 | lt 0 gt 1 eq 2 so 3 un 3 |
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312 | cr0 0 cr1 1 cr2 2 cr3 3 |
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313 | cr4 4 cr5 5 cr6 6 cr7 7 |
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314 | These may be combined arithmetically, as in cr2*4+gt. These are |
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315 | only supported on the PowerPC, not the POWER. */ |
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316 | #define PPC_OPERAND_CR_BIT (0x10) |
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317 | |||
318 | /* This operand names a register. The disassembler uses this to print |
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319 | register names with a leading 'r'. */ |
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320 | #define PPC_OPERAND_GPR (0x20) |
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321 | |||
322 | /* Like PPC_OPERAND_GPR, but don't print a leading 'r' for r0. */ |
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323 | #define PPC_OPERAND_GPR_0 (0x40) |
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324 | |||
325 | /* This operand names a floating point register. The disassembler |
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326 | prints these with a leading 'f'. */ |
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327 | #define PPC_OPERAND_FPR (0x80) |
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328 | |||
329 | /* This operand is a relative branch displacement. The disassembler |
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330 | prints these symbolically if possible. */ |
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331 | #define PPC_OPERAND_RELATIVE (0x100) |
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332 | |||
333 | /* This operand is an absolute branch address. The disassembler |
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334 | prints these symbolically if possible. */ |
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335 | #define PPC_OPERAND_ABSOLUTE (0x200) |
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336 | |||
337 | /* This operand is optional, and is zero if omitted. This is used for |
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338 | example, in the optional BF field in the comparison instructions. The |
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339 | assembler must count the number of operands remaining on the line, |
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340 | and the number of operands remaining for the opcode, and decide |
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341 | whether this operand is present or not. The disassembler should |
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342 | print this operand out only if it is not zero. */ |
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343 | #define PPC_OPERAND_OPTIONAL (0x400) |
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344 | |||
345 | /* This flag is only used with PPC_OPERAND_OPTIONAL. If this operand |
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346 | is omitted, then for the next operand use this operand value plus |
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347 | 1, ignoring the next operand field for the opcode. This wretched |
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348 | hack is needed because the Power rotate instructions can take |
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349 | either 4 or 5 operands. The disassembler should print this operand |
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350 | out regardless of the PPC_OPERAND_OPTIONAL field. */ |
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351 | #define PPC_OPERAND_NEXT (0x800) |
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352 | |||
353 | /* This operand should be regarded as a negative number for the |
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354 | purposes of overflow checking (i.e., the normal most negative |
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355 | number is disallowed and one more than the normal most positive |
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356 | number is allowed). This flag will only be set for a signed |
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357 | operand. */ |
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358 | #define PPC_OPERAND_NEGATIVE (0x1000) |
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359 | |||
360 | /* This operand names a vector unit register. The disassembler |
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361 | prints these with a leading 'v'. */ |
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362 | #define PPC_OPERAND_VR (0x2000) |
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363 | |||
364 | /* This operand is for the DS field in a DS form instruction. */ |
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365 | #define PPC_OPERAND_DS (0x4000) |
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366 | |||
367 | /* This operand is for the DQ field in a DQ form instruction. */ |
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368 | #define PPC_OPERAND_DQ (0x8000) |
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369 | |||
370 | /* Valid range of operand is 0..n rather than 0..n-1. */ |
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371 | #define PPC_OPERAND_PLUS1 (0x10000) |
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372 | |||
373 | /* Xilinx APU and FSL related operands */ |
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374 | #define PPC_OPERAND_FSL (0x20000) |
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375 | #define PPC_OPERAND_FCR (0x40000) |
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376 | #define PPC_OPERAND_UDI (0x80000) |
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377 | |||
378 | /* This operand names a vector-scalar unit register. The disassembler |
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379 | prints these with a leading 'vs'. */ |
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380 | #define PPC_OPERAND_VSR (0x100000) |
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381 | |||
382 | /* This is a CR FIELD that does not use symbolic names. */ |
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383 | #define PPC_OPERAND_CR_REG (0x200000) |
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384 | |||
385 | /* The POWER and PowerPC assemblers use a few macros. We keep them |
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386 | with the operands table for simplicity. The macro table is an |
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387 | array of struct powerpc_macro. */ |
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388 | |||
389 | struct powerpc_macro |
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390 | { |
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391 | /* The macro name. */ |
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392 | const char *name; |
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393 | |||
394 | /* The number of operands the macro takes. */ |
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395 | unsigned int operands; |
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396 | |||
397 | /* One bit flags for the opcode. These are used to indicate which |
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398 | specific processors support the instructions. The values are the |
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399 | same as those for the struct powerpc_opcode flags field. */ |
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400 | ppc_cpu_t flags; |
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401 | |||
402 | /* A format string to turn the macro into a normal instruction. |
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403 | Each %N in the string is replaced with operand number N (zero |
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404 | based). */ |
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405 | const char *format; |
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406 | }; |
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407 | |||
408 | extern const struct powerpc_macro powerpc_macros[]; |
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409 | extern const int powerpc_num_macros; |
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410 | |||
411 | extern ppc_cpu_t ppc_parse_cpu (ppc_cpu_t, ppc_cpu_t *, const char *); |
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412 | |||
413 | #endif /* PPC_H */><>><>><>=>=> |