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| Rev | Author | Line No. | Line |
|---|---|---|---|
| 5191 | serge | 1 | /* ns32k-opcode.h -- Opcode table for National Semi 32k processor |
| 2 | Copyright 1987, 1991, 1994, 2002, 2010 Free Software Foundation, Inc. |
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| 3 | |||
| 4 | This file is part of GAS, the GNU Assembler. |
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| 5 | |||
| 6 | GAS is free software; you can redistribute it and/or modify |
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| 7 | it under the terms of the GNU General Public License as published by |
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| 8 | the Free Software Foundation; either version 3, or (at your option) |
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| 9 | any later version. |
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| 10 | |||
| 11 | GAS is distributed in the hope that it will be useful, |
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| 12 | but WITHOUT ANY WARRANTY; without even the implied warranty of |
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| 13 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
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| 14 | GNU General Public License for more details. |
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| 15 | |||
| 16 | You should have received a copy of the GNU General Public License |
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| 17 | along with GAS; see the file COPYING3. If not, write to |
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| 18 | the Free Software Foundation, 51 Franklin Street - Fifth Floor, |
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| 19 | Boston, MA 02110-1301, USA. */ |
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| 20 | |||
| 21 | #ifdef SEQUENT_COMPATABILITY |
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| 22 | #define DEF_MODEC 20 |
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| 23 | #define DEF_MODEL 21 |
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| 24 | #endif |
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| 25 | |||
| 26 | #ifndef DEF_MODEC |
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| 27 | #define DEF_MODEC 20 |
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| 28 | #endif |
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| 29 | |||
| 30 | #ifndef DEF_MODEL |
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| 31 | #define DEF_MODEL 20 |
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| 32 | #endif |
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| 33 | /* |
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| 34 | After deciding the instruction entry (via hash.c) the instruction parser |
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| 35 | will try to match the operands after the instruction to the required set |
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| 36 | given in the entry operandfield. Every operand will result in a change in |
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| 37 | the opcode or the addition of data to the opcode. |
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| 38 | The operands in the source instruction are checked for inconsistent |
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| 39 | semantics. |
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| 40 | |||
| 41 | F : 32 bit float general form |
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| 42 | L : 64 bit float " |
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| 43 | B : byte " |
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| 44 | W : word " |
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| 45 | D : double-word " |
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| 46 | A : double-word gen-address-form ie no regs, no immediate |
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| 47 | I : integer writeable gen int except immediate (A + reg) |
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| 48 | Z : floating writeable gen float except immediate (Z + freg) |
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| 49 | d : displacement |
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| 50 | b : displacement - pc relative addressing acb |
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| 51 | p : displacement - pc relative addressing br bcond bsr cxp |
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| 52 | q : quick |
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| 53 | i : immediate (8 bits) |
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| 54 | This is not a standard ns32k operandtype, it is used to build |
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| 55 | instructions like svc arg1,arg2 |
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| 56 | Svc is the instruction SuperVisorCall and is sometimes used to |
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| 57 | call OS-routines from usermode. Some args might be handy! |
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| 58 | r : register number (3 bits) |
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| 59 | O : setcfg instruction optionslist |
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| 60 | C : cinv instruction optionslist |
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| 61 | S : stringinstruction optionslist |
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| 62 | U : registerlist save,enter |
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| 63 | u : registerlist restore,exit |
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| 64 | M : mmu register |
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| 65 | P : cpu register |
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| 66 | g : 3:rd operand of inss or exts instruction |
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| 67 | G : 4:th operand of inss or exts instruction |
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| 68 | Those operands are encoded in the same byte. |
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| 69 | This byte is placed last in the instruction. |
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| 70 | f : operand of sfsr |
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| 71 | H : sequent-hack for bsr (Warning) |
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| 72 | |||
| 73 | column 1 instructions |
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| 74 | 2 number of bits in opcode. |
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| 75 | 3 number of bits in opcode explicitly |
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| 76 | determined by the instruction type. |
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| 77 | 4 opcodeseed, the number we build our opcode |
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| 78 | from. |
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| 79 | 5 operandtypes, used by operandparser. |
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| 80 | 6 size in bytes of immediate |
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| 81 | */ |
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| 82 | struct ns32k_opcode { |
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| 83 | const char *name; |
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| 84 | unsigned char opcode_id_size; /* not used by the assembler */ |
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| 85 | unsigned char opcode_size; |
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| 86 | unsigned long opcode_seed; |
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| 87 | const char *operands; |
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| 88 | unsigned char im_size; /* not used by dissassembler */ |
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| 89 | const char *default_args; /* default to those args when none given */ |
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| 90 | char default_modec; /* default to this addr-mode when ambigous |
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| 91 | ie when the argument of a general addr-mode |
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| 92 | is a plain constant */ |
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| 93 | char default_model; /* is a plain label */ |
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| 94 | }; |
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| 95 | |||
| 96 | #ifdef comment |
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| 97 | /* This section was from the gdb version of this file. */ |
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| 98 | |||
| 99 | #ifndef ns32k_opcodeT |
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| 100 | #define ns32k_opcodeT int |
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| 101 | #endif /* no ns32k_opcodeT */ |
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| 102 | |||
| 103 | struct not_wot /* ns32k opcode table: wot to do with this */ |
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| 104 | /* particular opcode */ |
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| 105 | { |
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| 106 | int obits; /* number of opcode bits */ |
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| 107 | int ibits; /* number of instruction bits */ |
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| 108 | ns32k_opcodeT code; /* op-code (may be > 8 bits!) */ |
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| 109 | const char *args; /* how to compile said opcode */ |
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| 110 | }; |
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| 111 | |||
| 112 | struct not /* ns32k opcode text */ |
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| 113 | { |
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| 114 | const char *name; /* opcode name: lowercase string [key] */ |
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| 115 | struct not_wot detail; /* rest of opcode table [datum] */ |
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| 116 | }; |
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| 117 | |||
| 118 | /* Instructions look like this: |
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| 119 | |||
| 120 | basic instruction--1, 2, or 3 bytes |
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| 121 | index byte for operand A, if operand A is indexed--1 byte |
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| 122 | index byte for operand B, if operand B is indexed--1 byte |
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| 123 | addressing extension for operand A |
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| 124 | addressing extension for operand B |
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| 125 | implied operands |
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| 126 | |||
| 127 | Operand A is the operand listed first in the following opcode table. |
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| 128 | Operand B is the operand listed second in the following opcode table. |
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| 129 | All instructions have at most 2 general operands, so this is enough. |
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| 130 | The implied operands are associated with operands other than A and B. |
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| 131 | |||
| 132 | Each operand has a digit and a letter. |
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| 133 | |||
| 134 | The digit gives the position in the assembly language. The letter, |
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| 135 | one of the following, tells us what kind of operand it is. */ |
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| 136 | |||
| 137 | /* F : 32 bit float |
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| 138 | * L : 64 bit float |
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| 139 | * B : byte |
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| 140 | * W : word |
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| 141 | * D : double-word |
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| 142 | * I : integer not immediate |
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| 143 | * Z : floating not immediate |
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| 144 | * d : displacement |
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| 145 | * q : quick |
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| 146 | * i : immediate (8 bits) |
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| 147 | * r : register number (3 bits) |
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| 148 | * p : displacement - pc relative addressing |
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| 149 | */ |
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| 150 | |||
| 151 | |||
| 152 | #endif /* comment */ |
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| 153 | |||
| 154 | static const struct ns32k_opcode ns32k_opcodes[]= |
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| 155 | { |
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| 156 | { "absf", 14,24, 0x35be, "1F2Z", 4, "", DEF_MODEC,DEF_MODEL }, |
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| 157 | { "absl", 14,24, 0x34be, "1L2Z", 8, "", DEF_MODEC,DEF_MODEL }, |
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| 158 | { "absb", 14,24, 0x304e, "1B2I", 1, "", DEF_MODEC,DEF_MODEL }, |
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| 159 | { "absw", 14,24, 0x314e, "1W2I", 2, "", DEF_MODEC,DEF_MODEL }, |
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| 160 | { "absd", 14,24, 0x334e, "1D2I", 4, "", DEF_MODEC,DEF_MODEL }, |
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| 161 | { "acbb", 7,16, 0x4c, "2I1q3p", 1, "", DEF_MODEC,DEF_MODEL }, |
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| 162 | { "acbw", 7,16, 0x4d, "2I1q3p", 2, "", DEF_MODEC,DEF_MODEL }, |
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| 163 | { "acbd", 7,16, 0x4f, "2I1q3p", 4, "", DEF_MODEC,DEF_MODEL }, |
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| 164 | { "addf", 14,24, 0x01be, "1F2Z", 4, "", DEF_MODEC,DEF_MODEL }, |
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| 165 | { "addl", 14,24, 0x00be, "1L2Z", 8, "", DEF_MODEC,DEF_MODEL }, |
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| 166 | { "addb", 6,16, 0x00, "1B2I", 1, "", DEF_MODEC,DEF_MODEL }, |
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| 167 | { "addw", 6,16, 0x01, "1W2I", 2, "", DEF_MODEC,DEF_MODEL }, |
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| 168 | { "addd", 6,16, 0x03, "1D2I", 4, "", DEF_MODEC,DEF_MODEL }, |
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| 169 | { "addcb", 6,16, 0x10, "1B2I", 1, "", DEF_MODEC,DEF_MODEL }, |
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| 170 | { "addcw", 6,16, 0x11, "1W2I", 2, "", DEF_MODEC,DEF_MODEL }, |
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| 171 | { "addcd", 6,16, 0x13, "1D2I", 4, "", DEF_MODEC,DEF_MODEL }, |
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| 172 | { "addpb", 14,24, 0x3c4e, "1B2I", 1, "", DEF_MODEC,DEF_MODEL }, |
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| 173 | { "addpw", 14,24, 0x3d4e, "1W2I", 2, "", DEF_MODEC,DEF_MODEL }, |
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| 174 | { "addpd", 14,24, 0x3f4e, "1D2I", 4, "", DEF_MODEC,DEF_MODEL }, |
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| 175 | { "addqb", 7,16, 0x0c, "2I1q", 1, "", DEF_MODEC,DEF_MODEL }, |
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| 176 | { "addqw", 7,16, 0x0d, "2I1q", 2, "", DEF_MODEC,DEF_MODEL }, |
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| 177 | { "addqd", 7,16, 0x0f, "2I1q", 4, "", DEF_MODEC,DEF_MODEL }, |
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| 178 | { "addr", 6,16, 0x27, "1A2I", 4, "", 21,21 }, |
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| 179 | { "adjspb", 11,16, 0x057c, "1B", 1, "", DEF_MODEC,DEF_MODEL }, |
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| 180 | { "adjspw", 11,16, 0x057d, "1W", 2, "", DEF_MODEC,DEF_MODEL }, |
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| 181 | { "adjspd", 11,16, 0x057f, "1D", 4, "", DEF_MODEC,DEF_MODEL }, |
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| 182 | { "andb", 6,16, 0x28, "1B2I", 1, "", DEF_MODEC,DEF_MODEL }, |
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| 183 | { "andw", 6,16, 0x29, "1W2I", 2, "", DEF_MODEC,DEF_MODEL }, |
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| 184 | { "andd", 6,16, 0x2b, "1D2I", 4, "", DEF_MODEC,DEF_MODEL }, |
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| 185 | { "ashb", 14,24, 0x044e, "1B2I", 1, "", DEF_MODEC,DEF_MODEL }, |
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| 186 | { "ashw", 14,24, 0x054e, "1B2I", 1, "", DEF_MODEC,DEF_MODEL }, |
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| 187 | { "ashd", 14,24, 0x074e, "1B2I", 1, "", DEF_MODEC,DEF_MODEL }, |
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| 188 | { "beq", 8,8, 0x0a, "1p", 0, "", 21,21 }, |
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| 189 | { "bne", 8,8, 0x1a, "1p", 0, "", 21,21 }, |
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| 190 | { "bcs", 8,8, 0x2a, "1p", 0, "", 21,21 }, |
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| 191 | { "bcc", 8,8, 0x3a, "1p", 0, "", 21,21 }, |
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| 192 | { "bhi", 8,8, 0x4a, "1p", 0, "", 21,21 }, |
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| 193 | { "bls", 8,8, 0x5a, "1p", 0, "", 21,21 }, |
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| 194 | { "bgt", 8,8, 0x6a, "1p", 0, "", 21,21 }, |
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| 195 | { "ble", 8,8, 0x7a, "1p", 0, "", 21,21 }, |
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| 196 | { "bfs", 8,8, 0x8a, "1p", 0, "", 21,21 }, |
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| 197 | { "bfc", 8,8, 0x9a, "1p", 0, "", 21,21 }, |
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| 198 | { "blo", 8,8, 0xaa, "1p", 0, "", 21,21 }, |
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| 199 | { "bhs", 8,8, 0xba, "1p", 0, "", 21,21 }, |
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| 200 | { "blt", 8,8, 0xca, "1p", 0, "", 21,21 }, |
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| 201 | { "bge", 8,8, 0xda, "1p", 0, "", 21,21 }, |
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| 202 | { "but", 8,8, 0xea, "1p", 0, "", 21,21 }, |
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| 203 | { "buf", 8,8, 0xfa, "1p", 0, "", 21,21 }, |
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| 204 | { "bicb", 6,16, 0x08, "1B2I", 1, "", DEF_MODEC,DEF_MODEL }, |
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| 205 | { "bicw", 6,16, 0x09, "1W2I", 2, "", DEF_MODEC,DEF_MODEL }, |
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| 206 | { "bicd", 6,16, 0x0b, "1D2I", 4, "", DEF_MODEC,DEF_MODEL }, |
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| 207 | { "bicpsrb", 11,16, 0x17c, "1B", 1, "", DEF_MODEC,DEF_MODEL }, |
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| 208 | { "bicpsrw", 11,16, 0x17d, "1W", 2, "", DEF_MODEC,DEF_MODEL }, |
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| 209 | { "bispsrb", 11,16, 0x37c, "1B", 1, "", DEF_MODEC,DEF_MODEL }, |
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| 210 | { "bispsrw", 11,16, 0x37d, "1W", 2, "", DEF_MODEC,DEF_MODEL }, |
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| 211 | { "bpt", 8,8, 0xf2, "", 0, "", DEF_MODEC,DEF_MODEL }, |
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| 212 | { "br", 8,8, 0xea, "1p", 0, "", 21,21 }, |
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| 213 | #ifdef SEQUENT_COMPATABILITY |
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| 214 | { "bsr", 8,8, 0x02, "1H", 0, "", 21,21 }, |
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| 215 | #else |
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| 216 | { "bsr", 8,8, 0x02, "1p", 0, "", 21,21 }, |
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| 217 | #endif |
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| 218 | { "caseb", 11,16, 0x77c, "1B", 1, "", DEF_MODEC,DEF_MODEL }, |
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| 219 | { "casew", 11,16, 0x77d, "1W", 2, "", DEF_MODEC,DEF_MODEL }, |
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| 220 | { "cased", 11,16, 0x77f, "1D", 4, "", DEF_MODEC,DEF_MODEL }, |
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| 221 | { "cbitb", 14,24, 0x084e, "1B2I", 1, "", DEF_MODEC,DEF_MODEL }, |
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| 222 | { "cbitw", 14,24, 0x094e, "1W2I", 2, "", DEF_MODEC,DEF_MODEL }, |
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| 223 | { "cbitd", 14,24, 0x0b4e, "1D2I", 4, "", DEF_MODEC,DEF_MODEL }, |
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| 224 | { "cbitib", 14,24, 0x0c4e, "1B2I", 1, "", DEF_MODEC,DEF_MODEL }, |
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| 225 | { "cbitiw", 14,24, 0x0d4e, "1W2I", 2, "", DEF_MODEC,DEF_MODEL }, |
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| 226 | { "cbitid", 14,24, 0x0f4e, "1D2I", 4, "", DEF_MODEC,DEF_MODEL }, |
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| 227 | { "checkb", 11,24, 0x0ee, "2A3B1r", 1, "", DEF_MODEC,DEF_MODEL }, |
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| 228 | { "checkw", 11,24, 0x1ee, "2A3W1r", 2, "", DEF_MODEC,DEF_MODEL }, |
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| 229 | { "checkd", 11,24, 0x3ee, "2A3D1r", 4, "", DEF_MODEC,DEF_MODEL }, |
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| 230 | { "cinv", 14,24, 0x271e, "2D1C", 4, "", DEF_MODEC,DEF_MODEL }, |
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| 231 | { "cmpf", 14,24, 0x09be, "1F2F", 4, "", DEF_MODEC,DEF_MODEL }, |
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| 232 | { "cmpl", 14,24, 0x08be, "1L2L", 8, "", DEF_MODEC,DEF_MODEL }, |
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| 233 | { "cmpb", 6,16, 0x04, "1B2B", 1, "", DEF_MODEC,DEF_MODEL }, |
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| 234 | { "cmpw", 6,16, 0x05, "1W2W", 2, "", DEF_MODEC,DEF_MODEL }, |
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| 235 | { "cmpd", 6,16, 0x07, "1D2D", 4, "", DEF_MODEC,DEF_MODEL }, |
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| 236 | { "cmpmb", 14,24, 0x04ce, "1A2A3b", 1, "", DEF_MODEC,DEF_MODEL }, |
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| 237 | { "cmpmw", 14,24, 0x05ce, "1A2A3b", 2, "", DEF_MODEC,DEF_MODEL }, |
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| 238 | { "cmpmd", 14,24, 0x07ce, "1A2A3b", 4, "", DEF_MODEC,DEF_MODEL }, |
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| 239 | { "cmpqb", 7,16, 0x1c, "2B1q", 1, "", DEF_MODEC,DEF_MODEL }, |
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| 240 | { "cmpqw", 7,16, 0x1d, "2W1q", 2, "", DEF_MODEC,DEF_MODEL }, |
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| 241 | { "cmpqd", 7,16, 0x1f, "2D1q", 4, "", DEF_MODEC,DEF_MODEL }, |
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| 242 | { "cmpsb", 16,24, 0x040e, "1S", 0, "[]", DEF_MODEC,DEF_MODEL }, |
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| 243 | { "cmpsw", 16,24, 0x050e, "1S", 0, "[]", DEF_MODEC,DEF_MODEL }, |
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| 244 | { "cmpsd", 16,24, 0x070e, "1S", 0, "[]", DEF_MODEC,DEF_MODEL }, |
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| 245 | { "cmpst", 16,24, 0x840e, "1S", 0, "[]", DEF_MODEC,DEF_MODEL }, |
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| 246 | { "comb", 14,24, 0x344e, "1B2I", 1, "", DEF_MODEC,DEF_MODEL }, |
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| 247 | { "comw", 14,24, 0x354e, "1W2I", 2, "", DEF_MODEC,DEF_MODEL }, |
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| 248 | { "comd", 14,24, 0x374e, "1D2I", 4, "", DEF_MODEC,DEF_MODEL }, |
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| 249 | { "cvtp", 11,24, 0x036e, "2A3D1r", 4, "", DEF_MODEC,DEF_MODEL }, |
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| 250 | { "cxp", 8,8, 0x22, "1p", 0, "", 21,21 }, |
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| 251 | { "cxpd", 11,16, 0x07f, "1A", 4, "", DEF_MODEC,DEF_MODEL }, |
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| 252 | { "deib", 14,24, 0x2cce, "1B2I", 1, "", DEF_MODEC,DEF_MODEL }, |
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| 253 | { "deiw", 14,24, 0x2dce, "1W2I", 2, "", DEF_MODEC,DEF_MODEL }, |
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| 254 | { "deid", 14,24, 0x2fce, "1D2I", 4, "", DEF_MODEC,DEF_MODEL }, |
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| 255 | { "dia", 8,8, 0xc2, "", 1, "", DEF_MODEC,DEF_MODEL }, |
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| 256 | { "divf", 14,24, 0x21be, "1F2Z", 4, "", DEF_MODEC,DEF_MODEL }, |
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| 257 | { "divl", 14,24, 0x20be, "1L2Z", 8, "", DEF_MODEC,DEF_MODEL }, |
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| 258 | { "divb", 14,24, 0x3cce, "1B2I", 1, "", DEF_MODEC,DEF_MODEL }, |
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| 259 | { "divw", 14,24, 0x3dce, "1W2I", 2, "", DEF_MODEC,DEF_MODEL }, |
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| 260 | { "divd", 14,24, 0x3fce, "1D2I", 4, "", DEF_MODEC,DEF_MODEL }, |
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| 261 | { "enter", 8,8, 0x82, "1U2d", 0, "", DEF_MODEC,DEF_MODEL }, |
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| 262 | { "exit", 8,8, 0x92, "1u", 0, "", DEF_MODEC,DEF_MODEL }, |
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| 263 | { "extb", 11,24, 0x02e, "2I3B1r4d", 1, "", DEF_MODEC,DEF_MODEL }, |
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| 264 | { "extw", 11,24, 0x12e, "2I3W1r4d", 2, "", DEF_MODEC,DEF_MODEL }, |
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| 265 | { "extd", 11,24, 0x32e, "2I3D1r4d", 4, "", DEF_MODEC,DEF_MODEL }, |
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| 266 | { "extsb", 14,24, 0x0cce, "1I2I4G3g", 1, "", DEF_MODEC,DEF_MODEL }, |
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| 267 | { "extsw", 14,24, 0x0dce, "1I2I4G3g", 2, "", DEF_MODEC,DEF_MODEL }, |
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| 268 | { "extsd", 14,24, 0x0fce, "1I2I4G3g", 4, "", DEF_MODEC,DEF_MODEL }, |
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| 269 | { "ffsb", 14,24, 0x046e, "1B2I", 1, "", DEF_MODEC,DEF_MODEL }, |
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| 270 | { "ffsw", 14,24, 0x056e, "1W2I", 2, "", DEF_MODEC,DEF_MODEL }, |
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| 271 | { "ffsd", 14,24, 0x076e, "1D2I", 4, "", DEF_MODEC,DEF_MODEL }, |
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| 272 | { "flag", 8,8, 0xd2, "", 0, "", DEF_MODEC,DEF_MODEL }, |
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| 273 | { "floorfb", 14,24, 0x3c3e, "1F2I", 4, "", DEF_MODEC,DEF_MODEL }, |
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| 274 | { "floorfw", 14,24, 0x3d3e, "1F2I", 4, "", DEF_MODEC,DEF_MODEL }, |
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| 275 | { "floorfd", 14,24, 0x3f3e, "1F2I", 4, "", DEF_MODEC,DEF_MODEL }, |
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| 276 | { "floorlb", 14,24, 0x383e, "1L2I", 8, "", DEF_MODEC,DEF_MODEL }, |
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| 277 | { "floorlw", 14,24, 0x393e, "1L2I", 8, "", DEF_MODEC,DEF_MODEL }, |
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| 278 | { "floorld", 14,24, 0x3b3e, "1L2I", 8, "", DEF_MODEC,DEF_MODEL }, |
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| 279 | { "ibitb", 14,24, 0x384e, "1B2I", 1, "", DEF_MODEC,DEF_MODEL }, |
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| 280 | { "ibitw", 14,24, 0x394e, "1W2I", 2, "", DEF_MODEC,DEF_MODEL }, |
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| 281 | { "ibitd", 14,24, 0x3b4e, "1D2I", 4, "", DEF_MODEC,DEF_MODEL }, |
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| 282 | { "indexb", 11,24, 0x42e, "2B3B1r", 1, "", DEF_MODEC,DEF_MODEL }, |
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| 283 | { "indexw", 11,24, 0x52e, "2W3W1r", 2, "", DEF_MODEC,DEF_MODEL }, |
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| 284 | { "indexd", 11,24, 0x72e, "2D3D1r", 4, "", DEF_MODEC,DEF_MODEL }, |
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| 285 | { "insb", 11,24, 0x0ae, "2B3I1r4d", 1, "", DEF_MODEC,DEF_MODEL }, |
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| 286 | { "insw", 11,24, 0x1ae, "2W3I1r4d", 2, "", DEF_MODEC,DEF_MODEL }, |
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| 287 | { "insd", 11,24, 0x3ae, "2D3I1r4d", 4, "", DEF_MODEC,DEF_MODEL }, |
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| 288 | { "inssb", 14,24, 0x08ce, "1B2I4G3g", 1, "", DEF_MODEC,DEF_MODEL }, |
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| 289 | { "inssw", 14,24, 0x09ce, "1W2I4G3g", 2, "", DEF_MODEC,DEF_MODEL }, |
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| 290 | { "inssd", 14,24, 0x0bce, "1D2I4G3g", 4, "", DEF_MODEC,DEF_MODEL }, |
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| 291 | { "jsr", 11,16, 0x67f, "1A", 4, "", 21,21 }, |
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| 292 | { "jump", 11,16, 0x27f, "1A", 4, "", 21,21 }, |
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| 293 | { "lfsr", 19,24, 0x00f3e,"1D", 4, "", DEF_MODEC,DEF_MODEL }, |
||
| 294 | { "lmr", 15,24, 0x0b1e, "2D1M", 4, "", DEF_MODEC,DEF_MODEL }, |
||
| 295 | { "lprb", 7,16, 0x6c, "2B1P", 1, "", DEF_MODEC,DEF_MODEL }, |
||
| 296 | { "lprw", 7,16, 0x6d, "2W1P", 2, "", DEF_MODEC,DEF_MODEL }, |
||
| 297 | { "lprd", 7,16, 0x6f, "2D1P", 4, "", DEF_MODEC,DEF_MODEL }, |
||
| 298 | { "lshb", 14,24, 0x144e, "1B2I", 1, "", DEF_MODEC,DEF_MODEL }, |
||
| 299 | { "lshw", 14,24, 0x154e, "1B2I", 1, "", DEF_MODEC,DEF_MODEL }, |
||
| 300 | { "lshd", 14,24, 0x174e, "1B2I", 1, "", DEF_MODEC,DEF_MODEL }, |
||
| 301 | { "meib", 14,24, 0x24ce, "1B2I", 1, "", DEF_MODEC,DEF_MODEL }, |
||
| 302 | { "meiw", 14,24, 0x25ce, "1W2I", 2, "", DEF_MODEC,DEF_MODEL }, |
||
| 303 | { "meid", 14,24, 0x27ce, "1D2I", 4, "", DEF_MODEC,DEF_MODEL }, |
||
| 304 | { "modb", 14,24, 0x38ce, "1B2I", 1, "", DEF_MODEC,DEF_MODEL }, |
||
| 305 | { "modw", 14,24, 0x39ce, "1W2I", 2, "", DEF_MODEC,DEF_MODEL }, |
||
| 306 | { "modd", 14,24, 0x3bce, "1D2I", 4, "", DEF_MODEC,DEF_MODEL }, |
||
| 307 | { "movf", 14,24, 0x05be, "1F2Z", 4, "", DEF_MODEC,DEF_MODEL }, |
||
| 308 | { "movl", 14,24, 0x04be, "1L2Z", 8, "", DEF_MODEC,DEF_MODEL }, |
||
| 309 | { "movb", 6,16, 0x14, "1B2I", 1, "", DEF_MODEC,DEF_MODEL }, |
||
| 310 | { "movw", 6,16, 0x15, "1W2I", 2, "", DEF_MODEC,DEF_MODEL }, |
||
| 311 | { "movd", 6,16, 0x17, "1D2I", 4, "", DEF_MODEC,DEF_MODEL }, |
||
| 312 | { "movbf", 14,24, 0x043e, "1B2Z", 1, "", DEF_MODEC,DEF_MODEL }, |
||
| 313 | { "movwf", 14,24, 0x053e, "1W2Z", 2, "", DEF_MODEC,DEF_MODEL }, |
||
| 314 | { "movdf", 14,24, 0x073e, "1D2Z", 4, "", DEF_MODEC,DEF_MODEL }, |
||
| 315 | { "movbl", 14,24, 0x003e, "1B2Z", 1, "", DEF_MODEC,DEF_MODEL }, |
||
| 316 | { "movwl", 14,24, 0x013e, "1W2Z", 2, "", DEF_MODEC,DEF_MODEL }, |
||
| 317 | { "movdl", 14,24, 0x033e, "1D2Z", 4, "", DEF_MODEC,DEF_MODEL }, |
||
| 318 | { "movfl", 14,24, 0x1b3e, "1F2Z", 4, "", DEF_MODEC,DEF_MODEL }, |
||
| 319 | { "movlf", 14,24, 0x163e, "1L2Z", 8, "", DEF_MODEC,DEF_MODEL }, |
||
| 320 | { "movmb", 14,24, 0x00ce, "1A2A3b", 1, "", DEF_MODEC,DEF_MODEL }, |
||
| 321 | { "movmw", 14,24, 0x01ce, "1A2A3b", 2, "", DEF_MODEC,DEF_MODEL }, |
||
| 322 | { "movmd", 14,24, 0x03ce, "1A2A3b", 4, "", DEF_MODEC,DEF_MODEL }, |
||
| 323 | { "movqb", 7,16, 0x5c, "2I1q", 1, "", DEF_MODEC,DEF_MODEL }, |
||
| 324 | { "movqw", 7,16, 0x5d, "2I1q", 2, "", DEF_MODEC,DEF_MODEL }, |
||
| 325 | { "movqd", 7,16, 0x5f, "2I1q", 4, "", DEF_MODEC,DEF_MODEL }, |
||
| 326 | { "movsb", 16,24, 0x000e, "1S", 0, "[]", DEF_MODEC,DEF_MODEL }, |
||
| 327 | { "movsw", 16,24, 0x010e, "1S", 0, "[]", DEF_MODEC,DEF_MODEL }, |
||
| 328 | { "movsd", 16,24, 0x030e, "1S", 0, "[]", DEF_MODEC,DEF_MODEL }, |
||
| 329 | { "movst", 16,24, 0x800e, "1S", 0, "[]", DEF_MODEC,DEF_MODEL }, |
||
| 330 | { "movsub", 14,24, 0x0cae, "1A2A", 1, "", DEF_MODEC,DEF_MODEL }, |
||
| 331 | { "movsuw", 14,24, 0x0dae, "1A2A", 2, "", DEF_MODEC,DEF_MODEL }, |
||
| 332 | { "movsud", 14,24, 0x0fae, "1A2A", 4, "", DEF_MODEC,DEF_MODEL }, |
||
| 333 | { "movusb", 14,24, 0x1cae, "1A2A", 1, "", DEF_MODEC,DEF_MODEL }, |
||
| 334 | { "movusw", 14,24, 0x1dae, "1A2A", 2, "", DEF_MODEC,DEF_MODEL }, |
||
| 335 | { "movusd", 14,24, 0x1fae, "1A2A", 4, "", DEF_MODEC,DEF_MODEL }, |
||
| 336 | { "movxbd", 14,24, 0x1cce, "1B2I", 1, "", DEF_MODEC,DEF_MODEL }, |
||
| 337 | { "movxwd", 14,24, 0x1dce, "1W2I", 2, "", DEF_MODEC,DEF_MODEL }, |
||
| 338 | { "movxbw", 14,24, 0x10ce, "1B2I", 1, "", DEF_MODEC,DEF_MODEL }, |
||
| 339 | { "movzbd", 14,24, 0x18ce, "1B2I", 1, "", DEF_MODEC,DEF_MODEL }, |
||
| 340 | { "movzwd", 14,24, 0x19ce, "1W2I", 2, "", DEF_MODEC,DEF_MODEL }, |
||
| 341 | { "movzbw", 14,24, 0x14ce, "1B2I", 1, "", DEF_MODEC,DEF_MODEL }, |
||
| 342 | { "mulf", 14,24, 0x31be, "1F2Z", 4, "", DEF_MODEC,DEF_MODEL }, |
||
| 343 | { "mull", 14,24, 0x30be, "1L2Z", 8, "", DEF_MODEC,DEF_MODEL }, |
||
| 344 | { "mulb", 14,24, 0x20ce, "1B2I", 1, "", DEF_MODEC,DEF_MODEL }, |
||
| 345 | { "mulw", 14,24, 0x21ce, "1W2I", 2, "", DEF_MODEC,DEF_MODEL }, |
||
| 346 | { "muld", 14,24, 0x23ce, "1D2I", 4, "", DEF_MODEC,DEF_MODEL }, |
||
| 347 | { "negf", 14,24, 0x15be, "1F2Z", 4, "", DEF_MODEC,DEF_MODEL }, |
||
| 348 | { "negl", 14,24, 0x14be, "1L2Z", 8, "", DEF_MODEC,DEF_MODEL }, |
||
| 349 | { "negb", 14,24, 0x204e, "1B2I", 1, "", DEF_MODEC,DEF_MODEL }, |
||
| 350 | { "negw", 14,24, 0x214e, "1W2I", 2, "", DEF_MODEC,DEF_MODEL }, |
||
| 351 | { "negd", 14,24, 0x234e, "1D2I", 4, "", DEF_MODEC,DEF_MODEL }, |
||
| 352 | { "nop", 8,8, 0xa2, "", 0, "", DEF_MODEC,DEF_MODEL }, |
||
| 353 | { "notb", 14,24, 0x244e, "1B2I", 1, "", DEF_MODEC,DEF_MODEL }, |
||
| 354 | { "notw", 14,24, 0x254e, "1W2I", 2, "", DEF_MODEC,DEF_MODEL }, |
||
| 355 | { "notd", 14,24, 0x274e, "1D2I", 4, "", DEF_MODEC,DEF_MODEL }, |
||
| 356 | { "orb", 6,16, 0x18, "1B2I", 1, "", DEF_MODEC,DEF_MODEL }, |
||
| 357 | { "orw", 6,16, 0x19, "1W2I", 2, "", DEF_MODEC,DEF_MODEL }, |
||
| 358 | { "ord", 6,16, 0x1b, "1D2I", 4, "", DEF_MODEC,DEF_MODEL }, |
||
| 359 | { "quob", 14,24, 0x30ce, "1B2I", 1, "", DEF_MODEC,DEF_MODEL }, |
||
| 360 | { "quow", 14,24, 0x31ce, "1W2I", 2, "", DEF_MODEC,DEF_MODEL }, |
||
| 361 | { "quod", 14,24, 0x33ce, "1D2I", 4, "", DEF_MODEC,DEF_MODEL }, |
||
| 362 | { "rdval", 19,24, 0x0031e,"1A", 4, "", DEF_MODEC,DEF_MODEL }, |
||
| 363 | { "remb", 14,24, 0x34ce, "1B2I", 1, "", DEF_MODEC,DEF_MODEL }, |
||
| 364 | { "remw", 14,24, 0x35ce, "1W2I", 2, "", DEF_MODEC,DEF_MODEL }, |
||
| 365 | { "remd", 14,24, 0x37ce, "1D2I", 4, "", DEF_MODEC,DEF_MODEL }, |
||
| 366 | { "restore", 8,8, 0x72, "1u", 0, "", DEF_MODEC,DEF_MODEL }, |
||
| 367 | { "ret", 8,8, 0x12, "1d", 0, "", DEF_MODEC,DEF_MODEL }, |
||
| 368 | { "reti", 8,8, 0x52, "", 0, "", DEF_MODEC,DEF_MODEL }, |
||
| 369 | { "rett", 8,8, 0x42, "1d", 0, "", DEF_MODEC,DEF_MODEL }, |
||
| 370 | { "rotb", 14,24, 0x004e, "1B2I", 1, "", DEF_MODEC,DEF_MODEL }, |
||
| 371 | { "rotw", 14,24, 0x014e, "1B2I", 1, "", DEF_MODEC,DEF_MODEL }, |
||
| 372 | { "rotd", 14,24, 0x034e, "1B2I", 1, "", DEF_MODEC,DEF_MODEL }, |
||
| 373 | { "roundfb", 14,24, 0x243e, "1F2I", 4, "", DEF_MODEC,DEF_MODEL }, |
||
| 374 | { "roundfw", 14,24, 0x253e, "1F2I", 4, "", DEF_MODEC,DEF_MODEL }, |
||
| 375 | { "roundfd", 14,24, 0x273e, "1F2I", 4, "", DEF_MODEC,DEF_MODEL }, |
||
| 376 | { "roundlb", 14,24, 0x203e, "1L2I", 8, "", DEF_MODEC,DEF_MODEL }, |
||
| 377 | { "roundlw", 14,24, 0x213e, "1L2I", 8, "", DEF_MODEC,DEF_MODEL }, |
||
| 378 | { "roundld", 14,24, 0x233e, "1L2I", 8, "", DEF_MODEC,DEF_MODEL }, |
||
| 379 | { "rxp", 8,8, 0x32, "1d", 0, "", DEF_MODEC,DEF_MODEL }, |
||
| 380 | { "seqb", 11,16, 0x3c, "1B", 0, "", DEF_MODEC,DEF_MODEL }, |
||
| 381 | { "seqw", 11,16, 0x3d, "1W", 0, "", DEF_MODEC,DEF_MODEL }, |
||
| 382 | { "seqd", 11,16, 0x3f, "1D", 0, "", DEF_MODEC,DEF_MODEL }, |
||
| 383 | { "sneb", 11,16, 0xbc, "1B", 0, "", DEF_MODEC,DEF_MODEL }, |
||
| 384 | { "snew", 11,16, 0xbd, "1W", 0, "", DEF_MODEC,DEF_MODEL }, |
||
| 385 | { "sned", 11,16, 0xbf, "1D", 0, "", DEF_MODEC,DEF_MODEL }, |
||
| 386 | { "scsb", 11,16, 0x13c, "1B", 0, "", DEF_MODEC,DEF_MODEL }, |
||
| 387 | { "scsw", 11,16, 0x13d, "1W", 0, "", DEF_MODEC,DEF_MODEL }, |
||
| 388 | { "scsd", 11,16, 0x13f, "1D", 0, "", DEF_MODEC,DEF_MODEL }, |
||
| 389 | { "sccb", 11,16, 0x1bc, "1B", 0, "", DEF_MODEC,DEF_MODEL }, |
||
| 390 | { "sccw", 11,16, 0x1bd, "1W", 0, "", DEF_MODEC,DEF_MODEL }, |
||
| 391 | { "sccd", 11,16, 0x1bf, "1D", 0, "", DEF_MODEC,DEF_MODEL }, |
||
| 392 | { "shib", 11,16, 0x23c, "1B", 0, "", DEF_MODEC,DEF_MODEL }, |
||
| 393 | { "shiw", 11,16, 0x23d, "1W", 0, "", DEF_MODEC,DEF_MODEL }, |
||
| 394 | { "shid", 11,16, 0x23f, "1D", 0, "", DEF_MODEC,DEF_MODEL }, |
||
| 395 | { "slsb", 11,16, 0x2bc, "1B", 0, "", DEF_MODEC,DEF_MODEL }, |
||
| 396 | { "slsw", 11,16, 0x2bd, "1W", 0, "", DEF_MODEC,DEF_MODEL }, |
||
| 397 | { "slsd", 11,16, 0x2bf, "1D", 0, "", DEF_MODEC,DEF_MODEL }, |
||
| 398 | { "sgtb", 11,16, 0x33c, "1B", 0, "", DEF_MODEC,DEF_MODEL }, |
||
| 399 | { "sgtw", 11,16, 0x33d, "1W", 0, "", DEF_MODEC,DEF_MODEL }, |
||
| 400 | { "sgtd", 11,16, 0x33f, "1D", 0, "", DEF_MODEC,DEF_MODEL }, |
||
| 401 | { "sleb", 11,16, 0x3bc, "1B", 0, "", DEF_MODEC,DEF_MODEL }, |
||
| 402 | { "slew", 11,16, 0x3bd, "1W", 0, "", DEF_MODEC,DEF_MODEL }, |
||
| 403 | { "sled", 11,16, 0x3bf, "1D", 0, "", DEF_MODEC,DEF_MODEL }, |
||
| 404 | { "sfsb", 11,16, 0x43c, "1B", 0, "", DEF_MODEC,DEF_MODEL }, |
||
| 405 | { "sfsw", 11,16, 0x43d, "1W", 0, "", DEF_MODEC,DEF_MODEL }, |
||
| 406 | { "sfsd", 11,16, 0x43f, "1D", 0, "", DEF_MODEC,DEF_MODEL }, |
||
| 407 | { "sfcb", 11,16, 0x4bc, "1B", 0, "", DEF_MODEC,DEF_MODEL }, |
||
| 408 | { "sfcw", 11,16, 0x4bd, "1W", 0, "", DEF_MODEC,DEF_MODEL }, |
||
| 409 | { "sfcd", 11,16, 0x4bf, "1D", 0, "", DEF_MODEC,DEF_MODEL }, |
||
| 410 | { "slob", 11,16, 0x53c, "1B", 0, "", DEF_MODEC,DEF_MODEL }, |
||
| 411 | { "slow", 11,16, 0x53d, "1W", 0, "", DEF_MODEC,DEF_MODEL }, |
||
| 412 | { "slod", 11,16, 0x53f, "1D", 0, "", DEF_MODEC,DEF_MODEL }, |
||
| 413 | { "shsb", 11,16, 0x5bc, "1B", 0, "", DEF_MODEC,DEF_MODEL }, |
||
| 414 | { "shsw", 11,16, 0x5bd, "1W", 0, "", DEF_MODEC,DEF_MODEL }, |
||
| 415 | { "shsd", 11,16, 0x5bf, "1D", 0, "", DEF_MODEC,DEF_MODEL }, |
||
| 416 | { "sltb", 11,16, 0x63c, "1B", 0, "", DEF_MODEC,DEF_MODEL }, |
||
| 417 | { "sltw", 11,16, 0x63d, "1W", 0, "", DEF_MODEC,DEF_MODEL }, |
||
| 418 | { "sltd", 11,16, 0x63f, "1D", 0, "", DEF_MODEC,DEF_MODEL }, |
||
| 419 | { "sgeb", 11,16, 0x6bc, "1B", 0, "", DEF_MODEC,DEF_MODEL }, |
||
| 420 | { "sgew", 11,16, 0x6bd, "1W", 0, "", DEF_MODEC,DEF_MODEL }, |
||
| 421 | { "sged", 11,16, 0x6bf, "1D", 0, "", DEF_MODEC,DEF_MODEL }, |
||
| 422 | { "sutb", 11,16, 0x73c, "1B", 0, "", DEF_MODEC,DEF_MODEL }, |
||
| 423 | { "sutw", 11,16, 0x73d, "1W", 0, "", DEF_MODEC,DEF_MODEL }, |
||
| 424 | { "sutd", 11,16, 0x73f, "1D", 0, "", DEF_MODEC,DEF_MODEL }, |
||
| 425 | { "sufb", 11,16, 0x7bc, "1B", 0, "", DEF_MODEC,DEF_MODEL }, |
||
| 426 | { "sufw", 11,16, 0x7bd, "1W", 0, "", DEF_MODEC,DEF_MODEL }, |
||
| 427 | { "sufd", 11,16, 0x7bf, "1D", 0, "", DEF_MODEC,DEF_MODEL }, |
||
| 428 | { "save", 8,8, 0x62, "1U", 0, "", DEF_MODEC,DEF_MODEL }, |
||
| 429 | { "sbitb", 14,24, 0x184e, "1B2A", 1, "", DEF_MODEC,DEF_MODEL }, |
||
| 430 | { "sbitw", 14,24, 0x194e, "1W2A", 2, "", DEF_MODEC,DEF_MODEL }, |
||
| 431 | { "sbitd", 14,24, 0x1b4e, "1D2A", 4, "", DEF_MODEC,DEF_MODEL }, |
||
| 432 | { "sbitib", 14,24, 0x1c4e, "1B2A", 1, "", DEF_MODEC,DEF_MODEL }, |
||
| 433 | { "sbitiw", 14,24, 0x1d4e, "1W2A", 2, "", DEF_MODEC,DEF_MODEL }, |
||
| 434 | { "sbitid", 14,24, 0x1f4e, "1D2A", 4, "", DEF_MODEC,DEF_MODEL }, |
||
| 435 | { "setcfg", 15,24, 0x0b0e, "1O", 0, "", DEF_MODEC,DEF_MODEL }, |
||
| 436 | { "sfsr", 14,24, 0x373e, "1f", 0, "", DEF_MODEC,DEF_MODEL }, |
||
| 437 | { "skpsb", 16,24, 0x0c0e, "1S", 0, "[]", DEF_MODEC,DEF_MODEL }, |
||
| 438 | { "skpsw", 16,24, 0x0d0e, "1S", 0, "[]", DEF_MODEC,DEF_MODEL }, |
||
| 439 | { "skpsd", 16,24, 0x0f0e, "1S", 0, "[]", DEF_MODEC,DEF_MODEL }, |
||
| 440 | { "skpst", 16,24, 0x8c0e, "1S", 0, "[]", DEF_MODEC,DEF_MODEL }, |
||
| 441 | { "smr", 15,24, 0x0f1e, "2I1M", 4, "", DEF_MODEC,DEF_MODEL }, |
||
| 442 | { "sprb", 7,16, 0x2c, "2I1P", 1, "", DEF_MODEC,DEF_MODEL }, |
||
| 443 | { "sprw", 7,16, 0x2d, "2I1P", 2, "", DEF_MODEC,DEF_MODEL }, |
||
| 444 | { "sprd", 7,16, 0x2f, "2I1P", 4, "", DEF_MODEC,DEF_MODEL }, |
||
| 445 | { "subf", 14,24, 0x11be, "1F2Z", 4, "", DEF_MODEC,DEF_MODEL }, |
||
| 446 | { "subl", 14,24, 0x10be, "1L2Z", 8, "", DEF_MODEC,DEF_MODEL }, |
||
| 447 | { "subb", 6,16, 0x20, "1B2I", 1, "", DEF_MODEC,DEF_MODEL }, |
||
| 448 | { "subw", 6,16, 0x21, "1W2I", 2, "", DEF_MODEC,DEF_MODEL }, |
||
| 449 | { "subd", 6,16, 0x23, "1D2I", 4, "", DEF_MODEC,DEF_MODEL }, |
||
| 450 | { "subcb", 6,16, 0x30, "1B2I", 1, "", DEF_MODEC,DEF_MODEL }, |
||
| 451 | { "subcw", 6,16, 0x31, "1W2I", 2, "", DEF_MODEC,DEF_MODEL }, |
||
| 452 | { "subcd", 6,16, 0x33, "1D2I", 4, "", DEF_MODEC,DEF_MODEL }, |
||
| 453 | { "subpb", 14,24, 0x2c4e, "1B2I", 1, "", DEF_MODEC,DEF_MODEL }, |
||
| 454 | { "subpw", 14,24, 0x2d4e, "1W2I", 2, "", DEF_MODEC,DEF_MODEL }, |
||
| 455 | { "subpd", 14,24, 0x2f4e, "1D2I", 4, "", DEF_MODEC,DEF_MODEL }, |
||
| 456 | #ifdef NS32K_SVC_IMMED_OPERANDS |
||
| 457 | { "svc", 8,8, 0xe2, "2i1i", 1, "", DEF_MODEC,DEF_MODEL }, /* not really, but some unix uses it */ |
||
| 458 | #else |
||
| 459 | { "svc", 8,8, 0xe2, "", 0, "", DEF_MODEC,DEF_MODEL }, |
||
| 460 | #endif |
||
| 461 | { "tbitb", 6,16, 0x34, "1B2A", 1, "", DEF_MODEC,DEF_MODEL }, |
||
| 462 | { "tbitw", 6,16, 0x35, "1W2A", 2, "", DEF_MODEC,DEF_MODEL }, |
||
| 463 | { "tbitd", 6,16, 0x37, "1D2A", 4, "", DEF_MODEC,DEF_MODEL }, |
||
| 464 | { "truncfb", 14,24, 0x2c3e, "1F2I", 4, "", DEF_MODEC,DEF_MODEL }, |
||
| 465 | { "truncfw", 14,24, 0x2d3e, "1F2I", 4, "", DEF_MODEC,DEF_MODEL }, |
||
| 466 | { "truncfd", 14,24, 0x2f3e, "1F2I", 4, "", DEF_MODEC,DEF_MODEL }, |
||
| 467 | { "trunclb", 14,24, 0x283e, "1L2I", 8, "", DEF_MODEC,DEF_MODEL }, |
||
| 468 | { "trunclw", 14,24, 0x293e, "1L2I", 8, "", DEF_MODEC,DEF_MODEL }, |
||
| 469 | { "truncld", 14,24, 0x2b3e, "1L2I", 8, "", DEF_MODEC,DEF_MODEL }, |
||
| 470 | { "wait", 8,8, 0xb2, "", 0, "", DEF_MODEC,DEF_MODEL }, |
||
| 471 | { "wrval", 19,24, 0x0071e,"1A", 0, "", DEF_MODEC,DEF_MODEL }, |
||
| 472 | { "xorb", 6,16, 0x38, "1B2I", 1, "", DEF_MODEC,DEF_MODEL }, |
||
| 473 | { "xorw", 6,16, 0x39, "1W2I", 2, "", DEF_MODEC,DEF_MODEL }, |
||
| 474 | { "xord", 6,16, 0x3b, "1D2I", 4, "", DEF_MODEC,DEF_MODEL }, |
||
| 475 | { "dotf", 14,24, 0x0dfe, "1F2F", 4, "", DEF_MODEC,DEF_MODEL }, |
||
| 476 | { "dotl", 14,24, 0x0cfe, "1L2L", 8, "", DEF_MODEC,DEF_MODEL }, |
||
| 477 | { "logbf", 14,24, 0x15fe, "1F2Z", 4, "", DEF_MODEC,DEF_MODEL }, |
||
| 478 | { "logbl", 14,24, 0x14fe, "1L2Z", 8, "", DEF_MODEC,DEF_MODEL }, |
||
| 479 | { "polyf", 14,24, 0x09fe, "1F2F", 4, "", DEF_MODEC,DEF_MODEL }, |
||
| 480 | { "polyl", 14,24, 0x08fe, "1L2L", 8, "", DEF_MODEC,DEF_MODEL }, |
||
| 481 | { "scalbf", 14,24, 0x11fe, "1F2Z", 4, "", DEF_MODEC,DEF_MODEL }, |
||
| 482 | { "scalbl", 14,24, 0x10fe, "1L2Z", 8, "", DEF_MODEC,DEF_MODEL }, |
||
| 483 | }; |
||
| 484 | |||
| 485 | #define MAX_ARGS 4 |
||
| 486 | #define ARG_LEN 50 |
||
| 487 |