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5191 | serge | 1 | /* Nios II opcode list for GAS, the GNU assembler. |
6324 | serge | 2 | Copyright (C) 2012-2015 Free Software Foundation, Inc. |
5191 | serge | 3 | Contributed by Nigel Gray (ngray@altera.com). |
4 | Contributed by Mentor Graphics, Inc. |
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5 | |||
6 | This file is part of GAS, the GNU Assembler, and GDB, the GNU disassembler. |
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7 | |||
8 | GAS/GDB is free software; you can redistribute it and/or modify |
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9 | it under the terms of the GNU General Public License as published by |
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10 | the Free Software Foundation; either version 3, or (at your option) |
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11 | any later version. |
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12 | |||
13 | GAS/GDB is distributed in the hope that it will be useful, |
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14 | but WITHOUT ANY WARRANTY; without even the implied warranty of |
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15 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
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16 | GNU General Public License for more details. |
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17 | |||
18 | You should have received a copy of the GNU General Public License |
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19 | along with GAS or GDB; see the file COPYING3. If not, write to |
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20 | the Free Software Foundation, 51 Franklin Street - Fifth Floor, |
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21 | Boston, MA 02110-1301, USA. */ |
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22 | |||
23 | #ifndef _NIOS2_H_ |
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24 | #define _NIOS2_H_ |
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25 | |||
26 | #include "bfd.h" |
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27 | |||
6324 | serge | 28 | #ifdef __cplusplus |
29 | extern "C" { |
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30 | #endif |
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31 | |||
5191 | serge | 32 | /**************************************************************************** |
33 | * This file contains structures, bit masks and shift counts used |
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34 | * by the GNU toolchain to define the Nios II instruction set and |
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35 | * access various opcode fields. |
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36 | ****************************************************************************/ |
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37 | |||
6324 | serge | 38 | /* Instruction encoding formats. */ |
39 | enum iw_format_type { |
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40 | /* R1 formats. */ |
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41 | iw_i_type, |
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42 | iw_r_type, |
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43 | iw_j_type, |
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44 | iw_custom_type, |
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45 | |||
46 | /* 32-bit R2 formats. */ |
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47 | iw_L26_type, |
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48 | iw_F2I16_type, |
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49 | iw_F2X4I12_type, |
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50 | iw_F1X4I12_type, |
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51 | iw_F1X4L17_type, |
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52 | iw_F3X6L5_type, |
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53 | iw_F2X6L10_type, |
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54 | iw_F3X6_type, |
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55 | iw_F3X8_type, |
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56 | |||
57 | /* 16-bit R2 formats. */ |
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58 | iw_I10_type, |
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59 | iw_T1I7_type, |
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60 | iw_T2I4_type, |
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61 | iw_T1X1I6_type, |
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62 | iw_X1I7_type, |
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63 | iw_L5I4X1_type, |
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64 | iw_T2X1L3_type, |
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65 | iw_T2X1I3_type, |
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66 | iw_T3X1_type, |
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67 | iw_T2X3_type, |
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68 | iw_F1X1_type, |
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69 | iw_X2L5_type, |
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70 | iw_F1I5_type, |
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71 | iw_F2_type |
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72 | }; |
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73 | |||
5191 | serge | 74 | /* Identify different overflow situations for error messages. */ |
75 | enum overflow_type |
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76 | { |
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77 | call_target_overflow = 0, |
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78 | branch_target_overflow, |
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79 | address_offset_overflow, |
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80 | signed_immed16_overflow, |
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81 | unsigned_immed16_overflow, |
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82 | unsigned_immed5_overflow, |
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6324 | serge | 83 | signed_immed12_overflow, |
5191 | serge | 84 | custom_opcode_overflow, |
6324 | serge | 85 | enumeration_overflow, |
5191 | serge | 86 | no_overflow |
87 | }; |
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88 | |||
89 | /* This structure holds information for a particular instruction. |
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90 | |||
91 | The args field is a string describing the operands. The following |
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92 | letters can appear in the args: |
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93 | c - a 5-bit control register index |
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94 | d - a 5-bit destination register index |
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95 | s - a 5-bit left source register index |
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96 | t - a 5-bit right source register index |
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6324 | serge | 97 | D - a 3-bit encoded destination register |
98 | S - a 3-bit encoded left source register |
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99 | T - a 3-bit encoded right source register |
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5191 | serge | 100 | i - a 16-bit signed immediate |
101 | j - a 5-bit unsigned immediate |
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6324 | serge | 102 | k - a (second) 5-bit unsigned immediate |
5191 | serge | 103 | l - a 8-bit custom instruction constant |
104 | m - a 26-bit unsigned immediate |
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6324 | serge | 105 | o - a 16-bit signed pc-relative offset |
106 | u - a 16-bit unsigned immediate |
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107 | I - a 12-bit signed immediate |
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108 | M - a 6-bit unsigned immediate |
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109 | N - a 6-bit unsigned immediate with 2-bit shift |
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110 | O - a 10-bit signed pc-relative offset with 1-bit shift |
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111 | P - a 7-bit signed pc-relative offset with 1-bit shift |
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112 | U - a 7-bit unsigned immediate with 2-bit shift |
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113 | V - a 5-bit unsigned immediate with 2-bit shift |
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114 | W - a 4-bit unsigned immediate with 2-bit shift |
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115 | X - a 4-bit unsigned immediate with 1-bit shift |
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116 | Y - a 4-bit unsigned immediate |
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117 | e - an immediate coded as an enumeration for addi.n/subi.n |
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118 | f - an immediate coded as an enumeration for slli.n/srli.n |
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119 | g - an immediate coded as an enumeration for andi.n |
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120 | h - an immediate coded as an enumeration for movi.n |
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121 | R - a reglist for ldwm/stwm or push.n/pop.n |
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122 | B - a base register specifier and option list for ldwm/stwm |
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5191 | serge | 123 | Literal ',', '(', and ')' characters may also appear in the args as |
124 | delimiters. |
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125 | |||
6324 | serge | 126 | Note that the args describe the semantics and assembly-language syntax |
127 | of the operands, not their encoding into the instruction word. |
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128 | |||
5191 | serge | 129 | The pinfo field is INSN_MACRO for a macro. Otherwise, it is a collection |
130 | of bits describing the instruction, notably any relevant hazard |
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131 | information. |
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132 | |||
133 | When assembling, the match field contains the opcode template, which |
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134 | is modified by the arguments to produce the actual opcode |
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135 | that is emitted. If pinfo is INSN_MACRO, then this is 0. |
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136 | |||
137 | If pinfo is INSN_MACRO, the mask field stores the macro identifier. |
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138 | Otherwise this is a bit mask for the relevant portions of the opcode |
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139 | when disassembling. If the actual opcode anded with the match field |
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140 | equals the opcode field, then we have found the correct instruction. */ |
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141 | |||
142 | struct nios2_opcode |
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143 | { |
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144 | const char *name; /* The name of the instruction. */ |
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145 | const char *args; /* A string describing the arguments for this |
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146 | instruction. */ |
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147 | const char *args_test; /* Like args, but with an extra argument for |
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148 | the expected opcode. */ |
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149 | unsigned long num_args; /* The number of arguments the instruction |
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150 | takes. */ |
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6324 | serge | 151 | unsigned size; /* Size in bytes of the instruction. */ |
152 | enum iw_format_type format; /* Instruction format. */ |
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5191 | serge | 153 | unsigned long match; /* The basic opcode for the instruction. */ |
154 | unsigned long mask; /* Mask for the opcode field of the |
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155 | instruction. */ |
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156 | unsigned long pinfo; /* Is this a real instruction or instruction |
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157 | macro? */ |
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158 | enum overflow_type overflow_msg; /* Used to generate informative |
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159 | message when fixup overflows. */ |
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160 | }; |
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161 | |||
162 | /* This value is used in the nios2_opcode.pinfo field to indicate that the |
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163 | instruction is a macro or pseudo-op. This requires special treatment by |
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164 | the assembler, and is used by the disassembler to determine whether to |
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165 | check for a nop. */ |
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166 | #define NIOS2_INSN_MACRO 0x80000000 |
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167 | #define NIOS2_INSN_MACRO_MOV 0x80000001 |
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168 | #define NIOS2_INSN_MACRO_MOVI 0x80000002 |
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169 | #define NIOS2_INSN_MACRO_MOVIA 0x80000004 |
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170 | |||
171 | #define NIOS2_INSN_RELAXABLE 0x40000000 |
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172 | #define NIOS2_INSN_UBRANCH 0x00000010 |
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173 | #define NIOS2_INSN_CBRANCH 0x00000020 |
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174 | #define NIOS2_INSN_CALL 0x00000040 |
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175 | |||
6324 | serge | 176 | #define NIOS2_INSN_OPTARG 0x00000080 |
5191 | serge | 177 | |
6324 | serge | 178 | /* Register attributes. */ |
179 | #define REG_NORMAL (1<<0) /* Normal registers. */ |
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180 | #define REG_CONTROL (1<<1) /* Control registers. */ |
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181 | #define REG_COPROCESSOR (1<<2) /* For custom instructions. */ |
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182 | #define REG_3BIT (1<<3) /* For R2 CDX instructions. */ |
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183 | #define REG_LDWM (1<<4) /* For R2 ldwm/stwm. */ |
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184 | #define REG_POP (1<<5) /* For R2 pop.n/push.n. */ |
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5191 | serge | 185 | |
186 | struct nios2_reg |
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187 | { |
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188 | const char *name; |
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189 | const int index; |
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6324 | serge | 190 | unsigned long regtype; |
5191 | serge | 191 | }; |
192 | |||
6324 | serge | 193 | /* Pull in the instruction field accessors, opcodes, and masks. */ |
194 | #include "nios2r1.h" |
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195 | #include "nios2r2.h" |
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5191 | serge | 196 | |
6324 | serge | 197 | /* These are the data structures used to hold the instruction information. */ |
198 | extern const struct nios2_opcode nios2_r1_opcodes[]; |
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199 | extern const int nios2_num_r1_opcodes; |
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200 | extern const struct nios2_opcode nios2_r2_opcodes[]; |
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201 | extern const int nios2_num_r2_opcodes; |
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5191 | serge | 202 | extern struct nios2_opcode *nios2_opcodes; |
6324 | serge | 203 | extern int nios2_num_opcodes; |
5191 | serge | 204 | |
205 | /* These are the data structures used to hold the register information. */ |
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206 | extern const struct nios2_reg nios2_builtin_regs[]; |
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207 | extern struct nios2_reg *nios2_regs; |
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208 | extern const int nios2_num_builtin_regs; |
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209 | extern int nios2_num_regs; |
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210 | |||
6324 | serge | 211 | /* Return the opcode descriptor for a single instruction. */ |
212 | extern const struct nios2_opcode * |
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213 | nios2_find_opcode_hash (unsigned long, unsigned long); |
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5191 | serge | 214 | |
6324 | serge | 215 | /* Lookup tables for R2 immediate decodings. */ |
216 | extern unsigned int nios2_r2_asi_n_mappings[]; |
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217 | extern const int nios2_num_r2_asi_n_mappings; |
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218 | extern unsigned int nios2_r2_shi_n_mappings[]; |
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219 | extern const int nios2_num_r2_shi_n_mappings; |
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220 | extern unsigned int nios2_r2_andi_n_mappings[]; |
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221 | extern const int nios2_num_r2_andi_n_mappings; |
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5191 | serge | 222 | |
6324 | serge | 223 | /* Lookup table for 3-bit register decodings. */ |
224 | extern int nios2_r2_reg3_mappings[]; |
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225 | extern const int nios2_num_r2_reg3_mappings; |
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226 | |||
227 | /* Lookup table for REG_RANGE value list decodings. */ |
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228 | extern unsigned long nios2_r2_reg_range_mappings[]; |
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229 | extern const int nios2_num_r2_reg_range_mappings; |
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230 | |||
231 | #ifdef __cplusplus |
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232 | } |
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233 | #endif |
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234 | |||
5191 | serge | 235 | #endif /* _NIOS2_H */5)><5)>4)><4)>3)><3)>2)><2)>1)><1)>0)><0)> |