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5191 | serge | 1 | /* mips.h. Mips opcode list for GDB, the GNU debugger. |
2 | Copyright 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001, 2002, |
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3 | 2003, 2004, 2005, 2008, 2009, 2010, 2013 |
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4 | Free Software Foundation, Inc. |
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5 | Contributed by Ralph Campbell and OSF |
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6 | Commented and modified by Ian Lance Taylor, Cygnus Support |
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7 | |||
8 | This file is part of GDB, GAS, and the GNU binutils. |
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9 | |||
10 | GDB, GAS, and the GNU binutils are free software; you can redistribute |
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11 | them and/or modify them under the terms of the GNU General Public |
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12 | License as published by the Free Software Foundation; either version 3, |
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13 | or (at your option) any later version. |
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14 | |||
15 | GDB, GAS, and the GNU binutils are distributed in the hope that they |
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16 | will be useful, but WITHOUT ANY WARRANTY; without even the implied |
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17 | warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See |
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18 | the GNU General Public License for more details. |
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19 | |||
20 | You should have received a copy of the GNU General Public License |
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21 | along with this file; see the file COPYING3. If not, write to the Free |
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22 | Software Foundation, 51 Franklin Street - Fifth Floor, Boston, |
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23 | MA 02110-1301, USA. */ |
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24 | |||
25 | #ifndef _MIPS_H_ |
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26 | #define _MIPS_H_ |
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27 | |||
28 | #include "bfd.h" |
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29 | |||
30 | /* These are bit masks and shift counts to use to access the various |
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31 | fields of an instruction. To retrieve the X field of an |
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32 | instruction, use the expression |
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33 | (i >> OP_SH_X) & OP_MASK_X |
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34 | To set the same field (to j), use |
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35 | i = (i &~ (OP_MASK_X << OP_SH_X)) | (j << OP_SH_X) |
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36 | |||
37 | Make sure you use fields that are appropriate for the instruction, |
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38 | of course. |
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39 | |||
40 | The 'i' format uses OP, RS, RT and IMMEDIATE. |
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41 | |||
42 | The 'j' format uses OP and TARGET. |
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43 | |||
44 | The 'r' format uses OP, RS, RT, RD, SHAMT and FUNCT. |
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45 | |||
46 | The 'b' format uses OP, RS, RT and DELTA. |
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47 | |||
48 | The floating point 'i' format uses OP, RS, RT and IMMEDIATE. |
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49 | |||
50 | The floating point 'r' format uses OP, FMT, FT, FS, FD and FUNCT. |
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51 | |||
52 | A breakpoint instruction uses OP, CODE and SPEC (10 bits of the |
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53 | breakpoint instruction are not defined; Kane says the breakpoint |
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54 | code field in BREAK is 20 bits; yet MIPS assemblers and debuggers |
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55 | only use ten bits). An optional two-operand form of break/sdbbp |
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56 | allows the lower ten bits to be set too, and MIPS32 and later |
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57 | architectures allow 20 bits to be set with a signal operand |
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58 | (using CODE20). |
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59 | |||
60 | The syscall instruction uses CODE20. |
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61 | |||
62 | The general coprocessor instructions use COPZ. */ |
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63 | |||
64 | #define OP_MASK_OP 0x3f |
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65 | #define OP_SH_OP 26 |
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66 | #define OP_MASK_RS 0x1f |
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67 | #define OP_SH_RS 21 |
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68 | #define OP_MASK_FR 0x1f |
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69 | #define OP_SH_FR 21 |
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70 | #define OP_MASK_FMT 0x1f |
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71 | #define OP_SH_FMT 21 |
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72 | #define OP_MASK_BCC 0x7 |
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73 | #define OP_SH_BCC 18 |
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74 | #define OP_MASK_CODE 0x3ff |
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75 | #define OP_SH_CODE 16 |
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76 | #define OP_MASK_CODE2 0x3ff |
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77 | #define OP_SH_CODE2 6 |
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78 | #define OP_MASK_RT 0x1f |
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79 | #define OP_SH_RT 16 |
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80 | #define OP_MASK_FT 0x1f |
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81 | #define OP_SH_FT 16 |
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82 | #define OP_MASK_CACHE 0x1f |
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83 | #define OP_SH_CACHE 16 |
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84 | #define OP_MASK_RD 0x1f |
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85 | #define OP_SH_RD 11 |
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86 | #define OP_MASK_FS 0x1f |
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87 | #define OP_SH_FS 11 |
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88 | #define OP_MASK_PREFX 0x1f |
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89 | #define OP_SH_PREFX 11 |
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90 | #define OP_MASK_CCC 0x7 |
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91 | #define OP_SH_CCC 8 |
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92 | #define OP_MASK_CODE20 0xfffff /* 20 bit syscall/breakpoint code. */ |
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93 | #define OP_SH_CODE20 6 |
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94 | #define OP_MASK_SHAMT 0x1f |
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95 | #define OP_SH_SHAMT 6 |
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96 | #define OP_MASK_EXTLSB OP_MASK_SHAMT |
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97 | #define OP_SH_EXTLSB OP_SH_SHAMT |
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98 | #define OP_MASK_STYPE OP_MASK_SHAMT |
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99 | #define OP_SH_STYPE OP_SH_SHAMT |
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100 | #define OP_MASK_FD 0x1f |
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101 | #define OP_SH_FD 6 |
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102 | #define OP_MASK_TARGET 0x3ffffff |
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103 | #define OP_SH_TARGET 0 |
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104 | #define OP_MASK_COPZ 0x1ffffff |
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105 | #define OP_SH_COPZ 0 |
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106 | #define OP_MASK_IMMEDIATE 0xffff |
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107 | #define OP_SH_IMMEDIATE 0 |
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108 | #define OP_MASK_DELTA 0xffff |
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109 | #define OP_SH_DELTA 0 |
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110 | #define OP_MASK_FUNCT 0x3f |
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111 | #define OP_SH_FUNCT 0 |
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112 | #define OP_MASK_SPEC 0x3f |
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113 | #define OP_SH_SPEC 0 |
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114 | #define OP_SH_LOCC 8 /* FP condition code. */ |
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115 | #define OP_SH_HICC 18 /* FP condition code. */ |
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116 | #define OP_MASK_CC 0x7 |
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117 | #define OP_SH_COP1NORM 25 /* Normal COP1 encoding. */ |
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118 | #define OP_MASK_COP1NORM 0x1 /* a single bit. */ |
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119 | #define OP_SH_COP1SPEC 21 /* COP1 encodings. */ |
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120 | #define OP_MASK_COP1SPEC 0xf |
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121 | #define OP_MASK_COP1SCLR 0x4 |
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122 | #define OP_MASK_COP1CMP 0x3 |
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123 | #define OP_SH_COP1CMP 4 |
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124 | #define OP_SH_FORMAT 21 /* FP short format field. */ |
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125 | #define OP_MASK_FORMAT 0x7 |
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126 | #define OP_SH_TRUE 16 |
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127 | #define OP_MASK_TRUE 0x1 |
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128 | #define OP_SH_GE 17 |
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129 | #define OP_MASK_GE 0x01 |
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130 | #define OP_SH_UNSIGNED 16 |
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131 | #define OP_MASK_UNSIGNED 0x1 |
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132 | #define OP_SH_HINT 16 |
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133 | #define OP_MASK_HINT 0x1f |
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134 | #define OP_SH_MMI 0 /* Multimedia (parallel) op. */ |
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135 | #define OP_MASK_MMI 0x3f |
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136 | #define OP_SH_MMISUB 6 |
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137 | #define OP_MASK_MMISUB 0x1f |
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138 | #define OP_MASK_PERFREG 0x1f /* Performance monitoring. */ |
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139 | #define OP_SH_PERFREG 1 |
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140 | #define OP_SH_SEL 0 /* Coprocessor select field. */ |
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141 | #define OP_MASK_SEL 0x7 /* The sel field of mfcZ and mtcZ. */ |
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142 | #define OP_SH_CODE19 6 /* 19 bit wait code. */ |
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143 | #define OP_MASK_CODE19 0x7ffff |
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144 | #define OP_SH_ALN 21 |
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145 | #define OP_MASK_ALN 0x7 |
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146 | #define OP_SH_VSEL 21 |
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147 | #define OP_MASK_VSEL 0x1f |
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148 | #define OP_MASK_VECBYTE 0x7 /* Selector field is really 4 bits, |
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149 | but 0x8-0xf don't select bytes. */ |
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150 | #define OP_SH_VECBYTE 22 |
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151 | #define OP_MASK_VECALIGN 0x7 /* Vector byte-align (alni.ob) op. */ |
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152 | #define OP_SH_VECALIGN 21 |
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153 | #define OP_MASK_INSMSB 0x1f /* "ins" MSB. */ |
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154 | #define OP_SH_INSMSB 11 |
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155 | #define OP_MASK_EXTMSBD 0x1f /* "ext" MSBD. */ |
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156 | #define OP_SH_EXTMSBD 11 |
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157 | |||
158 | /* MIPS DSP ASE */ |
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159 | #define OP_SH_DSPACC 11 |
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160 | #define OP_MASK_DSPACC 0x3 |
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161 | #define OP_SH_DSPACC_S 21 |
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162 | #define OP_MASK_DSPACC_S 0x3 |
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163 | #define OP_SH_DSPSFT 20 |
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164 | #define OP_MASK_DSPSFT 0x3f |
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165 | #define OP_SH_DSPSFT_7 19 |
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166 | #define OP_MASK_DSPSFT_7 0x7f |
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167 | #define OP_SH_SA3 21 |
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168 | #define OP_MASK_SA3 0x7 |
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169 | #define OP_SH_SA4 21 |
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170 | #define OP_MASK_SA4 0xf |
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171 | #define OP_SH_IMM8 16 |
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172 | #define OP_MASK_IMM8 0xff |
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173 | #define OP_SH_IMM10 16 |
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174 | #define OP_MASK_IMM10 0x3ff |
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175 | #define OP_SH_WRDSP 11 |
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176 | #define OP_MASK_WRDSP 0x3f |
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177 | #define OP_SH_RDDSP 16 |
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178 | #define OP_MASK_RDDSP 0x3f |
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179 | #define OP_SH_BP 11 |
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180 | #define OP_MASK_BP 0x3 |
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181 | |||
182 | /* MIPS MT ASE */ |
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183 | #define OP_SH_MT_U 5 |
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184 | #define OP_MASK_MT_U 0x1 |
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185 | #define OP_SH_MT_H 4 |
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186 | #define OP_MASK_MT_H 0x1 |
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187 | #define OP_SH_MTACC_T 18 |
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188 | #define OP_MASK_MTACC_T 0x3 |
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189 | #define OP_SH_MTACC_D 13 |
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190 | #define OP_MASK_MTACC_D 0x3 |
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191 | |||
192 | /* MIPS MCU ASE */ |
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193 | #define OP_MASK_3BITPOS 0x7 |
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194 | #define OP_SH_3BITPOS 12 |
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195 | #define OP_MASK_OFFSET12 0xfff |
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196 | #define OP_SH_OFFSET12 0 |
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197 | |||
198 | #define OP_OP_COP0 0x10 |
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199 | #define OP_OP_COP1 0x11 |
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200 | #define OP_OP_COP2 0x12 |
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201 | #define OP_OP_COP3 0x13 |
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202 | #define OP_OP_LWC1 0x31 |
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203 | #define OP_OP_LWC2 0x32 |
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204 | #define OP_OP_LWC3 0x33 /* a.k.a. pref */ |
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205 | #define OP_OP_LDC1 0x35 |
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206 | #define OP_OP_LDC2 0x36 |
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207 | #define OP_OP_LDC3 0x37 /* a.k.a. ld */ |
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208 | #define OP_OP_SWC1 0x39 |
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209 | #define OP_OP_SWC2 0x3a |
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210 | #define OP_OP_SWC3 0x3b |
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211 | #define OP_OP_SDC1 0x3d |
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212 | #define OP_OP_SDC2 0x3e |
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213 | #define OP_OP_SDC3 0x3f /* a.k.a. sd */ |
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214 | |||
215 | /* MIPS VIRT ASE */ |
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216 | #define OP_MASK_CODE10 0x3ff |
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217 | #define OP_SH_CODE10 11 |
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218 | |||
219 | /* Values in the 'VSEL' field. */ |
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220 | #define MDMX_FMTSEL_IMM_QH 0x1d |
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221 | #define MDMX_FMTSEL_IMM_OB 0x1e |
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222 | #define MDMX_FMTSEL_VEC_QH 0x15 |
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223 | #define MDMX_FMTSEL_VEC_OB 0x16 |
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224 | |||
225 | /* UDI */ |
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226 | #define OP_SH_UDI1 6 |
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227 | #define OP_MASK_UDI1 0x1f |
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228 | #define OP_SH_UDI2 6 |
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229 | #define OP_MASK_UDI2 0x3ff |
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230 | #define OP_SH_UDI3 6 |
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231 | #define OP_MASK_UDI3 0x7fff |
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232 | #define OP_SH_UDI4 6 |
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233 | #define OP_MASK_UDI4 0xfffff |
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234 | |||
235 | /* Octeon */ |
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236 | #define OP_SH_BBITIND 16 |
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237 | #define OP_MASK_BBITIND 0x1f |
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238 | #define OP_SH_CINSPOS 6 |
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239 | #define OP_MASK_CINSPOS 0x1f |
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240 | #define OP_SH_CINSLM1 11 |
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241 | #define OP_MASK_CINSLM1 0x1f |
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242 | #define OP_SH_SEQI 6 |
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243 | #define OP_MASK_SEQI 0x3ff |
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244 | |||
245 | /* Loongson */ |
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246 | #define OP_SH_OFFSET_A 6 |
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247 | #define OP_MASK_OFFSET_A 0xff |
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248 | #define OP_SH_OFFSET_B 3 |
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249 | #define OP_MASK_OFFSET_B 0xff |
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250 | #define OP_SH_OFFSET_C 6 |
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251 | #define OP_MASK_OFFSET_C 0x1ff |
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252 | #define OP_SH_RZ 0 |
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253 | #define OP_MASK_RZ 0x1f |
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254 | #define OP_SH_FZ 0 |
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255 | #define OP_MASK_FZ 0x1f |
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256 | |||
257 | /* Every MICROMIPSOP_X definition requires a corresponding OP_X |
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258 | definition, and vice versa. This simplifies various parts |
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259 | of the operand handling in GAS. The fields below only exist |
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260 | in the microMIPS encoding, so define each one to have an empty |
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261 | range. */ |
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262 | #define OP_MASK_TRAP 0 |
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263 | #define OP_SH_TRAP 0 |
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264 | #define OP_MASK_OFFSET10 0 |
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265 | #define OP_SH_OFFSET10 0 |
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266 | #define OP_MASK_RS3 0 |
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267 | #define OP_SH_RS3 0 |
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268 | #define OP_MASK_MB 0 |
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269 | #define OP_SH_MB 0 |
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270 | #define OP_MASK_MC 0 |
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271 | #define OP_SH_MC 0 |
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272 | #define OP_MASK_MD 0 |
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273 | #define OP_SH_MD 0 |
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274 | #define OP_MASK_ME 0 |
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275 | #define OP_SH_ME 0 |
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276 | #define OP_MASK_MF 0 |
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277 | #define OP_SH_MF 0 |
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278 | #define OP_MASK_MG 0 |
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279 | #define OP_SH_MG 0 |
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280 | #define OP_MASK_MH 0 |
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281 | #define OP_SH_MH 0 |
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282 | #define OP_MASK_MJ 0 |
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283 | #define OP_SH_MJ 0 |
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284 | #define OP_MASK_ML 0 |
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285 | #define OP_SH_ML 0 |
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286 | #define OP_MASK_MM 0 |
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287 | #define OP_SH_MM 0 |
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288 | #define OP_MASK_MN 0 |
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289 | #define OP_SH_MN 0 |
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290 | #define OP_MASK_MP 0 |
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291 | #define OP_SH_MP 0 |
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292 | #define OP_MASK_MQ 0 |
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293 | #define OP_SH_MQ 0 |
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294 | #define OP_MASK_IMMA 0 |
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295 | #define OP_SH_IMMA 0 |
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296 | #define OP_MASK_IMMB 0 |
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297 | #define OP_SH_IMMB 0 |
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298 | #define OP_MASK_IMMC 0 |
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299 | #define OP_SH_IMMC 0 |
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300 | #define OP_MASK_IMMF 0 |
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301 | #define OP_SH_IMMF 0 |
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302 | #define OP_MASK_IMMG 0 |
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303 | #define OP_SH_IMMG 0 |
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304 | #define OP_MASK_IMMH 0 |
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305 | #define OP_SH_IMMH 0 |
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306 | #define OP_MASK_IMMI 0 |
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307 | #define OP_SH_IMMI 0 |
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308 | #define OP_MASK_IMMJ 0 |
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309 | #define OP_SH_IMMJ 0 |
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310 | #define OP_MASK_IMML 0 |
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311 | #define OP_SH_IMML 0 |
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312 | #define OP_MASK_IMMM 0 |
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313 | #define OP_SH_IMMM 0 |
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314 | #define OP_MASK_IMMN 0 |
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315 | #define OP_SH_IMMN 0 |
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316 | #define OP_MASK_IMMO 0 |
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317 | #define OP_SH_IMMO 0 |
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318 | #define OP_MASK_IMMP 0 |
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319 | #define OP_SH_IMMP 0 |
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320 | #define OP_MASK_IMMQ 0 |
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321 | #define OP_SH_IMMQ 0 |
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322 | #define OP_MASK_IMMU 0 |
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323 | #define OP_SH_IMMU 0 |
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324 | #define OP_MASK_IMMW 0 |
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325 | #define OP_SH_IMMW 0 |
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326 | #define OP_MASK_IMMX 0 |
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327 | #define OP_SH_IMMX 0 |
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328 | #define OP_MASK_IMMY 0 |
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329 | #define OP_SH_IMMY 0 |
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330 | |||
331 | /* Enhanced VA Scheme */ |
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332 | #define OP_SH_EVAOFFSET 7 |
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333 | #define OP_MASK_EVAOFFSET 0x1ff |
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334 | |||
335 | /* Enumerates the various types of MIPS operand. */ |
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336 | enum mips_operand_type { |
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337 | /* Described by mips_int_operand. */ |
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338 | OP_INT, |
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339 | |||
340 | /* Described by mips_mapped_int_operand. */ |
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341 | OP_MAPPED_INT, |
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342 | |||
343 | /* Described by mips_msb_operand. */ |
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344 | OP_MSB, |
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345 | |||
346 | /* Described by mips_reg_operand. */ |
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347 | OP_REG, |
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348 | |||
349 | /* Like OP_REG, but can be omitted if the register is the same as the |
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350 | previous operand. */ |
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351 | OP_OPTIONAL_REG, |
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352 | |||
353 | /* Described by mips_reg_pair_operand. */ |
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354 | OP_REG_PAIR, |
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355 | |||
356 | /* Described by mips_pcrel_operand. */ |
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357 | OP_PCREL, |
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358 | |||
359 | /* A performance register. The field is 5 bits in size, but the supported |
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360 | values are much more restricted. */ |
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361 | OP_PERF_REG, |
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362 | |||
363 | /* The final operand in a microMIPS ADDIUSP instruction. It mostly acts |
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364 | as a normal 9-bit signed offset that is multiplied by four, but there |
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365 | are four special cases: |
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366 | |||
367 | -2 * 4 => -258 * 4 |
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368 | -1 * 4 => -257 * 4 |
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369 | |||
370 | 1 * 4 => 257 * 4. */ |
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371 | OP_ADDIUSP_INT, |
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372 | |||
373 | /* The target of a (D)CLO or (D)CLZ instruction. The operand spans two |
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374 | 5-bit register fields, both of which must be set to the destination |
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375 | register. */ |
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376 | OP_CLO_CLZ_DEST, |
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377 | |||
378 | /* A register list for a microMIPS LWM or SWM instruction. The operand |
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379 | size determines whether the 16-bit or 32-bit encoding is required. */ |
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380 | OP_LWM_SWM_LIST, |
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381 | |||
382 | /* The register list for an emulated MIPS16 ENTRY or EXIT instruction. */ |
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383 | OP_ENTRY_EXIT_LIST, |
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384 | |||
385 | /* The register list and frame size for a MIPS16 SAVE or RESTORE |
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386 | instruction. */ |
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387 | OP_SAVE_RESTORE_LIST, |
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388 | |||
389 | /* A 10-bit field VVVVVNNNNN used for octobyte and quadhalf instructions: |
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390 | |||
391 | V Meaning |
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392 | ----- ------- |
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393 | 0EEE0 8 copies of $vN[E], OB format |
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394 | 0EE01 4 copies of $vN[E], QH format |
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395 | 10110 all 8 elements of $vN, OB format |
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396 | 10101 all 4 elements of $vN, QH format |
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397 | 11110 8 copies of immediate N, OB format |
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398 | 11101 4 copies of immediate N, QH format. */ |
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399 | OP_MDMX_IMM_REG, |
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400 | |||
401 | /* A register operand that must match the destination register. */ |
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402 | OP_REPEAT_DEST_REG, |
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403 | |||
404 | /* A register operand that must match the previous register. */ |
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405 | OP_REPEAT_PREV_REG, |
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406 | |||
407 | /* $pc, which has no encoding in the architectural instruction. */ |
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408 | OP_PC, |
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409 | |||
410 | /* A 4-bit XYZW channel mask or 2-bit XYZW index; the size determines |
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411 | which. */ |
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412 | OP_VU0_SUFFIX, |
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413 | |||
414 | /* Like OP_VU0_SUFFIX, but used when the operand's value has already |
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415 | been set. Any suffix used here must match the previous value. */ |
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416 | OP_VU0_MATCH_SUFFIX |
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417 | }; |
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418 | |||
419 | /* Enumerates the types of MIPS register. */ |
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420 | enum mips_reg_operand_type { |
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421 | /* General registers $0-$31. Software names like $at can also be used. */ |
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422 | OP_REG_GP, |
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423 | |||
424 | /* Floating-point registers $f0-$f31. */ |
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425 | OP_REG_FP, |
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426 | |||
427 | /* Coprocessor condition code registers $cc0-$cc7. FPU condition codes |
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428 | can also be written $fcc0-$fcc7. */ |
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429 | OP_REG_CCC, |
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430 | |||
431 | /* FPRs used in a vector capacity. They can be written $f0-$f31 |
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432 | or $v0-$v31, although the latter form is not used for the VR5400 |
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433 | vector instructions. */ |
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434 | OP_REG_VEC, |
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435 | |||
436 | /* DSP accumulator registers $ac0-$ac3. */ |
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437 | OP_REG_ACC, |
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438 | |||
439 | /* Coprocessor registers $0-$31. Mnemonic names like c0_cause can |
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440 | also be used in some contexts. */ |
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441 | OP_REG_COPRO, |
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442 | |||
443 | /* Hardware registers $0-$31. Mnemonic names like hwr_cpunum can |
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444 | also be used in some contexts. */ |
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445 | OP_REG_HW, |
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446 | |||
447 | /* Floating-point registers $vf0-$vf31. */ |
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448 | OP_REG_VF, |
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449 | |||
450 | /* Integer registers $vi0-$vi31. */ |
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451 | OP_REG_VI, |
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452 | |||
453 | /* R5900 VU0 registers $I, $Q, $R and $ACC. */ |
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454 | OP_REG_R5900_I, |
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455 | OP_REG_R5900_Q, |
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456 | OP_REG_R5900_R, |
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457 | OP_REG_R5900_ACC |
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458 | }; |
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459 | |||
460 | /* Base class for all operands. */ |
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461 | struct mips_operand |
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462 | { |
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463 | /* The type of the operand. */ |
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464 | enum mips_operand_type type; |
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465 | |||
466 | /* The operand occupies SIZE bits of the instruction, starting at LSB. */ |
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467 | unsigned short size; |
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468 | unsigned short lsb; |
||
469 | }; |
||
470 | |||
471 | /* Describes an integer operand with a regular encoding pattern. */ |
||
472 | struct mips_int_operand |
||
473 | { |
||
474 | struct mips_operand root; |
||
475 | |||
476 | /* The low ROOT.SIZE bits of MAX_VAL encodes (MAX_VAL + BIAS) << SHIFT. |
||
477 | The cyclically previous field value encodes 1 << SHIFT less than that, |
||
478 | and so on. E.g. |
||
479 | |||
480 | - for { { T, 4, L }, 14, 0, 0 }, field values 0...14 encode themselves, |
||
481 | but 15 encodes -1. |
||
482 | |||
483 | - { { T, 8, L }, 127, 0, 2 } is a normal signed 8-bit operand that is |
||
484 | shifted left two places. |
||
485 | |||
486 | - { { T, 3, L }, 8, 0, 0 } is a normal unsigned 3-bit operand except |
||
487 | that 0 encodes 8. |
||
488 | |||
489 | - { { ... }, 0, 1, 3 } means that N encodes (N + 1) << 3. */ |
||
490 | unsigned int max_val; |
||
491 | int bias; |
||
492 | unsigned int shift; |
||
493 | |||
494 | /* True if the operand should be printed as hex rather than decimal. */ |
||
495 | bfd_boolean print_hex; |
||
496 | }; |
||
497 | |||
498 | /* Uses a lookup table to describe a small integer operand. */ |
||
499 | struct mips_mapped_int_operand |
||
500 | { |
||
501 | struct mips_operand root; |
||
502 | |||
503 | /* Maps each encoding value to the integer that it represents. */ |
||
504 | const int *int_map; |
||
505 | |||
506 | /* True if the operand should be printed as hex rather than decimal. */ |
||
507 | bfd_boolean print_hex; |
||
508 | }; |
||
509 | |||
510 | /* An operand that encodes the most significant bit position of a bitfield. |
||
511 | Given a bitfield that spans bits [MSB, LSB], some operands of this type |
||
512 | encode MSB directly while others encode MSB - LSB. Each operand of this |
||
513 | type is preceded by an integer operand that specifies LSB. |
||
514 | |||
515 | The assembly form varies between instructions. For some instructions, |
||
516 | such as EXT, the operand is written as the bitfield size. For others, |
||
517 | such as EXTS, it is written in raw MSB - LSB form. */ |
||
518 | struct mips_msb_operand |
||
519 | { |
||
520 | struct mips_operand root; |
||
521 | |||
522 | /* The assembly-level operand encoded by a field value of 0. */ |
||
523 | int bias; |
||
524 | |||
525 | /* True if the operand encodes MSB directly, false if it encodes |
||
526 | MSB - LSB. */ |
||
527 | bfd_boolean add_lsb; |
||
528 | |||
529 | /* The maximum value of MSB + 1. */ |
||
530 | unsigned int opsize; |
||
531 | }; |
||
532 | |||
533 | /* Describes a single register operand. */ |
||
534 | struct mips_reg_operand |
||
535 | { |
||
536 | struct mips_operand root; |
||
537 | |||
538 | /* The type of register. */ |
||
539 | enum mips_reg_operand_type reg_type; |
||
540 | |||
541 | /* If nonnull, REG_MAP[N] gives the register associated with encoding N, |
||
542 | otherwise the encoding is the same as the register number. */ |
||
543 | const unsigned char *reg_map; |
||
544 | }; |
||
545 | |||
546 | /* Describes an operand that encodes a pair of registers. */ |
||
547 | struct mips_reg_pair_operand |
||
548 | { |
||
549 | struct mips_operand root; |
||
550 | |||
551 | /* The type of register. */ |
||
552 | enum mips_reg_operand_type reg_type; |
||
553 | |||
554 | /* Encoding N represents REG1_MAP[N], REG2_MAP[N]. */ |
||
555 | unsigned char *reg1_map; |
||
556 | unsigned char *reg2_map; |
||
557 | }; |
||
558 | |||
559 | /* Describes an operand that is calculated relative to a base PC. |
||
560 | The base PC is usually the address of the following instruction, |
||
561 | but the rules for MIPS16 instructions like ADDIUPC are more complicated. */ |
||
562 | struct mips_pcrel_operand |
||
563 | { |
||
564 | /* Encodes the offset. */ |
||
565 | struct mips_int_operand root; |
||
566 | |||
567 | /* The low ALIGN_LOG2 bits of the base PC are cleared to give PC', |
||
568 | which is then added to the offset encoded by ROOT. */ |
||
569 | unsigned int align_log2 : 8; |
||
570 | |||
571 | /* If INCLUDE_ISA_BIT, the ISA bit of the original base PC is then |
||
572 | reinstated. This is true for jumps and branches and false for |
||
573 | PC-relative data instructions. */ |
||
574 | unsigned int include_isa_bit : 1; |
||
575 | |||
576 | /* If FLIP_ISA_BIT, the ISA bit of the result is inverted. |
||
577 | This is true for JALX and false otherwise. */ |
||
578 | unsigned int flip_isa_bit : 1; |
||
579 | }; |
||
580 | |||
581 | /* Return true if the assembly syntax allows OPERAND to be omitted. */ |
||
582 | |||
583 | static inline bfd_boolean |
||
584 | mips_optional_operand_p (const struct mips_operand *operand) |
||
585 | { |
||
586 | return (operand->type == OP_OPTIONAL_REG |
||
587 | || operand->type == OP_REPEAT_PREV_REG); |
||
588 | } |
||
589 | |||
590 | /* Return a version of INSN in which the field specified by OPERAND |
||
591 | has value UVAL. */ |
||
592 | |||
593 | static inline unsigned int |
||
594 | mips_insert_operand (const struct mips_operand *operand, unsigned int insn, |
||
595 | unsigned int uval) |
||
596 | { |
||
597 | unsigned int mask; |
||
598 | |||
599 | mask = (1 << operand->size) - 1; |
||
600 | insn &= ~(mask << operand->lsb); |
||
601 | insn |= (uval & mask) << operand->lsb; |
||
602 | return insn; |
||
603 | } |
||
604 | |||
605 | /* Extract OPERAND from instruction INSN. */ |
||
606 | |||
607 | static inline unsigned int |
||
608 | mips_extract_operand (const struct mips_operand *operand, unsigned int insn) |
||
609 | { |
||
610 | return (insn >> operand->lsb) & ((1 << operand->size) - 1); |
||
611 | } |
||
612 | |||
613 | /* UVAL is the value encoded by OPERAND. Return it in signed form. */ |
||
614 | |||
615 | static inline int |
||
616 | mips_signed_operand (const struct mips_operand *operand, unsigned int uval) |
||
617 | { |
||
618 | unsigned int sign_bit, mask; |
||
619 | |||
620 | mask = (1 << operand->size) - 1; |
||
621 | sign_bit = 1 << (operand->size - 1); |
||
622 | return ((uval + sign_bit) & mask) - sign_bit; |
||
623 | } |
||
624 | |||
625 | /* Return the integer that OPERAND encodes as UVAL. */ |
||
626 | |||
627 | static inline int |
||
628 | mips_decode_int_operand (const struct mips_int_operand *operand, |
||
629 | unsigned int uval) |
||
630 | { |
||
631 | uval |= (operand->max_val - uval) & -(1 << operand->root.size); |
||
632 | uval += operand->bias; |
||
633 | uval <<= operand->shift; |
||
634 | return uval; |
||
635 | } |
||
636 | |||
637 | /* Return the maximum value that can be encoded by OPERAND. */ |
||
638 | |||
639 | static inline int |
||
640 | mips_int_operand_max (const struct mips_int_operand *operand) |
||
641 | { |
||
642 | return (operand->max_val + operand->bias) << operand->shift; |
||
643 | } |
||
644 | |||
645 | /* Return the minimum value that can be encoded by OPERAND. */ |
||
646 | |||
647 | static inline int |
||
648 | mips_int_operand_min (const struct mips_int_operand *operand) |
||
649 | { |
||
650 | unsigned int mask; |
||
651 | |||
652 | mask = (1 << operand->root.size) - 1; |
||
653 | return mips_int_operand_max (operand) - (mask << operand->shift); |
||
654 | } |
||
655 | |||
656 | /* Return the register that OPERAND encodes as UVAL. */ |
||
657 | |||
658 | static inline int |
||
659 | mips_decode_reg_operand (const struct mips_reg_operand *operand, |
||
660 | unsigned int uval) |
||
661 | { |
||
662 | if (operand->reg_map) |
||
663 | uval = operand->reg_map[uval]; |
||
664 | return uval; |
||
665 | } |
||
666 | |||
667 | /* PC-relative operand OPERAND has value UVAL and is relative to BASE_PC. |
||
668 | Return the address that it encodes. */ |
||
669 | |||
670 | static inline bfd_vma |
||
671 | mips_decode_pcrel_operand (const struct mips_pcrel_operand *operand, |
||
672 | bfd_vma base_pc, unsigned int uval) |
||
673 | { |
||
674 | bfd_vma addr; |
||
675 | |||
676 | addr = base_pc & -(1 << operand->align_log2); |
||
677 | addr += mips_decode_int_operand (&operand->root, uval); |
||
678 | if (operand->include_isa_bit) |
||
679 | addr |= base_pc & 1; |
||
680 | if (operand->flip_isa_bit) |
||
681 | addr ^= 1; |
||
682 | return addr; |
||
683 | } |
||
684 | |||
685 | /* This structure holds information for a particular instruction. */ |
||
686 | |||
687 | struct mips_opcode |
||
688 | { |
||
689 | /* The name of the instruction. */ |
||
690 | const char *name; |
||
691 | /* A string describing the arguments for this instruction. */ |
||
692 | const char *args; |
||
693 | /* The basic opcode for the instruction. When assembling, this |
||
694 | opcode is modified by the arguments to produce the actual opcode |
||
695 | that is used. If pinfo is INSN_MACRO, then this is 0. */ |
||
696 | unsigned long match; |
||
697 | /* If pinfo is not INSN_MACRO, then this is a bit mask for the |
||
698 | relevant portions of the opcode when disassembling. If the |
||
699 | actual opcode anded with the match field equals the opcode field, |
||
700 | then we have found the correct instruction. If pinfo is |
||
701 | INSN_MACRO, then this field is the macro identifier. */ |
||
702 | unsigned long mask; |
||
703 | /* For a macro, this is INSN_MACRO. Otherwise, it is a collection |
||
704 | of bits describing the instruction, notably any relevant hazard |
||
705 | information. */ |
||
706 | unsigned long pinfo; |
||
707 | /* A collection of additional bits describing the instruction. */ |
||
708 | unsigned long pinfo2; |
||
709 | /* A collection of bits describing the instruction sets of which this |
||
710 | instruction or macro is a member. */ |
||
711 | unsigned long membership; |
||
712 | /* A collection of bits describing the ASE of which this instruction |
||
713 | or macro is a member. */ |
||
714 | unsigned long ase; |
||
715 | /* A collection of bits describing the instruction sets of which this |
||
716 | instruction or macro is not a member. */ |
||
717 | unsigned long exclusions; |
||
718 | }; |
||
719 | |||
720 | /* These are the characters which may appear in the args field of an |
||
721 | instruction. They appear in the order in which the fields appear |
||
722 | when the instruction is used. Commas and parentheses in the args |
||
723 | string are ignored when assembling, and written into the output |
||
724 | when disassembling. |
||
725 | |||
726 | Each of these characters corresponds to a mask field defined above. |
||
727 | |||
728 | "1" 5 bit sync type (OP_*_STYPE) |
||
729 | "<" 5 bit shift amount (OP_*_SHAMT) |
||
730 | ">" shift amount between 32 and 63, stored after subtracting 32 (OP_*_SHAMT) |
||
731 | "a" 26 bit target address (OP_*_TARGET) |
||
732 | "+i" likewise, but flips bit 0 |
||
733 | "b" 5 bit base register (OP_*_RS) |
||
734 | "c" 10 bit breakpoint code (OP_*_CODE) |
||
735 | "d" 5 bit destination register specifier (OP_*_RD) |
||
736 | "h" 5 bit prefx hint (OP_*_PREFX) |
||
737 | "i" 16 bit unsigned immediate (OP_*_IMMEDIATE) |
||
738 | "j" 16 bit signed immediate (OP_*_DELTA) |
||
739 | "k" 5 bit cache opcode in target register position (OP_*_CACHE) |
||
740 | "o" 16 bit signed offset (OP_*_DELTA) |
||
741 | "p" 16 bit PC relative branch target address (OP_*_DELTA) |
||
742 | "q" 10 bit extra breakpoint code (OP_*_CODE2) |
||
743 | "r" 5 bit same register used as both source and target (OP_*_RS) |
||
744 | "s" 5 bit source register specifier (OP_*_RS) |
||
745 | "t" 5 bit target register (OP_*_RT) |
||
746 | "u" 16 bit upper 16 bits of address (OP_*_IMMEDIATE) |
||
747 | "v" 5 bit same register used as both source and destination (OP_*_RS) |
||
748 | "w" 5 bit same register used as both target and destination (OP_*_RT) |
||
749 | "U" 5 bit same destination register in both OP_*_RD and OP_*_RT |
||
750 | (used by clo and clz) |
||
751 | "C" 25 bit coprocessor function code (OP_*_COPZ) |
||
752 | "B" 20 bit syscall/breakpoint function code (OP_*_CODE20) |
||
753 | "J" 19 bit wait function code (OP_*_CODE19) |
||
754 | "x" accept and ignore register name |
||
755 | "z" must be zero register |
||
756 | "K" 5 bit Hardware Register (rdhwr instruction) (OP_*_RD) |
||
757 | "+A" 5 bit ins/ext/dins/dext/dinsm/dextm position, which becomes |
||
758 | LSB (OP_*_SHAMT; OP_*_EXTLSB or OP_*_STYPE may be used for |
||
759 | microMIPS compatibility). |
||
760 | Enforces: 0 <= pos < 32. |
||
761 | "+B" 5 bit ins/dins size, which becomes MSB (OP_*_INSMSB). |
||
762 | Requires that "+A" or "+E" occur first to set position. |
||
763 | Enforces: 0 < (pos+size) <= 32. |
||
764 | "+C" 5 bit ext/dext size, which becomes MSBD (OP_*_EXTMSBD). |
||
765 | Requires that "+A" or "+E" occur first to set position. |
||
766 | Enforces: 0 < (pos+size) <= 32. |
||
767 | (Also used by "dext" w/ different limits, but limits for |
||
768 | that are checked by the M_DEXT macro.) |
||
769 | "+E" 5 bit dinsu/dextu position, which becomes LSB-32 (OP_*_SHAMT). |
||
770 | Enforces: 32 <= pos < 64. |
||
771 | "+F" 5 bit "dinsm/dinsu" size, which becomes MSB-32 (OP_*_INSMSB). |
||
772 | Requires that "+A" or "+E" occur first to set position. |
||
773 | Enforces: 32 < (pos+size) <= 64. |
||
774 | "+G" 5 bit "dextm" size, which becomes MSBD-32 (OP_*_EXTMSBD). |
||
775 | Requires that "+A" or "+E" occur first to set position. |
||
776 | Enforces: 32 < (pos+size) <= 64. |
||
777 | "+H" 5 bit "dextu" size, which becomes MSBD (OP_*_EXTMSBD). |
||
778 | Requires that "+A" or "+E" occur first to set position. |
||
779 | Enforces: 32 < (pos+size) <= 64. |
||
780 | |||
781 | Floating point instructions: |
||
782 | "D" 5 bit destination register (OP_*_FD) |
||
783 | "M" 3 bit compare condition code (OP_*_CCC) (only used for mips4 and up) |
||
784 | "N" 3 bit branch condition code (OP_*_BCC) (only used for mips4 and up) |
||
785 | "S" 5 bit fs source 1 register (OP_*_FS) |
||
786 | "T" 5 bit ft source 2 register (OP_*_FT) |
||
787 | "R" 5 bit fr source 3 register (OP_*_FR) |
||
788 | "V" 5 bit same register used as floating source and destination (OP_*_FS) |
||
789 | "W" 5 bit same register used as floating target and destination (OP_*_FT) |
||
790 | |||
791 | Coprocessor instructions: |
||
792 | "E" 5 bit target register (OP_*_RT) |
||
793 | "G" 5 bit destination register (OP_*_RD) |
||
794 | "H" 3 bit sel field for (d)mtc* and (d)mfc* (OP_*_SEL) |
||
795 | "P" 5 bit performance-monitor register (OP_*_PERFREG) |
||
796 | "e" 5 bit vector register byte specifier (OP_*_VECBYTE) |
||
797 | "%" 3 bit immediate vr5400 vector alignment operand (OP_*_VECALIGN) |
||
798 | |||
799 | Macro instructions: |
||
800 | "A" General 32 bit expression |
||
801 | "I" 32 bit immediate (value placed in imm_expr). |
||
802 | "F" 64 bit floating point constant in .rdata |
||
803 | "L" 64 bit floating point constant in .lit8 |
||
804 | "f" 32 bit floating point constant |
||
805 | "l" 32 bit floating point constant in .lit4 |
||
806 | |||
807 | MDMX and VR5400 instruction operands (note that while these use the |
||
808 | FP register fields, the MDMX instructions accept both $fN and $vN names |
||
809 | for the registers): |
||
810 | "O" alignment offset (OP_*_ALN) |
||
811 | "Q" vector/scalar/immediate source (OP_*_VSEL and OP_*_FT) |
||
812 | "X" destination register (OP_*_FD) |
||
813 | "Y" source register (OP_*_FS) |
||
814 | "Z" source register (OP_*_FT) |
||
815 | |||
816 | R5900 VU0 Macromode instructions: |
||
817 | "+5" 5 bit floating point register (FD) |
||
818 | "+6" 5 bit floating point register (FS) |
||
819 | "+7" 5 bit floating point register (FT) |
||
820 | "+8" 5 bit integer register (FD) |
||
821 | "+9" 5 bit integer register (FS) |
||
822 | "+0" 5 bit integer register (FT) |
||
823 | "+K" match an existing 4-bit channel mask starting at bit 21 |
||
824 | "+L" 2-bit channel index starting at bit 21 |
||
825 | "+M" 2-bit channel index starting at bit 23 |
||
826 | "+N" match an existing 2-bit channel index starting at bit 0 |
||
827 | "+f" 15 bit immediate for VCALLMS |
||
828 | "+g" 5 bit signed immediate for VIADDI |
||
829 | "+m" $ACC register (syntax only) |
||
830 | "+q" $Q register (syntax only) |
||
831 | "+r" $R register (syntax only) |
||
832 | "+y" $I register (syntax only) |
||
833 | "#+" "++" decorator in ($reg++) sequence |
||
834 | "#-" "--" decorator in (--$reg) sequence |
||
835 | |||
836 | DSP ASE usage: |
||
837 | "2" 2 bit unsigned immediate for byte align (OP_*_BP) |
||
838 | "3" 3 bit unsigned immediate (OP_*_SA3) |
||
839 | "4" 4 bit unsigned immediate (OP_*_SA4) |
||
840 | "5" 8 bit unsigned immediate (OP_*_IMM8) |
||
841 | "6" 5 bit unsigned immediate (OP_*_RS) |
||
842 | "7" 2 bit dsp accumulator register (OP_*_DSPACC) |
||
843 | "8" 6 bit unsigned immediate (OP_*_WRDSP) |
||
844 | "9" 2 bit dsp accumulator register (OP_*_DSPACC_S) |
||
845 | "0" 6 bit signed immediate (OP_*_DSPSFT) |
||
846 | ":" 7 bit signed immediate (OP_*_DSPSFT_7) |
||
847 | "'" 6 bit unsigned immediate (OP_*_RDDSP) |
||
848 | "@" 10 bit signed immediate (OP_*_IMM10) |
||
849 | |||
850 | MT ASE usage: |
||
851 | "!" 1 bit usermode flag (OP_*_MT_U) |
||
852 | "$" 1 bit load high flag (OP_*_MT_H) |
||
853 | "*" 2 bit dsp/smartmips accumulator register (OP_*_MTACC_T) |
||
854 | "&" 2 bit dsp/smartmips accumulator register (OP_*_MTACC_D) |
||
855 | "g" 5 bit coprocessor 1 and 2 destination register (OP_*_RD) |
||
856 | "+t" 5 bit coprocessor 0 destination register (OP_*_RT) |
||
857 | |||
858 | MCU ASE usage: |
||
859 | "~" 12 bit offset (OP_*_OFFSET12) |
||
860 | "\" 3 bit position for aset and aclr (OP_*_3BITPOS) |
||
861 | |||
862 | VIRT ASE usage: |
||
863 | "+J" 10-bit hypcall code (OP_*CODE10) |
||
864 | |||
865 | UDI immediates: |
||
866 | "+1" UDI immediate bits 6-10 |
||
867 | "+2" UDI immediate bits 6-15 |
||
868 | "+3" UDI immediate bits 6-20 |
||
869 | "+4" UDI immediate bits 6-25 |
||
870 | |||
871 | Octeon: |
||
872 | "+x" Bit index field of bbit. Enforces: 0 <= index < 32. |
||
873 | "+X" Bit index field of bbit aliasing bbit32. Matches if 32 <= index < 64, |
||
874 | otherwise skips to next candidate. |
||
875 | "+p" Position field of cins/cins32/exts/exts32. Enforces 0 <= pos < 32. |
||
876 | "+P" Position field of cins/exts aliasing cins32/exts32. Matches if |
||
877 | 32 <= pos < 64, otherwise skips to next candidate. |
||
878 | "+Q" Immediate field of seqi/snei. Enforces -512 <= imm < 512. |
||
879 | "+s" Length-minus-one field of cins32/exts32. Requires msb position |
||
880 | of the field to be <= 31. |
||
881 | "+S" Length-minus-one field of cins/exts. Requires msb position |
||
882 | of the field to be <= 63. |
||
883 | |||
884 | Loongson-3A: |
||
885 | "+a" 8-bit signed offset in bit 6 (OP_*_OFFSET_A) |
||
886 | "+b" 8-bit signed offset in bit 3 (OP_*_OFFSET_B) |
||
887 | "+c" 9-bit signed offset in bit 6 (OP_*_OFFSET_C) |
||
888 | "+z" 5-bit rz register (OP_*_RZ) |
||
889 | "+Z" 5-bit fz register (OP_*_FZ) |
||
890 | |||
891 | Enhanced VA Scheme: |
||
892 | "+j" 9-bit signed offset in bit 7 (OP_*_EVAOFFSET) |
||
893 | |||
894 | Other: |
||
895 | "()" parens surrounding optional value |
||
896 | "," separates operands |
||
897 | "+" Start of extension sequence. |
||
898 | |||
899 | Characters used so far, for quick reference when adding more: |
||
900 | "1234567890" |
||
901 | "%[]<>(),+:'@!#$*&\~" |
||
902 | "ABCDEFGHIJKLMNOPQRSTUVWXYZ" |
||
903 | "abcdefghijklopqrstuvwxz" |
||
904 | |||
905 | Extension character sequences used so far ("+" followed by the |
||
906 | following), for quick reference when adding more: |
||
907 | "1234567890" |
||
908 | "ABCEFGHJKLMNPQSXZ" |
||
909 | "abcfgijmpqrstxyz" |
||
910 | */ |
||
911 | |||
912 | /* These are the bits which may be set in the pinfo field of an |
||
913 | instructions, if it is not equal to INSN_MACRO. */ |
||
914 | |||
915 | /* Writes to operand number N. */ |
||
916 | #define INSN_WRITE_SHIFT 0 |
||
917 | #define INSN_WRITE_1 0x00000001 |
||
918 | #define INSN_WRITE_2 0x00000002 |
||
919 | #define INSN_WRITE_ALL 0x00000003 |
||
920 | /* Reads from operand number N. */ |
||
921 | #define INSN_READ_SHIFT 2 |
||
922 | #define INSN_READ_1 0x00000004 |
||
923 | #define INSN_READ_2 0x00000008 |
||
924 | #define INSN_READ_3 0x00000010 |
||
925 | #define INSN_READ_4 0x00000020 |
||
926 | #define INSN_READ_ALL 0x0000003c |
||
927 | /* Modifies general purpose register 31. */ |
||
928 | #define INSN_WRITE_GPR_31 0x00000040 |
||
929 | /* Modifies coprocessor condition code. */ |
||
930 | #define INSN_WRITE_COND_CODE 0x00000080 |
||
931 | /* Reads coprocessor condition code. */ |
||
932 | #define INSN_READ_COND_CODE 0x00000100 |
||
933 | /* TLB operation. */ |
||
934 | #define INSN_TLB 0x00000200 |
||
935 | /* Reads coprocessor register other than floating point register. */ |
||
936 | #define INSN_COP 0x00000400 |
||
937 | /* Instruction loads value from memory, requiring delay. */ |
||
938 | #define INSN_LOAD_MEMORY_DELAY 0x00000800 |
||
939 | /* Instruction loads value from coprocessor, requiring delay. */ |
||
940 | #define INSN_LOAD_COPROC_DELAY 0x00001000 |
||
941 | /* Instruction has unconditional branch delay slot. */ |
||
942 | #define INSN_UNCOND_BRANCH_DELAY 0x00002000 |
||
943 | /* Instruction has conditional branch delay slot. */ |
||
944 | #define INSN_COND_BRANCH_DELAY 0x00004000 |
||
945 | /* Conditional branch likely: if branch not taken, insn nullified. */ |
||
946 | #define INSN_COND_BRANCH_LIKELY 0x00008000 |
||
947 | /* Moves to coprocessor register, requiring delay. */ |
||
948 | #define INSN_COPROC_MOVE_DELAY 0x00010000 |
||
949 | /* Loads coprocessor register from memory, requiring delay. */ |
||
950 | #define INSN_COPROC_MEMORY_DELAY 0x00020000 |
||
951 | /* Reads the HI register. */ |
||
952 | #define INSN_READ_HI 0x00040000 |
||
953 | /* Reads the LO register. */ |
||
954 | #define INSN_READ_LO 0x00080000 |
||
955 | /* Modifies the HI register. */ |
||
956 | #define INSN_WRITE_HI 0x00100000 |
||
957 | /* Modifies the LO register. */ |
||
958 | #define INSN_WRITE_LO 0x00200000 |
||
959 | /* Not to be placed in a branch delay slot, either architecturally |
||
960 | or for ease of handling (such as with instructions that take a trap). */ |
||
961 | #define INSN_NO_DELAY_SLOT 0x00400000 |
||
962 | /* Instruction stores value into memory. */ |
||
963 | #define INSN_STORE_MEMORY 0x00800000 |
||
964 | /* Instruction uses single precision floating point. */ |
||
965 | #define FP_S 0x01000000 |
||
966 | /* Instruction uses double precision floating point. */ |
||
967 | #define FP_D 0x02000000 |
||
968 | /* Instruction is part of the tx39's integer multiply family. */ |
||
969 | #define INSN_MULT 0x04000000 |
||
970 | /* Reads general purpose register 24. */ |
||
971 | #define INSN_READ_GPR_24 0x08000000 |
||
972 | /* Writes to general purpose register 24. */ |
||
973 | #define INSN_WRITE_GPR_24 0x10000000 |
||
974 | /* A user-defined instruction. */ |
||
975 | #define INSN_UDI 0x20000000 |
||
976 | /* Instruction is actually a macro. It should be ignored by the |
||
977 | disassembler, and requires special treatment by the assembler. */ |
||
978 | #define INSN_MACRO 0xffffffff |
||
979 | |||
980 | /* These are the bits which may be set in the pinfo2 field of an |
||
981 | instruction. */ |
||
982 | |||
983 | /* Instruction is a simple alias (I.E. "move" for daddu/addu/or) */ |
||
984 | #define INSN2_ALIAS 0x00000001 |
||
985 | /* Instruction reads MDMX accumulator. */ |
||
986 | #define INSN2_READ_MDMX_ACC 0x00000002 |
||
987 | /* Instruction writes MDMX accumulator. */ |
||
988 | #define INSN2_WRITE_MDMX_ACC 0x00000004 |
||
989 | /* Macro uses single-precision floating-point instructions. This should |
||
990 | only be set for macros. For instructions, FP_S in pinfo carries the |
||
991 | same information. */ |
||
992 | #define INSN2_M_FP_S 0x00000008 |
||
993 | /* Macro uses double-precision floating-point instructions. This should |
||
994 | only be set for macros. For instructions, FP_D in pinfo carries the |
||
995 | same information. */ |
||
996 | #define INSN2_M_FP_D 0x00000010 |
||
997 | /* Instruction has a branch delay slot that requires a 16-bit instruction. */ |
||
998 | #define INSN2_BRANCH_DELAY_16BIT 0x00000020 |
||
999 | /* Instruction has a branch delay slot that requires a 32-bit instruction. */ |
||
1000 | #define INSN2_BRANCH_DELAY_32BIT 0x00000040 |
||
1001 | /* Writes to the stack pointer ($29). */ |
||
1002 | #define INSN2_WRITE_SP 0x00000080 |
||
1003 | /* Reads from the stack pointer ($29). */ |
||
1004 | #define INSN2_READ_SP 0x00000100 |
||
1005 | /* Reads the RA ($31) register. */ |
||
1006 | #define INSN2_READ_GPR_31 0x00000200 |
||
1007 | /* Reads the program counter ($pc). */ |
||
1008 | #define INSN2_READ_PC 0x00000400 |
||
1009 | /* Is an unconditional branch insn. */ |
||
1010 | #define INSN2_UNCOND_BRANCH 0x00000800 |
||
1011 | /* Is a conditional branch insn. */ |
||
1012 | #define INSN2_COND_BRANCH 0x00001000 |
||
1013 | /* Reads from $16. This is true of the MIPS16 0x6500 nop. */ |
||
1014 | #define INSN2_READ_GPR_16 0x00002000 |
||
1015 | /* Has an "\.x?y?z?w?" suffix based on mips_vu0_channel_mask. */ |
||
1016 | #define INSN2_VU0_CHANNEL_SUFFIX 0x00004000 |
||
1017 | |||
1018 | /* Masks used to mark instructions to indicate which MIPS ISA level |
||
1019 | they were introduced in. INSN_ISA_MASK masks an enumeration that |
||
1020 | specifies the base ISA level(s). The remainder of a 32-bit |
||
1021 | word constructed using these macros is a bitmask of the remaining |
||
1022 | INSN_* values below. */ |
||
1023 | |||
1024 | #define INSN_ISA_MASK 0x0000000ful |
||
1025 | |||
1026 | /* We cannot start at zero due to ISA_UNKNOWN below. */ |
||
1027 | #define INSN_ISA1 1 |
||
1028 | #define INSN_ISA2 2 |
||
1029 | #define INSN_ISA3 3 |
||
1030 | #define INSN_ISA4 4 |
||
1031 | #define INSN_ISA5 5 |
||
1032 | #define INSN_ISA32 6 |
||
1033 | #define INSN_ISA32R2 7 |
||
1034 | #define INSN_ISA64 8 |
||
1035 | #define INSN_ISA64R2 9 |
||
1036 | /* Below this point the INSN_* values correspond to combinations of ISAs. |
||
1037 | They are only for use in the opcodes table to indicate membership of |
||
1038 | a combination of ISAs that cannot be expressed using the usual inclusion |
||
1039 | ordering on the above INSN_* values. */ |
||
1040 | #define INSN_ISA3_32 10 |
||
1041 | #define INSN_ISA3_32R2 11 |
||
1042 | #define INSN_ISA4_32 12 |
||
1043 | #define INSN_ISA4_32R2 13 |
||
1044 | #define INSN_ISA5_32R2 14 |
||
1045 | |||
1046 | /* Given INSN_ISA* values X and Y, where X ranges over INSN_ISA1 through |
||
1047 | INSN_ISA5_32R2 and Y ranges over INSN_ISA1 through INSN_ISA64R2, |
||
1048 | this table describes whether at least one of the ISAs described by X |
||
1049 | is/are implemented by ISA Y. (Think of Y as the ISA level supported by |
||
1050 | a particular core and X as the ISA level(s) at which a certain instruction |
||
1051 | is defined.) The ISA(s) described by X is/are implemented by Y iff |
||
1052 | (mips_isa_table[(Y & INSN_ISA_MASK) - 1] >> ((X & INSN_ISA_MASK) - 1)) & 1 |
||
1053 | is non-zero. */ |
||
1054 | static const unsigned int mips_isa_table[] = |
||
1055 | { 0x0001, 0x0003, 0x0607, 0x1e0f, 0x3e1f, 0x0a23, 0x3e63, 0x3ebf, 0x3fff }; |
||
1056 | |||
1057 | /* Masks used for Chip specific instructions. */ |
||
1058 | #define INSN_CHIP_MASK 0xc3ff0f20 |
||
1059 | |||
1060 | /* Cavium Networks Octeon instructions. */ |
||
1061 | #define INSN_OCTEON 0x00000800 |
||
1062 | #define INSN_OCTEONP 0x00000200 |
||
1063 | #define INSN_OCTEON2 0x00000100 |
||
1064 | |||
1065 | /* MIPS R5900 instruction */ |
||
1066 | #define INSN_5900 0x00004000 |
||
1067 | |||
1068 | /* MIPS R4650 instruction. */ |
||
1069 | #define INSN_4650 0x00010000 |
||
1070 | /* LSI R4010 instruction. */ |
||
1071 | #define INSN_4010 0x00020000 |
||
1072 | /* NEC VR4100 instruction. */ |
||
1073 | #define INSN_4100 0x00040000 |
||
1074 | /* Toshiba R3900 instruction. */ |
||
1075 | #define INSN_3900 0x00080000 |
||
1076 | /* MIPS R10000 instruction. */ |
||
1077 | #define INSN_10000 0x00100000 |
||
1078 | /* Broadcom SB-1 instruction. */ |
||
1079 | #define INSN_SB1 0x00200000 |
||
1080 | /* NEC VR4111/VR4181 instruction. */ |
||
1081 | #define INSN_4111 0x00400000 |
||
1082 | /* NEC VR4120 instruction. */ |
||
1083 | #define INSN_4120 0x00800000 |
||
1084 | /* NEC VR5400 instruction. */ |
||
1085 | #define INSN_5400 0x01000000 |
||
1086 | /* NEC VR5500 instruction. */ |
||
1087 | #define INSN_5500 0x02000000 |
||
1088 | |||
1089 | /* ST Microelectronics Loongson 2E. */ |
||
1090 | #define INSN_LOONGSON_2E 0x40000000 |
||
1091 | /* ST Microelectronics Loongson 2F. */ |
||
1092 | #define INSN_LOONGSON_2F 0x80000000 |
||
1093 | /* Loongson 3A. */ |
||
1094 | #define INSN_LOONGSON_3A 0x00000400 |
||
1095 | /* RMI Xlr instruction */ |
||
1096 | #define INSN_XLR 0x00000020 |
||
1097 | |||
1098 | /* DSP ASE */ |
||
1099 | #define ASE_DSP 0x00000001 |
||
1100 | #define ASE_DSP64 0x00000002 |
||
1101 | /* DSP R2 ASE */ |
||
1102 | #define ASE_DSPR2 0x00000004 |
||
1103 | /* Enhanced VA Scheme */ |
||
1104 | #define ASE_EVA 0x00000008 |
||
1105 | /* MCU (MicroController) ASE */ |
||
1106 | #define ASE_MCU 0x00000010 |
||
1107 | /* MDMX ASE */ |
||
1108 | #define ASE_MDMX 0x00000020 |
||
1109 | /* MIPS-3D ASE */ |
||
1110 | #define ASE_MIPS3D 0x00000040 |
||
1111 | /* MT ASE */ |
||
1112 | #define ASE_MT 0x00000080 |
||
1113 | /* SmartMIPS ASE */ |
||
1114 | #define ASE_SMARTMIPS 0x00000100 |
||
1115 | /* Virtualization ASE */ |
||
1116 | #define ASE_VIRT 0x00000200 |
||
1117 | #define ASE_VIRT64 0x00000400 |
||
1118 | |||
1119 | /* MIPS ISA defines, use instead of hardcoding ISA level. */ |
||
1120 | |||
1121 | #define ISA_UNKNOWN 0 /* Gas internal use. */ |
||
1122 | #define ISA_MIPS1 INSN_ISA1 |
||
1123 | #define ISA_MIPS2 INSN_ISA2 |
||
1124 | #define ISA_MIPS3 INSN_ISA3 |
||
1125 | #define ISA_MIPS4 INSN_ISA4 |
||
1126 | #define ISA_MIPS5 INSN_ISA5 |
||
1127 | |||
1128 | #define ISA_MIPS32 INSN_ISA32 |
||
1129 | #define ISA_MIPS64 INSN_ISA64 |
||
1130 | |||
1131 | #define ISA_MIPS32R2 INSN_ISA32R2 |
||
1132 | #define ISA_MIPS64R2 INSN_ISA64R2 |
||
1133 | |||
1134 | |||
1135 | /* CPU defines, use instead of hardcoding processor number. Keep this |
||
1136 | in sync with bfd/archures.c in order for machine selection to work. */ |
||
1137 | #define CPU_UNKNOWN 0 /* Gas internal use. */ |
||
1138 | #define CPU_R3000 3000 |
||
1139 | #define CPU_R3900 3900 |
||
1140 | #define CPU_R4000 4000 |
||
1141 | #define CPU_R4010 4010 |
||
1142 | #define CPU_VR4100 4100 |
||
1143 | #define CPU_R4111 4111 |
||
1144 | #define CPU_VR4120 4120 |
||
1145 | #define CPU_R4300 4300 |
||
1146 | #define CPU_R4400 4400 |
||
1147 | #define CPU_R4600 4600 |
||
1148 | #define CPU_R4650 4650 |
||
1149 | #define CPU_R5000 5000 |
||
1150 | #define CPU_VR5400 5400 |
||
1151 | #define CPU_VR5500 5500 |
||
1152 | #define CPU_R5900 5900 |
||
1153 | #define CPU_R6000 6000 |
||
1154 | #define CPU_RM7000 7000 |
||
1155 | #define CPU_R8000 8000 |
||
1156 | #define CPU_RM9000 9000 |
||
1157 | #define CPU_R10000 10000 |
||
1158 | #define CPU_R12000 12000 |
||
1159 | #define CPU_R14000 14000 |
||
1160 | #define CPU_R16000 16000 |
||
1161 | #define CPU_MIPS16 16 |
||
1162 | #define CPU_MIPS32 32 |
||
1163 | #define CPU_MIPS32R2 33 |
||
1164 | #define CPU_MIPS5 5 |
||
1165 | #define CPU_MIPS64 64 |
||
1166 | #define CPU_MIPS64R2 65 |
||
1167 | #define CPU_SB1 12310201 /* octal 'SB', 01. */ |
||
1168 | #define CPU_LOONGSON_2E 3001 |
||
1169 | #define CPU_LOONGSON_2F 3002 |
||
1170 | #define CPU_LOONGSON_3A 3003 |
||
1171 | #define CPU_OCTEON 6501 |
||
1172 | #define CPU_OCTEONP 6601 |
||
1173 | #define CPU_OCTEON2 6502 |
||
1174 | #define CPU_XLR 887682 /* decimal 'XLR' */ |
||
1175 | |||
1176 | /* Return true if the given CPU is included in INSN_* mask MASK. */ |
||
1177 | |||
1178 | static inline bfd_boolean |
||
1179 | cpu_is_member (int cpu, unsigned int mask) |
||
1180 | { |
||
1181 | switch (cpu) |
||
1182 | { |
||
1183 | case CPU_R4650: |
||
1184 | case CPU_RM7000: |
||
1185 | case CPU_RM9000: |
||
1186 | return (mask & INSN_4650) != 0; |
||
1187 | |||
1188 | case CPU_R4010: |
||
1189 | return (mask & INSN_4010) != 0; |
||
1190 | |||
1191 | case CPU_VR4100: |
||
1192 | return (mask & INSN_4100) != 0; |
||
1193 | |||
1194 | case CPU_R3900: |
||
1195 | return (mask & INSN_3900) != 0; |
||
1196 | |||
1197 | case CPU_R10000: |
||
1198 | case CPU_R12000: |
||
1199 | case CPU_R14000: |
||
1200 | case CPU_R16000: |
||
1201 | return (mask & INSN_10000) != 0; |
||
1202 | |||
1203 | case CPU_SB1: |
||
1204 | return (mask & INSN_SB1) != 0; |
||
1205 | |||
1206 | case CPU_R4111: |
||
1207 | return (mask & INSN_4111) != 0; |
||
1208 | |||
1209 | case CPU_VR4120: |
||
1210 | return (mask & INSN_4120) != 0; |
||
1211 | |||
1212 | case CPU_VR5400: |
||
1213 | return (mask & INSN_5400) != 0; |
||
1214 | |||
1215 | case CPU_VR5500: |
||
1216 | return (mask & INSN_5500) != 0; |
||
1217 | |||
1218 | case CPU_R5900: |
||
1219 | return (mask & INSN_5900) != 0; |
||
1220 | |||
1221 | case CPU_LOONGSON_2E: |
||
1222 | return (mask & INSN_LOONGSON_2E) != 0; |
||
1223 | |||
1224 | case CPU_LOONGSON_2F: |
||
1225 | return (mask & INSN_LOONGSON_2F) != 0; |
||
1226 | |||
1227 | case CPU_LOONGSON_3A: |
||
1228 | return (mask & INSN_LOONGSON_3A) != 0; |
||
1229 | |||
1230 | case CPU_OCTEON: |
||
1231 | return (mask & INSN_OCTEON) != 0; |
||
1232 | |||
1233 | case CPU_OCTEONP: |
||
1234 | return (mask & INSN_OCTEONP) != 0; |
||
1235 | |||
1236 | case CPU_OCTEON2: |
||
1237 | return (mask & INSN_OCTEON2) != 0; |
||
1238 | |||
1239 | case CPU_XLR: |
||
1240 | return (mask & INSN_XLR) != 0; |
||
1241 | |||
1242 | default: |
||
1243 | return FALSE; |
||
1244 | } |
||
1245 | } |
||
1246 | |||
1247 | /* Test for membership in an ISA including chip specific ISAs. INSN |
||
1248 | is pointer to an element of the opcode table; ISA is the specified |
||
1249 | ISA/ASE bitmask to test against; and CPU is the CPU specific ISA to |
||
1250 | test, or zero if no CPU specific ISA test is desired. Return true |
||
1251 | if instruction INSN is available to the given ISA and CPU. */ |
||
1252 | |||
1253 | static inline bfd_boolean |
||
1254 | opcode_is_member (const struct mips_opcode *insn, int isa, int ase, int cpu) |
||
1255 | { |
||
1256 | if (!cpu_is_member (cpu, insn->exclusions)) |
||
1257 | { |
||
1258 | /* Test for ISA level compatibility. */ |
||
1259 | if ((isa & INSN_ISA_MASK) != 0 |
||
1260 | && (insn->membership & INSN_ISA_MASK) != 0 |
||
1261 | && ((mips_isa_table[(isa & INSN_ISA_MASK) - 1] |
||
1262 | >> ((insn->membership & INSN_ISA_MASK) - 1)) & 1) != 0) |
||
1263 | return TRUE; |
||
1264 | |||
1265 | /* Test for ASE compatibility. */ |
||
1266 | if ((ase & insn->ase) != 0) |
||
1267 | return TRUE; |
||
1268 | |||
1269 | /* Test for processor-specific extensions. */ |
||
1270 | if (cpu_is_member (cpu, insn->membership)) |
||
1271 | return TRUE; |
||
1272 | } |
||
1273 | return FALSE; |
||
1274 | } |
||
1275 | |||
1276 | /* This is a list of macro expanded instructions. |
||
1277 | |||
1278 | _I appended means immediate |
||
1279 | _A appended means target address of a jump |
||
1280 | _AB appended means address with (possibly zero) base register |
||
1281 | _D appended means 64 bit floating point constant |
||
1282 | _S appended means 32 bit floating point constant. */ |
||
1283 | |||
1284 | enum |
||
1285 | { |
||
1286 | M_ABS, |
||
1287 | M_ACLR_AB, |
||
1288 | M_ADD_I, |
||
1289 | M_ADDU_I, |
||
1290 | M_AND_I, |
||
1291 | M_ASET_AB, |
||
1292 | M_BALIGN, |
||
1293 | M_BC1FL, |
||
1294 | M_BC1TL, |
||
1295 | M_BC2FL, |
||
1296 | M_BC2TL, |
||
1297 | M_BEQ, |
||
1298 | M_BEQ_I, |
||
1299 | M_BEQL, |
||
1300 | M_BEQL_I, |
||
1301 | M_BGE, |
||
1302 | M_BGEL, |
||
1303 | M_BGE_I, |
||
1304 | M_BGEL_I, |
||
1305 | M_BGEU, |
||
1306 | M_BGEUL, |
||
1307 | M_BGEU_I, |
||
1308 | M_BGEUL_I, |
||
1309 | M_BGEZ, |
||
1310 | M_BGEZL, |
||
1311 | M_BGEZALL, |
||
1312 | M_BGT, |
||
1313 | M_BGTL, |
||
1314 | M_BGT_I, |
||
1315 | M_BGTL_I, |
||
1316 | M_BGTU, |
||
1317 | M_BGTUL, |
||
1318 | M_BGTU_I, |
||
1319 | M_BGTUL_I, |
||
1320 | M_BGTZ, |
||
1321 | M_BGTZL, |
||
1322 | M_BLE, |
||
1323 | M_BLEL, |
||
1324 | M_BLE_I, |
||
1325 | M_BLEL_I, |
||
1326 | M_BLEU, |
||
1327 | M_BLEUL, |
||
1328 | M_BLEU_I, |
||
1329 | M_BLEUL_I, |
||
1330 | M_BLEZ, |
||
1331 | M_BLEZL, |
||
1332 | M_BLT, |
||
1333 | M_BLTL, |
||
1334 | M_BLT_I, |
||
1335 | M_BLTL_I, |
||
1336 | M_BLTU, |
||
1337 | M_BLTUL, |
||
1338 | M_BLTU_I, |
||
1339 | M_BLTUL_I, |
||
1340 | M_BLTZ, |
||
1341 | M_BLTZL, |
||
1342 | M_BLTZALL, |
||
1343 | M_BNE, |
||
1344 | M_BNEL, |
||
1345 | M_BNE_I, |
||
1346 | M_BNEL_I, |
||
1347 | M_CACHE_AB, |
||
1348 | M_CACHEE_AB, |
||
1349 | M_DABS, |
||
1350 | M_DADD_I, |
||
1351 | M_DADDU_I, |
||
1352 | M_DDIV_3, |
||
1353 | M_DDIV_3I, |
||
1354 | M_DDIVU_3, |
||
1355 | M_DDIVU_3I, |
||
1356 | M_DIV_3, |
||
1357 | M_DIV_3I, |
||
1358 | M_DIVU_3, |
||
1359 | M_DIVU_3I, |
||
1360 | M_DLA_AB, |
||
1361 | M_DLCA_AB, |
||
1362 | M_DLI, |
||
1363 | M_DMUL, |
||
1364 | M_DMUL_I, |
||
1365 | M_DMULO, |
||
1366 | M_DMULO_I, |
||
1367 | M_DMULOU, |
||
1368 | M_DMULOU_I, |
||
1369 | M_DREM_3, |
||
1370 | M_DREM_3I, |
||
1371 | M_DREMU_3, |
||
1372 | M_DREMU_3I, |
||
1373 | M_DSUB_I, |
||
1374 | M_DSUBU_I, |
||
1375 | M_DSUBU_I_2, |
||
1376 | M_J_A, |
||
1377 | M_JAL_1, |
||
1378 | M_JAL_2, |
||
1379 | M_JAL_A, |
||
1380 | M_JALS_1, |
||
1381 | M_JALS_2, |
||
1382 | M_JALS_A, |
||
1383 | M_JRADDIUSP, |
||
1384 | M_JRC, |
||
1385 | M_L_DAB, |
||
1386 | M_LA_AB, |
||
1387 | M_LB_AB, |
||
1388 | M_LBE_AB, |
||
1389 | M_LBU_AB, |
||
1390 | M_LBUE_AB, |
||
1391 | M_LCA_AB, |
||
1392 | M_LD_AB, |
||
1393 | M_LDC1_AB, |
||
1394 | M_LDC2_AB, |
||
1395 | M_LQC2_AB, |
||
1396 | M_LDC3_AB, |
||
1397 | M_LDL_AB, |
||
1398 | M_LDM_AB, |
||
1399 | M_LDP_AB, |
||
1400 | M_LDR_AB, |
||
1401 | M_LH_AB, |
||
1402 | M_LHE_AB, |
||
1403 | M_LHU_AB, |
||
1404 | M_LHUE_AB, |
||
1405 | M_LI, |
||
1406 | M_LI_D, |
||
1407 | M_LI_DD, |
||
1408 | M_LI_S, |
||
1409 | M_LI_SS, |
||
1410 | M_LL_AB, |
||
1411 | M_LLD_AB, |
||
1412 | M_LLE_AB, |
||
1413 | M_LQ_AB, |
||
1414 | M_LW_AB, |
||
1415 | M_LWE_AB, |
||
1416 | M_LWC0_AB, |
||
1417 | M_LWC1_AB, |
||
1418 | M_LWC2_AB, |
||
1419 | M_LWC3_AB, |
||
1420 | M_LWL_AB, |
||
1421 | M_LWLE_AB, |
||
1422 | M_LWM_AB, |
||
1423 | M_LWP_AB, |
||
1424 | M_LWR_AB, |
||
1425 | M_LWRE_AB, |
||
1426 | M_LWU_AB, |
||
1427 | M_MSGSND, |
||
1428 | M_MSGLD, |
||
1429 | M_MSGLD_T, |
||
1430 | M_MSGWAIT, |
||
1431 | M_MSGWAIT_T, |
||
1432 | M_MOVE, |
||
1433 | M_MOVEP, |
||
1434 | M_MUL, |
||
1435 | M_MUL_I, |
||
1436 | M_MULO, |
||
1437 | M_MULO_I, |
||
1438 | M_MULOU, |
||
1439 | M_MULOU_I, |
||
1440 | M_NOR_I, |
||
1441 | M_OR_I, |
||
1442 | M_PREF_AB, |
||
1443 | M_PREFE_AB, |
||
1444 | M_REM_3, |
||
1445 | M_REM_3I, |
||
1446 | M_REMU_3, |
||
1447 | M_REMU_3I, |
||
1448 | M_DROL, |
||
1449 | M_ROL, |
||
1450 | M_DROL_I, |
||
1451 | M_ROL_I, |
||
1452 | M_DROR, |
||
1453 | M_ROR, |
||
1454 | M_DROR_I, |
||
1455 | M_ROR_I, |
||
1456 | M_S_DA, |
||
1457 | M_S_DAB, |
||
1458 | M_S_S, |
||
1459 | M_SAA_AB, |
||
1460 | M_SAAD_AB, |
||
1461 | M_SC_AB, |
||
1462 | M_SCD_AB, |
||
1463 | M_SCE_AB, |
||
1464 | M_SD_AB, |
||
1465 | M_SDC1_AB, |
||
1466 | M_SDC2_AB, |
||
1467 | M_SQC2_AB, |
||
1468 | M_SDC3_AB, |
||
1469 | M_SDL_AB, |
||
1470 | M_SDM_AB, |
||
1471 | M_SDP_AB, |
||
1472 | M_SDR_AB, |
||
1473 | M_SEQ, |
||
1474 | M_SEQ_I, |
||
1475 | M_SGE, |
||
1476 | M_SGE_I, |
||
1477 | M_SGEU, |
||
1478 | M_SGEU_I, |
||
1479 | M_SGT, |
||
1480 | M_SGT_I, |
||
1481 | M_SGTU, |
||
1482 | M_SGTU_I, |
||
1483 | M_SLE, |
||
1484 | M_SLE_I, |
||
1485 | M_SLEU, |
||
1486 | M_SLEU_I, |
||
1487 | M_SLT_I, |
||
1488 | M_SLTU_I, |
||
1489 | M_SNE, |
||
1490 | M_SNE_I, |
||
1491 | M_SB_AB, |
||
1492 | M_SBE_AB, |
||
1493 | M_SH_AB, |
||
1494 | M_SHE_AB, |
||
1495 | M_SQ_AB, |
||
1496 | M_SW_AB, |
||
1497 | M_SWE_AB, |
||
1498 | M_SWC0_AB, |
||
1499 | M_SWC1_AB, |
||
1500 | M_SWC2_AB, |
||
1501 | M_SWC3_AB, |
||
1502 | M_SWL_AB, |
||
1503 | M_SWLE_AB, |
||
1504 | M_SWM_AB, |
||
1505 | M_SWP_AB, |
||
1506 | M_SWR_AB, |
||
1507 | M_SWRE_AB, |
||
1508 | M_SUB_I, |
||
1509 | M_SUBU_I, |
||
1510 | M_SUBU_I_2, |
||
1511 | M_TEQ_I, |
||
1512 | M_TGE_I, |
||
1513 | M_TGEU_I, |
||
1514 | M_TLT_I, |
||
1515 | M_TLTU_I, |
||
1516 | M_TNE_I, |
||
1517 | M_TRUNCWD, |
||
1518 | M_TRUNCWS, |
||
1519 | M_ULD_AB, |
||
1520 | M_ULH_AB, |
||
1521 | M_ULHU_AB, |
||
1522 | M_ULW_AB, |
||
1523 | M_USH_AB, |
||
1524 | M_USW_AB, |
||
1525 | M_USD_AB, |
||
1526 | M_XOR_I, |
||
1527 | M_COP0, |
||
1528 | M_COP1, |
||
1529 | M_COP2, |
||
1530 | M_COP3, |
||
1531 | M_NUM_MACROS |
||
1532 | }; |
||
1533 | |||
1534 | |||
1535 | /* The order of overloaded instructions matters. Label arguments and |
||
1536 | register arguments look the same. Instructions that can have either |
||
1537 | for arguments must apear in the correct order in this table for the |
||
1538 | assembler to pick the right one. In other words, entries with |
||
1539 | immediate operands must apear after the same instruction with |
||
1540 | registers. |
||
1541 | |||
1542 | Many instructions are short hand for other instructions (i.e., The |
||
1543 | jal |
||
1544 | |||
1545 | extern const struct mips_operand mips_vu0_channel_mask; |
||
1546 | extern const struct mips_operand *decode_mips_operand (const char *); |
||
1547 | extern const struct mips_opcode mips_builtin_opcodes[]; |
||
1548 | extern const int bfd_mips_num_builtin_opcodes; |
||
1549 | extern struct mips_opcode *mips_opcodes; |
||
1550 | extern int bfd_mips_num_opcodes; |
||
1551 | #define NUMOPCODES bfd_mips_num_opcodes |
||
1552 | |||
1553 | |||
1554 | /* The rest of this file adds definitions for the mips16 TinyRISC |
||
1555 | processor. */ |
||
1556 | |||
1557 | /* These are the bitmasks and shift counts used for the different |
||
1558 | fields in the instruction formats. Other than OP, no masks are |
||
1559 | provided for the fixed portions of an instruction, since they are |
||
1560 | not needed. |
||
1561 | |||
1562 | The I format uses IMM11. |
||
1563 | |||
1564 | The RI format uses RX and IMM8. |
||
1565 | |||
1566 | The RR format uses RX, and RY. |
||
1567 | |||
1568 | The RRI format uses RX, RY, and IMM5. |
||
1569 | |||
1570 | The RRR format uses RX, RY, and RZ. |
||
1571 | |||
1572 | The RRI_A format uses RX, RY, and IMM4. |
||
1573 | |||
1574 | The SHIFT format uses RX, RY, and SHAMT. |
||
1575 | |||
1576 | The I8 format uses IMM8. |
||
1577 | |||
1578 | The I8_MOVR32 format uses RY and REGR32. |
||
1579 | |||
1580 | The IR_MOV32R format uses REG32R and MOV32Z. |
||
1581 | |||
1582 | The I64 format uses IMM8. |
||
1583 | |||
1584 | The RI64 format uses RY and IMM5. |
||
1585 | */ |
||
1586 | |||
1587 | #define MIPS16OP_MASK_OP 0x1f |
||
1588 | #define MIPS16OP_SH_OP 11 |
||
1589 | #define MIPS16OP_MASK_IMM11 0x7ff |
||
1590 | #define MIPS16OP_SH_IMM11 0 |
||
1591 | #define MIPS16OP_MASK_RX 0x7 |
||
1592 | #define MIPS16OP_SH_RX 8 |
||
1593 | #define MIPS16OP_MASK_IMM8 0xff |
||
1594 | #define MIPS16OP_SH_IMM8 0 |
||
1595 | #define MIPS16OP_MASK_RY 0x7 |
||
1596 | #define MIPS16OP_SH_RY 5 |
||
1597 | #define MIPS16OP_MASK_IMM5 0x1f |
||
1598 | #define MIPS16OP_SH_IMM5 0 |
||
1599 | #define MIPS16OP_MASK_RZ 0x7 |
||
1600 | #define MIPS16OP_SH_RZ 2 |
||
1601 | #define MIPS16OP_MASK_IMM4 0xf |
||
1602 | #define MIPS16OP_SH_IMM4 0 |
||
1603 | #define MIPS16OP_MASK_REGR32 0x1f |
||
1604 | #define MIPS16OP_SH_REGR32 0 |
||
1605 | #define MIPS16OP_MASK_REG32R 0x1f |
||
1606 | #define MIPS16OP_SH_REG32R 3 |
||
1607 | #define MIPS16OP_EXTRACT_REG32R(i) ((((i) >> 5) & 7) | ((i) & 0x18)) |
||
1608 | #define MIPS16OP_MASK_MOVE32Z 0x7 |
||
1609 | #define MIPS16OP_SH_MOVE32Z 0 |
||
1610 | #define MIPS16OP_MASK_IMM6 0x3f |
||
1611 | #define MIPS16OP_SH_IMM6 5 |
||
1612 | |||
1613 | /* These are the characters which may appears in the args field of a MIPS16 |
||
1614 | instruction. They appear in the order in which the fields appear when the |
||
1615 | instruction is used. Commas and parentheses in the args string are ignored |
||
1616 | when assembling, and written into the output when disassembling. |
||
1617 | |||
1618 | "y" 3 bit register (MIPS16OP_*_RY) |
||
1619 | "x" 3 bit register (MIPS16OP_*_RX) |
||
1620 | "z" 3 bit register (MIPS16OP_*_RZ) |
||
1621 | "Z" 3 bit register (MIPS16OP_*_MOVE32Z) |
||
1622 | "v" 3 bit same register as source and destination (MIPS16OP_*_RX) |
||
1623 | "w" 3 bit same register as source and destination (MIPS16OP_*_RY) |
||
1624 | "0" zero register ($0) |
||
1625 | "S" stack pointer ($sp or $29) |
||
1626 | "P" program counter |
||
1627 | "R" return address register ($ra or $31) |
||
1628 | "X" 5 bit MIPS register (MIPS16OP_*_REGR32) |
||
1629 | "Y" 5 bit MIPS register (MIPS16OP_*_REG32R) |
||
1630 | "6" 6 bit unsigned break code (MIPS16OP_*_IMM6) |
||
1631 | "a" 26 bit jump address |
||
1632 | "i" likewise, but flips bit 0 |
||
1633 | "e" 11 bit extension value |
||
1634 | "l" register list for entry instruction |
||
1635 | "L" register list for exit instruction |
||
1636 | |||
1637 | "I" an immediate value used for macros |
||
1638 | |||
1639 | The remaining codes may be extended. Except as otherwise noted, |
||
1640 | the full extended operand is a 16 bit signed value. |
||
1641 | "<" 3 bit unsigned shift count * 0 (MIPS16OP_*_RZ) (full 5 bit unsigned) |
||
1642 | ">" 3 bit unsigned shift count * 0 (MIPS16OP_*_RX) (full 5 bit unsigned) |
||
1643 | "[" 3 bit unsigned shift count * 0 (MIPS16OP_*_RZ) (full 6 bit unsigned) |
||
1644 | "]" 3 bit unsigned shift count * 0 (MIPS16OP_*_RX) (full 6 bit unsigned) |
||
1645 | "4" 4 bit signed immediate * 0 (MIPS16OP_*_IMM4) (full 15 bit signed) |
||
1646 | "5" 5 bit unsigned immediate * 0 (MIPS16OP_*_IMM5) |
||
1647 | "H" 5 bit unsigned immediate * 2 (MIPS16OP_*_IMM5) |
||
1648 | "W" 5 bit unsigned immediate * 4 (MIPS16OP_*_IMM5) |
||
1649 | "D" 5 bit unsigned immediate * 8 (MIPS16OP_*_IMM5) |
||
1650 | "j" 5 bit signed immediate * 0 (MIPS16OP_*_IMM5) |
||
1651 | "8" 8 bit unsigned immediate * 0 (MIPS16OP_*_IMM8) |
||
1652 | "V" 8 bit unsigned immediate * 4 (MIPS16OP_*_IMM8) |
||
1653 | "C" 8 bit unsigned immediate * 8 (MIPS16OP_*_IMM8) |
||
1654 | "U" 8 bit unsigned immediate * 0 (MIPS16OP_*_IMM8) (full 16 bit unsigned) |
||
1655 | "k" 8 bit signed immediate * 0 (MIPS16OP_*_IMM8) |
||
1656 | "K" 8 bit signed immediate * 8 (MIPS16OP_*_IMM8) |
||
1657 | "p" 8 bit conditional branch address (MIPS16OP_*_IMM8) |
||
1658 | "q" 11 bit branch address (MIPS16OP_*_IMM11) |
||
1659 | "A" 8 bit PC relative address * 4 (MIPS16OP_*_IMM8) |
||
1660 | "B" 5 bit PC relative address * 8 (MIPS16OP_*_IMM5) |
||
1661 | "E" 5 bit PC relative address * 4 (MIPS16OP_*_IMM5) |
||
1662 | "m" 7 bit register list for save instruction (18 bit extended) |
||
1663 | "M" 7 bit register list for restore instruction (18 bit extended) |
||
1664 | */ |
||
1665 | |||
1666 | /* Save/restore encoding for the args field when all 4 registers are |
||
1667 | either saved as arguments or saved/restored as statics. */ |
||
1668 | #define MIPS16_ALL_ARGS 0xe |
||
1669 | #define MIPS16_ALL_STATICS 0xb |
||
1670 | |||
1671 | /* The following flags have the same value for the mips16 opcode |
||
1672 | table: |
||
1673 | |||
1674 | INSN_ISA3 |
||
1675 | |||
1676 | INSN_UNCOND_BRANCH_DELAY |
||
1677 | INSN_COND_BRANCH_DELAY |
||
1678 | INSN_COND_BRANCH_LIKELY (never used) |
||
1679 | INSN_READ_HI |
||
1680 | INSN_READ_LO |
||
1681 | INSN_WRITE_HI |
||
1682 | INSN_WRITE_LO |
||
1683 | INSN_TRAP |
||
1684 | FP_D (never used) |
||
1685 | */ |
||
1686 | |||
1687 | extern const struct mips_operand *decode_mips16_operand (char, bfd_boolean); |
||
1688 | extern const struct mips_opcode mips16_opcodes[]; |
||
1689 | extern const int bfd_mips16_num_opcodes; |
||
1690 | |||
1691 | /* These are the bit masks and shift counts used for the different fields |
||
1692 | in the microMIPS instruction formats. No masks are provided for the |
||
1693 | fixed portions of an instruction, since they are not needed. */ |
||
1694 | |||
1695 | #define MICROMIPSOP_MASK_IMMEDIATE 0xffff |
||
1696 | #define MICROMIPSOP_SH_IMMEDIATE 0 |
||
1697 | #define MICROMIPSOP_MASK_DELTA 0xffff |
||
1698 | #define MICROMIPSOP_SH_DELTA 0 |
||
1699 | #define MICROMIPSOP_MASK_CODE10 0x3ff |
||
1700 | #define MICROMIPSOP_SH_CODE10 16 /* 10-bit wait code. */ |
||
1701 | #define MICROMIPSOP_MASK_TRAP 0xf |
||
1702 | #define MICROMIPSOP_SH_TRAP 12 /* 4-bit trap code. */ |
||
1703 | #define MICROMIPSOP_MASK_SHAMT 0x1f |
||
1704 | #define MICROMIPSOP_SH_SHAMT 11 |
||
1705 | #define MICROMIPSOP_MASK_TARGET 0x3ffffff |
||
1706 | #define MICROMIPSOP_SH_TARGET 0 |
||
1707 | #define MICROMIPSOP_MASK_EXTLSB 0x1f /* "ext" LSB. */ |
||
1708 | #define MICROMIPSOP_SH_EXTLSB 6 |
||
1709 | #define MICROMIPSOP_MASK_EXTMSBD 0x1f /* "ext" MSBD. */ |
||
1710 | #define MICROMIPSOP_SH_EXTMSBD 11 |
||
1711 | #define MICROMIPSOP_MASK_INSMSB 0x1f /* "ins" MSB. */ |
||
1712 | #define MICROMIPSOP_SH_INSMSB 11 |
||
1713 | #define MICROMIPSOP_MASK_CODE 0x3ff |
||
1714 | #define MICROMIPSOP_SH_CODE 16 /* 10-bit higher break code. */ |
||
1715 | #define MICROMIPSOP_MASK_CODE2 0x3ff |
||
1716 | #define MICROMIPSOP_SH_CODE2 6 /* 10-bit lower break code. */ |
||
1717 | #define MICROMIPSOP_MASK_CACHE 0x1f |
||
1718 | #define MICROMIPSOP_SH_CACHE 21 /* 5-bit cache op. */ |
||
1719 | #define MICROMIPSOP_MASK_SEL 0x7 |
||
1720 | #define MICROMIPSOP_SH_SEL 11 |
||
1721 | #define MICROMIPSOP_MASK_OFFSET12 0xfff |
||
1722 | #define MICROMIPSOP_SH_OFFSET12 0 |
||
1723 | #define MICROMIPSOP_MASK_3BITPOS 0x7 |
||
1724 | #define MICROMIPSOP_SH_3BITPOS 21 |
||
1725 | #define MICROMIPSOP_MASK_STYPE 0x1f |
||
1726 | #define MICROMIPSOP_SH_STYPE 16 |
||
1727 | #define MICROMIPSOP_MASK_OFFSET10 0x3ff |
||
1728 | #define MICROMIPSOP_SH_OFFSET10 6 |
||
1729 | #define MICROMIPSOP_MASK_RS 0x1f |
||
1730 | #define MICROMIPSOP_SH_RS 16 |
||
1731 | #define MICROMIPSOP_MASK_RT 0x1f |
||
1732 | #define MICROMIPSOP_SH_RT 21 |
||
1733 | #define MICROMIPSOP_MASK_RD 0x1f |
||
1734 | #define MICROMIPSOP_SH_RD 11 |
||
1735 | #define MICROMIPSOP_MASK_FS 0x1f |
||
1736 | #define MICROMIPSOP_SH_FS 16 |
||
1737 | #define MICROMIPSOP_MASK_FT 0x1f |
||
1738 | #define MICROMIPSOP_SH_FT 21 |
||
1739 | #define MICROMIPSOP_MASK_FD 0x1f |
||
1740 | #define MICROMIPSOP_SH_FD 11 |
||
1741 | #define MICROMIPSOP_MASK_FR 0x1f |
||
1742 | #define MICROMIPSOP_SH_FR 6 |
||
1743 | #define MICROMIPSOP_MASK_RS3 0x1f |
||
1744 | #define MICROMIPSOP_SH_RS3 6 |
||
1745 | #define MICROMIPSOP_MASK_PREFX 0x1f |
||
1746 | #define MICROMIPSOP_SH_PREFX 11 |
||
1747 | #define MICROMIPSOP_MASK_BCC 0x7 |
||
1748 | #define MICROMIPSOP_SH_BCC 18 |
||
1749 | #define MICROMIPSOP_MASK_CCC 0x7 |
||
1750 | #define MICROMIPSOP_SH_CCC 13 |
||
1751 | #define MICROMIPSOP_MASK_COPZ 0x7fffff |
||
1752 | #define MICROMIPSOP_SH_COPZ 3 |
||
1753 | |||
1754 | #define MICROMIPSOP_MASK_MB 0x7 |
||
1755 | #define MICROMIPSOP_SH_MB 23 |
||
1756 | #define MICROMIPSOP_MASK_MC 0x7 |
||
1757 | #define MICROMIPSOP_SH_MC 4 |
||
1758 | #define MICROMIPSOP_MASK_MD 0x7 |
||
1759 | #define MICROMIPSOP_SH_MD 7 |
||
1760 | #define MICROMIPSOP_MASK_ME 0x7 |
||
1761 | #define MICROMIPSOP_SH_ME 1 |
||
1762 | #define MICROMIPSOP_MASK_MF 0x7 |
||
1763 | #define MICROMIPSOP_SH_MF 3 |
||
1764 | #define MICROMIPSOP_MASK_MG 0x7 |
||
1765 | #define MICROMIPSOP_SH_MG 0 |
||
1766 | #define MICROMIPSOP_MASK_MH 0x7 |
||
1767 | #define MICROMIPSOP_SH_MH 7 |
||
1768 | #define MICROMIPSOP_MASK_MJ 0x1f |
||
1769 | #define MICROMIPSOP_SH_MJ 0 |
||
1770 | #define MICROMIPSOP_MASK_ML 0x7 |
||
1771 | #define MICROMIPSOP_SH_ML 4 |
||
1772 | #define MICROMIPSOP_MASK_MM 0x7 |
||
1773 | #define MICROMIPSOP_SH_MM 1 |
||
1774 | #define MICROMIPSOP_MASK_MN 0x7 |
||
1775 | #define MICROMIPSOP_SH_MN 4 |
||
1776 | #define MICROMIPSOP_MASK_MP 0x1f |
||
1777 | #define MICROMIPSOP_SH_MP 5 |
||
1778 | #define MICROMIPSOP_MASK_MQ 0x7 |
||
1779 | #define MICROMIPSOP_SH_MQ 7 |
||
1780 | |||
1781 | #define MICROMIPSOP_MASK_IMMA 0x7f |
||
1782 | #define MICROMIPSOP_SH_IMMA 0 |
||
1783 | #define MICROMIPSOP_MASK_IMMB 0x7 |
||
1784 | #define MICROMIPSOP_SH_IMMB 1 |
||
1785 | #define MICROMIPSOP_MASK_IMMC 0xf |
||
1786 | #define MICROMIPSOP_SH_IMMC 0 |
||
1787 | #define MICROMIPSOP_MASK_IMMD 0x3ff |
||
1788 | #define MICROMIPSOP_SH_IMMD 0 |
||
1789 | #define MICROMIPSOP_MASK_IMME 0x7f |
||
1790 | #define MICROMIPSOP_SH_IMME 0 |
||
1791 | #define MICROMIPSOP_MASK_IMMF 0xf |
||
1792 | #define MICROMIPSOP_SH_IMMF 0 |
||
1793 | #define MICROMIPSOP_MASK_IMMG 0xf |
||
1794 | #define MICROMIPSOP_SH_IMMG 0 |
||
1795 | #define MICROMIPSOP_MASK_IMMH 0xf |
||
1796 | #define MICROMIPSOP_SH_IMMH 0 |
||
1797 | #define MICROMIPSOP_MASK_IMMI 0x7f |
||
1798 | #define MICROMIPSOP_SH_IMMI 0 |
||
1799 | #define MICROMIPSOP_MASK_IMMJ 0xf |
||
1800 | #define MICROMIPSOP_SH_IMMJ 0 |
||
1801 | #define MICROMIPSOP_MASK_IMML 0xf |
||
1802 | #define MICROMIPSOP_SH_IMML 0 |
||
1803 | #define MICROMIPSOP_MASK_IMMM 0x7 |
||
1804 | #define MICROMIPSOP_SH_IMMM 1 |
||
1805 | #define MICROMIPSOP_MASK_IMMN 0x3 |
||
1806 | #define MICROMIPSOP_SH_IMMN 4 |
||
1807 | #define MICROMIPSOP_MASK_IMMO 0xf |
||
1808 | #define MICROMIPSOP_SH_IMMO 0 |
||
1809 | #define MICROMIPSOP_MASK_IMMP 0x1f |
||
1810 | #define MICROMIPSOP_SH_IMMP 0 |
||
1811 | #define MICROMIPSOP_MASK_IMMQ 0x7fffff |
||
1812 | #define MICROMIPSOP_SH_IMMQ 0 |
||
1813 | #define MICROMIPSOP_MASK_IMMU 0x1f |
||
1814 | #define MICROMIPSOP_SH_IMMU 0 |
||
1815 | #define MICROMIPSOP_MASK_IMMW 0x3f |
||
1816 | #define MICROMIPSOP_SH_IMMW 1 |
||
1817 | #define MICROMIPSOP_MASK_IMMX 0xf |
||
1818 | #define MICROMIPSOP_SH_IMMX 1 |
||
1819 | #define MICROMIPSOP_MASK_IMMY 0x1ff |
||
1820 | #define MICROMIPSOP_SH_IMMY 1 |
||
1821 | |||
1822 | /* MIPS DSP ASE */ |
||
1823 | #define MICROMIPSOP_MASK_DSPACC 0x3 |
||
1824 | #define MICROMIPSOP_SH_DSPACC 14 |
||
1825 | #define MICROMIPSOP_MASK_DSPSFT 0x3f |
||
1826 | #define MICROMIPSOP_SH_DSPSFT 16 |
||
1827 | #define MICROMIPSOP_MASK_SA3 0x7 |
||
1828 | #define MICROMIPSOP_SH_SA3 13 |
||
1829 | #define MICROMIPSOP_MASK_SA4 0xf |
||
1830 | #define MICROMIPSOP_SH_SA4 12 |
||
1831 | #define MICROMIPSOP_MASK_IMM8 0xff |
||
1832 | #define MICROMIPSOP_SH_IMM8 13 |
||
1833 | #define MICROMIPSOP_MASK_IMM10 0x3ff |
||
1834 | #define MICROMIPSOP_SH_IMM10 16 |
||
1835 | #define MICROMIPSOP_MASK_WRDSP 0x3f |
||
1836 | #define MICROMIPSOP_SH_WRDSP 14 |
||
1837 | #define MICROMIPSOP_MASK_BP 0x3 |
||
1838 | #define MICROMIPSOP_SH_BP 14 |
||
1839 | |||
1840 | /* Placeholders for fields that only exist in the traditional 32-bit |
||
1841 | instruction encoding; see the comment above for details. */ |
||
1842 | #define MICROMIPSOP_MASK_CODE20 0 |
||
1843 | #define MICROMIPSOP_SH_CODE20 0 |
||
1844 | #define MICROMIPSOP_MASK_PERFREG 0 |
||
1845 | #define MICROMIPSOP_SH_PERFREG 0 |
||
1846 | #define MICROMIPSOP_MASK_CODE19 0 |
||
1847 | #define MICROMIPSOP_SH_CODE19 0 |
||
1848 | #define MICROMIPSOP_MASK_ALN 0 |
||
1849 | #define MICROMIPSOP_SH_ALN 0 |
||
1850 | #define MICROMIPSOP_MASK_VECBYTE 0 |
||
1851 | #define MICROMIPSOP_SH_VECBYTE 0 |
||
1852 | #define MICROMIPSOP_MASK_VECALIGN 0 |
||
1853 | #define MICROMIPSOP_SH_VECALIGN 0 |
||
1854 | #define MICROMIPSOP_MASK_DSPACC_S 0 |
||
1855 | #define MICROMIPSOP_SH_DSPACC_S 0 |
||
1856 | #define MICROMIPSOP_MASK_DSPSFT_7 0 |
||
1857 | #define MICROMIPSOP_SH_DSPSFT_7 0 |
||
1858 | #define MICROMIPSOP_MASK_RDDSP 0 |
||
1859 | #define MICROMIPSOP_SH_RDDSP 0 |
||
1860 | #define MICROMIPSOP_MASK_MT_U 0 |
||
1861 | #define MICROMIPSOP_SH_MT_U 0 |
||
1862 | #define MICROMIPSOP_MASK_MT_H 0 |
||
1863 | #define MICROMIPSOP_SH_MT_H 0 |
||
1864 | #define MICROMIPSOP_MASK_MTACC_T 0 |
||
1865 | #define MICROMIPSOP_SH_MTACC_T 0 |
||
1866 | #define MICROMIPSOP_MASK_MTACC_D 0 |
||
1867 | #define MICROMIPSOP_SH_MTACC_D 0 |
||
1868 | #define MICROMIPSOP_MASK_BBITIND 0 |
||
1869 | #define MICROMIPSOP_SH_BBITIND 0 |
||
1870 | #define MICROMIPSOP_MASK_CINSPOS 0 |
||
1871 | #define MICROMIPSOP_SH_CINSPOS 0 |
||
1872 | #define MICROMIPSOP_MASK_CINSLM1 0 |
||
1873 | #define MICROMIPSOP_SH_CINSLM1 0 |
||
1874 | #define MICROMIPSOP_MASK_SEQI 0 |
||
1875 | #define MICROMIPSOP_SH_SEQI 0 |
||
1876 | #define MICROMIPSOP_SH_OFFSET_A 0 |
||
1877 | #define MICROMIPSOP_MASK_OFFSET_A 0 |
||
1878 | #define MICROMIPSOP_SH_OFFSET_B 0 |
||
1879 | #define MICROMIPSOP_MASK_OFFSET_B 0 |
||
1880 | #define MICROMIPSOP_SH_OFFSET_C 0 |
||
1881 | #define MICROMIPSOP_MASK_OFFSET_C 0 |
||
1882 | #define MICROMIPSOP_SH_RZ 0 |
||
1883 | #define MICROMIPSOP_MASK_RZ 0 |
||
1884 | #define MICROMIPSOP_SH_FZ 0 |
||
1885 | #define MICROMIPSOP_MASK_FZ 0 |
||
1886 | |||
1887 | /* microMIPS Enhanced VA Scheme */ |
||
1888 | #define MICROMIPSOP_SH_EVAOFFSET 0 |
||
1889 | #define MICROMIPSOP_MASK_EVAOFFSET 0x1ff |
||
1890 | |||
1891 | /* These are the characters which may appears in the args field of a microMIPS |
||
1892 | instruction. They appear in the order in which the fields appear |
||
1893 | when the instruction is used. Commas and parentheses in the args |
||
1894 | string are ignored when assembling, and written into the output |
||
1895 | when disassembling. |
||
1896 | |||
1897 | The followings are for 16-bit microMIPS instructions. |
||
1898 | |||
1899 | "ma" must be $28 |
||
1900 | "mc" 3-bit MIPS registers 2-7, 16, 17 (MICROMIPSOP_*_MC) at bit 4 |
||
1901 | The same register used as both source and target. |
||
1902 | "md" 3-bit MIPS registers 2-7, 16, 17 (MICROMIPSOP_*_MD) at bit 7 |
||
1903 | "me" 3-bit MIPS registers 2-7, 16, 17 (MICROMIPSOP_*_ME) at bit 1 |
||
1904 | The same register used as both source and target. |
||
1905 | "mf" 3-bit MIPS registers 2-7, 16, 17 (MICROMIPSOP_*_MF) at bit 3 |
||
1906 | "mg" 3-bit MIPS registers 2-7, 16, 17 (MICROMIPSOP_*_MG) at bit 0 |
||
1907 | "mh" 3-bit MIPS register pair (MICROMIPSOP_*_MH) at bit 7 |
||
1908 | "mj" 5-bit MIPS registers (MICROMIPSOP_*_MJ) at bit 0 |
||
1909 | "ml" 3-bit MIPS registers 2-7, 16, 17 (MICROMIPSOP_*_ML) at bit 4 |
||
1910 | "mm" 3-bit MIPS registers 0, 2, 3, 16-20 (MICROMIPSOP_*_MM) at bit 1 |
||
1911 | "mn" 3-bit MIPS registers 0, 2, 3, 16-20 (MICROMIPSOP_*_MN) at bit 4 |
||
1912 | "mp" 5-bit MIPS registers (MICROMIPSOP_*_MP) at bit 5 |
||
1913 | "mq" 3-bit MIPS registers 0, 2-7, 17 (MICROMIPSOP_*_MQ) at bit 7 |
||
1914 | "mr" must be program counter |
||
1915 | "ms" must be $29 |
||
1916 | "mt" must be the same as the previous register |
||
1917 | "mx" must be the same as the destination register |
||
1918 | "my" must be $31 |
||
1919 | "mz" must be $0 |
||
1920 | |||
1921 | "mA" 7-bit immediate (-64 .. 63) << 2 (MICROMIPSOP_*_IMMA) |
||
1922 | "mB" 3-bit immediate (-1, 1, 4, 8, 12, 16, 20, 24) (MICROMIPSOP_*_IMMB) |
||
1923 | "mC" 4-bit immediate (1, 2, 3, 4, 7, 8, 15, 16, 31, 32, 63, 64, 128, 255, |
||
1924 | 32768, 65535) (MICROMIPSOP_*_IMMC) |
||
1925 | "mD" 10-bit branch address (-512 .. 511) << 1 (MICROMIPSOP_*_IMMD) |
||
1926 | "mE" 7-bit branch address (-64 .. 63) << 1 (MICROMIPSOP_*_IMME) |
||
1927 | "mF" 4-bit immediate (0 .. 15) (MICROMIPSOP_*_IMMF) |
||
1928 | "mG" 4-bit immediate (-1 .. 14) (MICROMIPSOP_*_IMMG) |
||
1929 | "mH" 4-bit immediate (0 .. 15) << 1 (MICROMIPSOP_*_IMMH) |
||
1930 | "mI" 7-bit immediate (-1 .. 126) (MICROMIPSOP_*_IMMI) |
||
1931 | "mJ" 4-bit immediate (0 .. 15) << 2 (MICROMIPSOP_*_IMMJ) |
||
1932 | "mL" 4-bit immediate (0 .. 15) (MICROMIPSOP_*_IMML) |
||
1933 | "mM" 3-bit immediate (1 .. 8) (MICROMIPSOP_*_IMMM) |
||
1934 | "mN" 2-bit immediate (0 .. 3) for register list (MICROMIPSOP_*_IMMN) |
||
1935 | "mO" 4-bit immediate (0 .. 15) (MICROMIPSOP_*_IMML) |
||
1936 | "mP" 5-bit immediate (0 .. 31) << 2 (MICROMIPSOP_*_IMMP) |
||
1937 | "mU" 5-bit immediate (0 .. 31) << 2 (MICROMIPSOP_*_IMMU) |
||
1938 | "mW" 6-bit immediate (0 .. 63) << 2 (MICROMIPSOP_*_IMMW) |
||
1939 | "mX" 4-bit immediate (-8 .. 7) (MICROMIPSOP_*_IMMX) |
||
1940 | "mY" 9-bit immediate (-258 .. -3, 2 .. 257) << 2 (MICROMIPSOP_*_IMMY) |
||
1941 | "mZ" must be zero |
||
1942 | |||
1943 | In most cases 32-bit microMIPS instructions use the same characters |
||
1944 | as MIPS (with ADDIUPC being a notable exception, but there are some |
||
1945 | others too). |
||
1946 | |||
1947 | "." 10-bit signed offset/number (MICROMIPSOP_*_OFFSET10) |
||
1948 | "1" 5-bit sync type (MICROMIPSOP_*_STYPE) |
||
1949 | "<" 5-bit shift amount (MICROMIPSOP_*_SHAMT) |
||
1950 | ">" shift amount between 32 and 63, stored after subtracting 32 |
||
1951 | (MICROMIPSOP_*_SHAMT) |
||
1952 | "\" 3-bit position for ASET and ACLR (MICROMIPSOP_*_3BITPOS) |
||
1953 | "|" 4-bit trap code (MICROMIPSOP_*_TRAP) |
||
1954 | "~" 12-bit signed offset (MICROMIPSOP_*_OFFSET12) |
||
1955 | "a" 26-bit target address (MICROMIPSOP_*_TARGET) |
||
1956 | "+i" likewise, but flips bit 0 |
||
1957 | "b" 5-bit base register (MICROMIPSOP_*_RS) |
||
1958 | "c" 10-bit higher breakpoint code (MICROMIPSOP_*_CODE) |
||
1959 | "d" 5-bit destination register specifier (MICROMIPSOP_*_RD) |
||
1960 | "h" 5-bit PREFX hint (MICROMIPSOP_*_PREFX) |
||
1961 | "i" 16-bit unsigned immediate (MICROMIPSOP_*_IMMEDIATE) |
||
1962 | "j" 16-bit signed immediate (MICROMIPSOP_*_DELTA) |
||
1963 | "k" 5-bit cache opcode in target register position (MICROMIPSOP_*_CACHE) |
||
1964 | "n" register list for 32-bit LWM/SWM instruction (MICROMIPSOP_*_RT) |
||
1965 | "o" 16-bit signed offset (MICROMIPSOP_*_DELTA) |
||
1966 | "p" 16-bit PC-relative branch target address (MICROMIPSOP_*_DELTA) |
||
1967 | "q" 10-bit lower breakpoint code (MICROMIPSOP_*_CODE2) |
||
1968 | "r" 5-bit same register used as both source and target (MICROMIPSOP_*_RS) |
||
1969 | "s" 5-bit source register specifier (MICROMIPSOP_*_RS) |
||
1970 | "t" 5-bit target register (MICROMIPSOP_*_RT) |
||
1971 | "u" 16-bit upper 16 bits of address (MICROMIPSOP_*_IMMEDIATE) |
||
1972 | "v" 5-bit same register used as both source and destination |
||
1973 | (MICROMIPSOP_*_RS) |
||
1974 | "w" 5-bit same register used as both target and destination |
||
1975 | (MICROMIPSOP_*_RT) |
||
1976 | "y" 5-bit source 3 register for ALNV.PS (MICROMIPSOP_*_RS3) |
||
1977 | "z" must be zero register |
||
1978 | "C" 23-bit coprocessor function code (MICROMIPSOP_*_COPZ) |
||
1979 | "B" 10-bit syscall/wait function code (MICROMIPSOP_*_CODE10) |
||
1980 | "K" 5-bit Hardware Register (RDHWR instruction) (MICROMIPSOP_*_RS) |
||
1981 | |||
1982 | "+A" 5-bit INS/EXT/DINS/DEXT/DINSM/DEXTM position, which becomes |
||
1983 | LSB (MICROMIPSOP_*_EXTLSB). |
||
1984 | Enforces: 0 <= pos < 32. |
||
1985 | "+B" 5-bit INS/DINS size, which becomes MSB (MICROMIPSOP_*_INSMSB). |
||
1986 | Requires that "+A" or "+E" occur first to set position. |
||
1987 | Enforces: 0 < (pos+size) <= 32. |
||
1988 | "+C" 5-bit EXT/DEXT size, which becomes MSBD (MICROMIPSOP_*_EXTMSBD). |
||
1989 | Requires that "+A" or "+E" occur first to set position. |
||
1990 | Enforces: 0 < (pos+size) <= 32. |
||
1991 | (Also used by DEXT w/ different limits, but limits for |
||
1992 | that are checked by the M_DEXT macro.) |
||
1993 | "+E" 5-bit DINSU/DEXTU position, which becomes LSB-32 (MICROMIPSOP_*_EXTLSB). |
||
1994 | Enforces: 32 <= pos < 64. |
||
1995 | "+F" 5-bit DINSM/DINSU size, which becomes MSB-32 (MICROMIPSOP_*_INSMSB). |
||
1996 | Requires that "+A" or "+E" occur first to set position. |
||
1997 | Enforces: 32 < (pos+size) <= 64. |
||
1998 | "+G" 5-bit DEXTM size, which becomes MSBD-32 (MICROMIPSOP_*_EXTMSBD). |
||
1999 | Requires that "+A" or "+E" occur first to set position. |
||
2000 | Enforces: 32 < (pos+size) <= 64. |
||
2001 | "+H" 5-bit DEXTU size, which becomes MSBD (MICROMIPSOP_*_EXTMSBD). |
||
2002 | Requires that "+A" or "+E" occur first to set position. |
||
2003 | Enforces: 32 < (pos+size) <= 64. |
||
2004 | |||
2005 | PC-relative addition (ADDIUPC) instruction: |
||
2006 | "mQ" 23-bit offset (-4194304 .. 4194303) << 2 (MICROMIPSOP_*_IMMQ) |
||
2007 | "mb" 3-bit MIPS registers 2-7, 16, 17 (MICROMIPSOP_*_MB) at bit 23 |
||
2008 | |||
2009 | Floating point instructions: |
||
2010 | "D" 5-bit destination register (MICROMIPSOP_*_FD) |
||
2011 | "M" 3-bit compare condition code (MICROMIPSOP_*_CCC) |
||
2012 | "N" 3-bit branch condition code (MICROMIPSOP_*_BCC) |
||
2013 | "R" 5-bit fr source 3 register (MICROMIPSOP_*_FR) |
||
2014 | "S" 5-bit fs source 1 register (MICROMIPSOP_*_FS) |
||
2015 | "T" 5-bit ft source 2 register (MICROMIPSOP_*_FT) |
||
2016 | "V" 5-bit same register used as floating source and destination or target |
||
2017 | (MICROMIPSOP_*_FS) |
||
2018 | |||
2019 | Coprocessor instructions: |
||
2020 | "E" 5-bit target register (MICROMIPSOP_*_RT) |
||
2021 | "G" 5-bit source register (MICROMIPSOP_*_RS) |
||
2022 | "H" 3-bit sel field for (D)MTC* and (D)MFC* (MICROMIPSOP_*_SEL) |
||
2023 | |||
2024 | Macro instructions: |
||
2025 | "A" general 32 bit expression |
||
2026 | "I" 32-bit immediate (value placed in imm_expr). |
||
2027 | "F" 64-bit floating point constant in .rdata |
||
2028 | "L" 64-bit floating point constant in .lit8 |
||
2029 | "f" 32-bit floating point constant |
||
2030 | "l" 32-bit floating point constant in .lit4 |
||
2031 | |||
2032 | DSP ASE usage: |
||
2033 | "2" 2-bit unsigned immediate for byte align (MICROMIPSOP_*_BP) |
||
2034 | "3" 3-bit unsigned immediate (MICROMIPSOP_*_SA3) |
||
2035 | "4" 4-bit unsigned immediate (MICROMIPSOP_*_SA4) |
||
2036 | "5" 8-bit unsigned immediate (MICROMIPSOP_*_IMM8) |
||
2037 | "6" 5-bit unsigned immediate (MICROMIPSOP_*_RS) |
||
2038 | "7" 2-bit DSP accumulator register (MICROMIPSOP_*_DSPACC) |
||
2039 | "8" 6-bit unsigned immediate (MICROMIPSOP_*_WRDSP) |
||
2040 | "0" 6-bit signed immediate (MICROMIPSOP_*_DSPSFT) |
||
2041 | "@" 10-bit signed immediate (MICROMIPSOP_*_IMM10) |
||
2042 | "^" 5-bit unsigned immediate (MICROMIPSOP_*_RD) |
||
2043 | |||
2044 | microMIPS Enhanced VA Scheme: |
||
2045 | "+j" 9-bit signed offset in bit 0 (OP_*_EVAOFFSET) |
||
2046 | |||
2047 | Other: |
||
2048 | "()" parens surrounding optional value |
||
2049 | "," separates operands |
||
2050 | "+" start of extension sequence |
||
2051 | "m" start of microMIPS extension sequence |
||
2052 | |||
2053 | Characters used so far, for quick reference when adding more: |
||
2054 | "12345678 0" |
||
2055 | "<>(),+.@\^|~" |
||
2056 | "ABCDEFGHI KLMN RST V " |
||
2057 | "abcd f hijklmnopqrstuvw yz" |
||
2058 | |||
2059 | Extension character sequences used so far ("+" followed by the |
||
2060 | following), for quick reference when adding more: |
||
2061 | "" |
||
2062 | "" |
||
2063 | "ABCEFGH" |
||
2064 | "ij" |
||
2065 | |||
2066 | Extension character sequences used so far ("m" followed by the |
||
2067 | following), for quick reference when adding more: |
||
2068 | "" |
||
2069 | "" |
||
2070 | " BCDEFGHIJ LMNOPQ U WXYZ" |
||
2071 | " bcdefghij lmn pq st xyz" |
||
2072 | */ |
||
2073 | |||
2074 | extern const struct mips_operand *decode_micromips_operand (const char *); |
||
2075 | extern const struct mips_opcode micromips_opcodes[]; |
||
2076 | extern const int bfd_micromips_num_opcodes; |
||
2077 | |||
2078 | /* A NOP insn impemented as "or at,at,zero". |
||
2079 | Used to implement -mfix-loongson2f. */ |
||
2080 | #define LOONGSON2F_NOP_INSN 0x00200825 |
||
2081 | |||
2082 | #endif /* _MIPS_H_ */>><>=>>=>>=>>>=>=>>=>>>=>">><>><>><>><>><>><>><>><>><>">>=>=>>=>>=>>=>>=>>=>=>>=>>=>>>=>=>>=>>>=>">><>><>><>><>=><=>><>><>><>><>><>><>><>><>><>><>><>><> |