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Rev | Author | Line No. | Line |
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5191 | serge | 1 | /* opcode/i386.h -- Intel 80386 opcode macros |
6324 | serge | 2 | Copyright (C) 1989-2015 Free Software Foundation, Inc. |
5191 | serge | 3 | |
4 | This file is part of GAS, the GNU Assembler, and GDB, the GNU Debugger. |
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5 | |||
6 | This program is free software; you can redistribute it and/or modify |
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7 | it under the terms of the GNU General Public License as published by |
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8 | the Free Software Foundation; either version 3 of the License, or |
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9 | (at your option) any later version. |
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10 | |||
11 | This program is distributed in the hope that it will be useful, |
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12 | but WITHOUT ANY WARRANTY; without even the implied warranty of |
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13 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
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14 | GNU General Public License for more details. |
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15 | |||
16 | You should have received a copy of the GNU General Public License |
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17 | along with this program; if not, write to the Free Software |
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18 | Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, |
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19 | MA 02110-1301, USA. */ |
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20 | |||
21 | /* The SystemV/386 SVR3.2 assembler, and probably all AT&T derived |
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22 | ix86 Unix assemblers, generate floating point instructions with |
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23 | reversed source and destination registers in certain cases. |
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24 | Unfortunately, gcc and possibly many other programs use this |
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25 | reversed syntax, so we're stuck with it. |
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26 | |||
27 | eg. `fsub %st(3),%st' results in st = st - st(3) as expected, but |
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28 | `fsub %st,%st(3)' results in st(3) = st - st(3), rather than |
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29 | the expected st(3) = st(3) - st |
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30 | |||
31 | This happens with all the non-commutative arithmetic floating point |
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32 | operations with two register operands, where the source register is |
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33 | %st, and destination register is %st(i). |
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34 | |||
35 | The affected opcode map is dceX, dcfX, deeX, defX. */ |
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36 | |||
37 | #ifndef OPCODE_I386_H |
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38 | #define OPCODE_I386_H |
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39 | |||
40 | #ifndef SYSV386_COMPAT |
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41 | /* Set non-zero for broken, compatible instructions. Set to zero for |
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42 | non-broken opcodes at your peril. gcc generates SystemV/386 |
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43 | compatible instructions. */ |
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44 | #define SYSV386_COMPAT 1 |
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45 | #endif |
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46 | #ifndef OLDGCC_COMPAT |
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47 | /* Set non-zero to cater for old (<= 2.8.1) versions of gcc that could |
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48 | generate nonsense fsubp, fsubrp, fdivp and fdivrp with operands |
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49 | reversed. */ |
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50 | #define OLDGCC_COMPAT SYSV386_COMPAT |
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51 | #endif |
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52 | |||
53 | #define MOV_AX_DISP32 0xa0 |
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54 | #define POP_SEG_SHORT 0x07 |
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55 | #define JUMP_PC_RELATIVE 0xeb |
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56 | #define INT_OPCODE 0xcd |
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57 | #define INT3_OPCODE 0xcc |
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58 | /* The opcode for the fwait instruction, which disassembler treats as a |
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59 | prefix when it can. */ |
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60 | #define FWAIT_OPCODE 0x9b |
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61 | |||
62 | /* Instruction prefixes. |
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63 | NOTE: For certain SSE* instructions, 0x66,0xf2,0xf3 are treated as |
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64 | part of the opcode. Other prefixes may still appear between them |
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65 | and the 0x0f part of the opcode. */ |
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66 | #define ADDR_PREFIX_OPCODE 0x67 |
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67 | #define DATA_PREFIX_OPCODE 0x66 |
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68 | #define LOCK_PREFIX_OPCODE 0xf0 |
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69 | #define CS_PREFIX_OPCODE 0x2e |
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70 | #define DS_PREFIX_OPCODE 0x3e |
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71 | #define ES_PREFIX_OPCODE 0x26 |
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72 | #define FS_PREFIX_OPCODE 0x64 |
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73 | #define GS_PREFIX_OPCODE 0x65 |
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74 | #define SS_PREFIX_OPCODE 0x36 |
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75 | #define REPNE_PREFIX_OPCODE 0xf2 |
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76 | #define REPE_PREFIX_OPCODE 0xf3 |
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77 | #define XACQUIRE_PREFIX_OPCODE 0xf2 |
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78 | #define XRELEASE_PREFIX_OPCODE 0xf3 |
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79 | #define BND_PREFIX_OPCODE 0xf2 |
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80 | |||
81 | #define TWO_BYTE_OPCODE_ESCAPE 0x0f |
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82 | #define NOP_OPCODE (char) 0x90 |
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83 | |||
84 | /* register numbers */ |
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85 | #define EAX_REG_NUM 0 |
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86 | #define ECX_REG_NUM 1 |
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87 | #define EDX_REG_NUM 2 |
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88 | #define EBX_REG_NUM 3 |
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89 | #define ESP_REG_NUM 4 |
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90 | #define EBP_REG_NUM 5 |
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91 | #define ESI_REG_NUM 6 |
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92 | #define EDI_REG_NUM 7 |
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93 | |||
94 | /* modrm_byte.regmem for twobyte escape */ |
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95 | #define ESCAPE_TO_TWO_BYTE_ADDRESSING ESP_REG_NUM |
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96 | /* index_base_byte.index for no index register addressing */ |
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97 | #define NO_INDEX_REGISTER ESP_REG_NUM |
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98 | /* index_base_byte.base for no base register addressing */ |
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99 | #define NO_BASE_REGISTER EBP_REG_NUM |
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100 | #define NO_BASE_REGISTER_16 6 |
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101 | |||
102 | /* modrm.mode = REGMEM_FIELD_HAS_REG when a register is in there */ |
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103 | #define REGMEM_FIELD_HAS_REG 0x3/* always = 0x3 */ |
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104 | #define REGMEM_FIELD_HAS_MEM (~REGMEM_FIELD_HAS_REG) |
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105 | |||
106 | /* Extract fields from the mod/rm byte. */ |
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107 | #define MODRM_MOD_FIELD(modrm) (((modrm) >> 6) & 3) |
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108 | #define MODRM_REG_FIELD(modrm) (((modrm) >> 3) & 7) |
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109 | #define MODRM_RM_FIELD(modrm) (((modrm) >> 0) & 7) |
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110 | |||
111 | /* Extract fields from the sib byte. */ |
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112 | #define SIB_SCALE_FIELD(sib) (((sib) >> 6) & 3) |
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113 | #define SIB_INDEX_FIELD(sib) (((sib) >> 3) & 7) |
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114 | #define SIB_BASE_FIELD(sib) (((sib) >> 0) & 7) |
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115 | |||
116 | /* x86-64 extension prefix. */ |
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117 | #define REX_OPCODE 0x40 |
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118 | |||
119 | /* Non-zero if OPCODE is the rex prefix. */ |
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120 | #define REX_PREFIX_P(opcode) (((opcode) & 0xf0) == REX_OPCODE) |
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121 | |||
122 | /* Indicates 64 bit operand size. */ |
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123 | #define REX_W 8 |
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124 | /* High extension to reg field of modrm byte. */ |
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125 | #define REX_R 4 |
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126 | /* High extension to SIB index field. */ |
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127 | #define REX_X 2 |
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128 | /* High extension to base field of modrm or SIB, or reg field of opcode. */ |
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129 | #define REX_B 1 |
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130 | |||
131 | /* max operands per insn */ |
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132 | #define MAX_OPERANDS 5 |
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133 | |||
134 | /* max immediates per insn (lcall, ljmp, insertq, extrq) */ |
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135 | #define MAX_IMMEDIATE_OPERANDS 2 |
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136 | |||
137 | /* max memory refs per insn (string ops) */ |
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138 | #define MAX_MEMORY_OPERANDS 2 |
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139 | |||
140 | /* max size of insn mnemonics. */ |
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141 | #define MAX_MNEM_SIZE 20 |
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142 | |||
143 | /* max size of register name in insn mnemonics. */ |
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144 | #define MAX_REG_NAME_SIZE 8 |
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145 | |||
146 | #endif /* OPCODE_I386_H */=> |