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5191 | serge | 1 | /* i370.h -- Header file for S/390 opcode table |
6324 | serge | 2 | Copyright (C) 1994-2015 Free Software Foundation, Inc. |
5191 | serge | 3 | PowerPC version written by Ian Lance Taylor, Cygnus Support |
4 | Rewritten for i370 ESA/390 support, Linas Vepstas |
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5 | |||
6 | This file is part of GDB, GAS, and the GNU binutils. |
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7 | |||
8 | GDB, GAS, and the GNU binutils are free software; you can redistribute |
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9 | them and/or modify them under the terms of the GNU General Public |
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10 | License as published by the Free Software Foundation; either version 3, |
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11 | or (at your option) any later version. |
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12 | |||
13 | GDB, GAS, and the GNU binutils are distributed in the hope that they |
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14 | will be useful, but WITHOUT ANY WARRANTY; without even the implied |
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15 | warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See |
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16 | the GNU General Public License for more details. |
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17 | |||
18 | You should have received a copy of the GNU General Public License |
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19 | along with this file; see the file COPYING3. If not, write to the Free |
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20 | Software Foundation, 51 Franklin Street - Fifth Floor, Boston, |
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21 | MA 02110-1301, USA. */ |
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22 | |||
23 | #ifndef I370_H |
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24 | #define I370_H |
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25 | |||
26 | /* The opcode table is an array of struct i370_opcode. */ |
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27 | typedef union |
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28 | { |
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29 | unsigned int i[2]; |
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30 | unsigned short s[4]; |
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31 | unsigned char b[8]; |
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32 | } i370_insn_t; |
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33 | |||
34 | struct i370_opcode |
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35 | { |
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36 | /* The opcode name. */ |
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37 | const char *name; |
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38 | |||
39 | /* the length of the instruction */ |
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40 | char len; |
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41 | |||
42 | /* The opcode itself. Those bits which will be filled in with |
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43 | operands are zeroes. */ |
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44 | i370_insn_t opcode; |
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45 | |||
46 | /* The opcode mask. This is used by the disassembler. This is a |
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47 | mask containing ones indicating those bits which must match the |
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48 | opcode field, and zeroes indicating those bits which need not |
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49 | match (and are presumably filled in by operands). */ |
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50 | i370_insn_t mask; |
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51 | |||
52 | /* One bit flags for the opcode. These are used to indicate which |
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53 | specific processors support the instructions. The defined values |
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54 | are listed below. */ |
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55 | unsigned long flags; |
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56 | |||
57 | /* An array of operand codes. Each code is an index into the |
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58 | operand table. They appear in the order which the operands must |
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59 | appear in assembly code, and are terminated by a zero. */ |
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60 | unsigned char operands[8]; |
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61 | }; |
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62 | |||
63 | /* The table itself is sorted by major opcode number, and is otherwise |
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64 | in the order in which the disassembler should consider |
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65 | instructions. */ |
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66 | extern const struct i370_opcode i370_opcodes[]; |
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67 | extern const int i370_num_opcodes; |
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68 | |||
69 | /* Values defined for the flags field of a struct i370_opcode. */ |
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70 | |||
71 | /* Opcode is defined for the original 360 architecture. */ |
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72 | #define I370_OPCODE_360 (0x01) |
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73 | |||
74 | /* Opcode is defined for the 370 architecture. */ |
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75 | #define I370_OPCODE_370 (0x02) |
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76 | |||
77 | /* Opcode is defined for the 370-XA architecture. */ |
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78 | #define I370_OPCODE_370_XA (0x04) |
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79 | |||
80 | /* Opcode is defined for the ESA/370 architecture. */ |
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81 | #define I370_OPCODE_ESA370 (0x08) |
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82 | |||
83 | /* Opcode is defined for the ESA/390 architecture. */ |
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84 | #define I370_OPCODE_ESA390 (0x10) |
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85 | |||
86 | /* Opcode is defined for the ESA/390 w/ BFP facility. */ |
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87 | #define I370_OPCODE_ESA390_BF (0x20) |
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88 | |||
89 | /* Opcode is defined for the ESA/390 w/ branch & set authority facility. */ |
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90 | #define I370_OPCODE_ESA390_BS (0x40) |
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91 | |||
92 | /* Opcode is defined for the ESA/390 w/ checksum facility. */ |
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93 | #define I370_OPCODE_ESA390_CK (0x80) |
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94 | |||
95 | /* Opcode is defined for the ESA/390 w/ compare & move extended facility. */ |
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96 | #define I370_OPCODE_ESA390_CM (0x100) |
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97 | |||
98 | /* Opcode is defined for the ESA/390 w/ flt.pt. support extensions facility. */ |
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99 | #define I370_OPCODE_ESA390_FX (0x200) |
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100 | |||
101 | /* Opcode is defined for the ESA/390 w/ HFP facility. */ |
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102 | #define I370_OPCODE_ESA390_HX (0x400) |
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103 | |||
104 | /* Opcode is defined for the ESA/390 w/ immediate & relative facility. */ |
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105 | #define I370_OPCODE_ESA390_IR (0x800) |
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106 | |||
107 | /* Opcode is defined for the ESA/390 w/ move-inverse facility. */ |
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108 | #define I370_OPCODE_ESA390_MI (0x1000) |
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109 | |||
110 | /* Opcode is defined for the ESA/390 w/ program-call-fast facility. */ |
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111 | #define I370_OPCODE_ESA390_PC (0x2000) |
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112 | |||
113 | /* Opcode is defined for the ESA/390 w/ perform-locked-op facility. */ |
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114 | #define I370_OPCODE_ESA390_PL (0x4000) |
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115 | |||
116 | /* Opcode is defined for the ESA/390 w/ square-root facility. */ |
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117 | #define I370_OPCODE_ESA390_QR (0x8000) |
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118 | |||
119 | /* Opcode is defined for the ESA/390 w/ resume-program facility. */ |
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120 | #define I370_OPCODE_ESA390_RP (0x10000) |
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121 | |||
122 | /* Opcode is defined for the ESA/390 w/ set-address-space-fast facility. */ |
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123 | #define I370_OPCODE_ESA390_SA (0x20000) |
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124 | |||
125 | /* Opcode is defined for the ESA/390 w/ subspace group facility. */ |
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126 | #define I370_OPCODE_ESA390_SG (0x40000) |
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127 | |||
128 | /* Opcode is defined for the ESA/390 w/ string facility. */ |
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129 | #define I370_OPCODE_ESA390_SR (0x80000) |
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130 | |||
131 | /* Opcode is defined for the ESA/390 w/ trap facility. */ |
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132 | #define I370_OPCODE_ESA390_TR (0x100000) |
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133 | |||
134 | #define I370_OPCODE_ESA390_SUPERSET (0x1fffff) |
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135 | |||
136 | |||
137 | /* The operands table is an array of struct i370_operand. */ |
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138 | |||
139 | struct i370_operand |
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140 | { |
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141 | /* The number of bits in the operand. */ |
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142 | int bits; |
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143 | |||
144 | /* How far the operand is left shifted in the instruction. */ |
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145 | int shift; |
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146 | |||
147 | /* Insertion function. This is used by the assembler. To insert an |
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148 | operand value into an instruction, check this field. |
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149 | |||
150 | If it is NULL, execute |
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151 | i |= (op & ((1 << o->bits) - 1)) << o->shift; |
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152 | (i is the instruction which we are filling in, o is a pointer to |
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153 | this structure, and op is the opcode value; this assumes twos |
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154 | complement arithmetic). |
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155 | |||
156 | If this field is not NULL, then simply call it with the |
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157 | instruction and the operand value. It will return the new value |
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158 | of the instruction. If the ERRMSG argument is not NULL, then if |
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159 | the operand value is illegal, *ERRMSG will be set to a warning |
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160 | string (the operand will be inserted in any case). If the |
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161 | operand value is legal, *ERRMSG will be unchanged (most operands |
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162 | can accept any value). */ |
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163 | i370_insn_t (*insert) |
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164 | (i370_insn_t instruction, long op, const char **errmsg); |
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165 | |||
166 | /* Extraction function. This is used by the disassembler. To |
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167 | extract this operand type from an instruction, check this field. |
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168 | |||
169 | If it is NULL, compute |
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170 | op = ((i) >> o->shift) & ((1 << o->bits) - 1); |
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171 | if ((o->flags & I370_OPERAND_SIGNED) != 0 |
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172 | && (op & (1 << (o->bits - 1))) != 0) |
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173 | op -= 1 << o->bits; |
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174 | (i is the instruction, o is a pointer to this structure, and op |
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175 | is the result; this assumes twos complement arithmetic). |
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176 | |||
177 | If this field is not NULL, then simply call it with the |
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178 | instruction value. It will return the value of the operand. If |
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179 | the INVALID argument is not NULL, *INVALID will be set to |
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180 | non-zero if this operand type can not actually be extracted from |
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181 | this operand (i.e., the instruction does not match). If the |
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182 | operand is valid, *INVALID will not be changed. */ |
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183 | long (*extract) (i370_insn_t instruction, int *invalid); |
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184 | |||
185 | /* One bit syntax flags. */ |
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186 | unsigned long flags; |
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187 | |||
188 | /* name -- handy for debugging, otherwise pointless */ |
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189 | char * name; |
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190 | }; |
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191 | |||
192 | /* Elements in the table are retrieved by indexing with values from |
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193 | the operands field of the i370_opcodes table. */ |
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194 | |||
195 | extern const struct i370_operand i370_operands[]; |
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196 | |||
197 | /* Values defined for the flags field of a struct i370_operand. */ |
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198 | |||
199 | /* This operand should be wrapped in parentheses rather than |
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200 | separated from the previous by a comma. This is used for S, RS and |
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201 | SS form instructions which want their operands to look like |
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202 | reg,displacement(basereg) */ |
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203 | #define I370_OPERAND_SBASE (0x01) |
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204 | |||
205 | /* This operand is a base register. It may or may not appear next |
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206 | to an index register, i.e. either of the two forms |
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207 | reg,displacement(basereg) |
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208 | reg,displacement(index,basereg) */ |
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209 | #define I370_OPERAND_BASE (0x02) |
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210 | |||
211 | /* This pair of operands should be wrapped in parentheses rather than |
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212 | separated from the last by a comma. This is used for the RX form |
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213 | instructions which want their operands to look like |
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214 | reg,displacement(index,basereg) */ |
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215 | #define I370_OPERAND_INDEX (0x04) |
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216 | |||
217 | /* This operand names a register. The disassembler uses this to print |
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218 | register names with a leading 'r'. */ |
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219 | #define I370_OPERAND_GPR (0x08) |
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220 | |||
221 | /* This operand names a floating point register. The disassembler |
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222 | prints these with a leading 'f'. */ |
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223 | #define I370_OPERAND_FPR (0x10) |
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224 | |||
225 | /* This operand is a displacement. */ |
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226 | #define I370_OPERAND_RELATIVE (0x20) |
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227 | |||
228 | /* This operand is a length, such as that in SS form instructions. */ |
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229 | #define I370_OPERAND_LENGTH (0x40) |
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230 | |||
231 | /* This operand is optional, and is zero if omitted. This is used for |
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232 | the optional B2 field in the shift-left, shift-right instructions. The |
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233 | assembler must count the number of operands remaining on the line, |
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234 | and the number of operands remaining for the opcode, and decide |
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235 | whether this operand is present or not. The disassembler should |
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236 | print this operand out only if it is not zero. */ |
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237 | #define I370_OPERAND_OPTIONAL (0x80) |
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238 | |||
239 | |||
240 | /* Define some misc macros. We keep them with the operands table |
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241 | for simplicity. The macro table is an array of struct i370_macro. */ |
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242 | |||
243 | struct i370_macro |
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244 | { |
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245 | /* The macro name. */ |
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246 | const char *name; |
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247 | |||
248 | /* The number of operands the macro takes. */ |
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249 | unsigned int operands; |
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250 | |||
251 | /* One bit flags for the opcode. These are used to indicate which |
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252 | specific processors support the instructions. The values are the |
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253 | same as those for the struct i370_opcode flags field. */ |
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254 | unsigned long flags; |
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255 | |||
256 | /* A format string to turn the macro into a normal instruction. |
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257 | Each %N in the string is replaced with operand number N (zero |
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258 | based). */ |
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259 | const char *format; |
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260 | }; |
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261 | |||
262 | extern const struct i370_macro i370_macros[]; |
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263 | extern const int i370_num_macros; |
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264 | |||
265 | |||
266 | #endif /* I370_H */><>><>><>><>><> |