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6400 | punk_joker | 1 | ;***** THIS IS A MACHINE GENERATED FILE - DO NOT EDIT ******************** |
2 | ;***** Created: 2005-01-11 10:31 ******* Source: ATtiny11.xml ************ |
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3 | ;************************************************************************* |
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4 | ;* A P P L I C A T I O N N O T E F O R T H E A V R F A M I L Y |
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5 | ;* |
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6 | ;* Number : AVR000 |
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7 | ;* File Name : "tn11def.inc" |
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8 | ;* Title : Register/Bit Definitions for the ATtiny11 |
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9 | ;* Date : 2005-01-11 |
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10 | ;* Version : 2.14 |
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11 | ;* Support E-mail : avr@atmel.com |
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12 | ;* Target MCU : ATtiny11 |
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13 | ;* |
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14 | ;* DESCRIPTION |
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15 | ;* When including this file in the assembly program file, all I/O register |
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16 | ;* names and I/O register bit names appearing in the data book can be used. |
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17 | ;* In addition, the six registers forming the three data pointers X, Y and |
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18 | ;* Z have been assigned names XL - ZH. Highest RAM address for Internal |
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19 | ;* SRAM is also defined |
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20 | ;* |
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21 | ;* The Register names are represented by their hexadecimal address. |
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22 | ;* |
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23 | ;* The Register Bit names are represented by their bit number (0-7). |
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24 | ;* |
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25 | ;* Please observe the difference in using the bit names with instructions |
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26 | ;* such as "sbr"/"cbr" (set/clear bit in register) and "sbrs"/"sbrc" |
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27 | ;* (skip if bit in register set/cleared). The following example illustrates |
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28 | ;* this: |
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29 | ;* |
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30 | ;* in r16,PORTB ;read PORTB latch |
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31 | ;* sbr r16,(1< |
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32 | ;* out PORTB,r16 ;output to PORTB |
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33 | ;* |
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34 | ;* in r16,TIFR ;read the Timer Interrupt Flag Register |
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35 | ;* sbrc r16,TOV0 ;test the overflow flag (use bit#) |
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36 | ;* rjmp TOV0_is_set ;jump if set |
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37 | ;* ... ;otherwise do something else |
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38 | ;************************************************************************* |
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39 | |||
40 | #ifndef _TN11DEF_INC_ |
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41 | #define _TN11DEF_INC_ |
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42 | |||
43 | |||
44 | #pragma partinc 0 |
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45 | |||
46 | ; ***** SPECIFY DEVICE *************************************************** |
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47 | .device ATtiny11 |
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48 | #pragma AVRPART ADMIN PART_NAME ATtiny11 |
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49 | .equ SIGNATURE_000 = 0x1e |
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50 | .equ SIGNATURE_001 = 0x90 |
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51 | .equ SIGNATURE_002 = 0x04 |
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52 | |||
53 | #pragma AVRPART CORE CORE_VERSION V0E |
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54 | |||
55 | |||
56 | ; ***** I/O REGISTER DEFINITIONS ***************************************** |
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57 | ; NOTE: |
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58 | ; Definitions marked "MEMORY MAPPED"are extended I/O ports |
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59 | ; and cannot be used with IN/OUT instructions |
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60 | .equ SREG = 0x3f |
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61 | .equ GIMSK = 0x3b |
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62 | .equ GIFR = 0x3a |
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63 | .equ TIMSK = 0x39 |
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64 | .equ TIFR = 0x38 |
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65 | .equ MCUCR = 0x35 |
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66 | .equ MCUSR = 0x34 |
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67 | .equ TCCR0 = 0x33 |
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68 | .equ TCNT0 = 0x32 |
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69 | .equ WDTCR = 0x21 |
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70 | .equ PORTB = 0x18 |
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71 | .equ DDRB = 0x17 |
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72 | .equ PINB = 0x16 |
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73 | .equ ACSR = 0x08 |
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74 | |||
75 | |||
76 | ; ***** BIT DEFINITIONS ************************************************** |
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77 | |||
78 | ; ***** ANALOG_COMPARATOR ************ |
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79 | ; ACSR - Analog Comparator Control And Status Register |
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80 | .equ ACIS0 = 0 ; Analog Comparator Interrupt Mode Select bit 0 |
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81 | .equ ACIS1 = 1 ; Analog Comparator Interrupt Mode Select bit 1 |
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82 | .equ ACIE = 3 ; Analog Comparator Interrupt Enable |
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83 | .equ ACI = 4 ; Analog Comparator Interrupt Flag |
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84 | .equ ACO = 5 ; Analog Comparator Output |
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85 | .equ ACD = 7 ; Analog Comparator Disable |
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86 | |||
87 | |||
88 | ; ***** EXTERNAL_INTERRUPT *********** |
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89 | ; GIMSK - General Interrupt Mask Register |
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90 | .equ PCIE = 5 ; Pin Change Interrupt Enable |
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91 | .equ INT0 = 6 ; External Interrupt Request 0 Enable |
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92 | |||
93 | ; GIFR - General Interrupt Flag register |
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94 | .equ PCIF = 5 ; Pin Change Interrupt Flag |
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95 | .equ INTF0 = 6 ; External Interrupt Flag 0 |
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96 | |||
97 | |||
98 | ; ***** PORTB ************************ |
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99 | ; PORTB - Data Register, Port B |
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100 | .equ PORTB0 = 0 ; |
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101 | .equ PB0 = 0 ; For compatibility |
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102 | .equ PORTB1 = 1 ; |
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103 | .equ PB1 = 1 ; For compatibility |
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104 | .equ PORTB2 = 2 ; |
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105 | .equ PB2 = 2 ; For compatibility |
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106 | .equ PORTB3 = 3 ; |
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107 | .equ PB3 = 3 ; For compatibility |
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108 | .equ PORTB4 = 4 ; |
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109 | .equ PB4 = 4 ; For compatibility |
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110 | |||
111 | ; DDRB - Data Direction Register, Port B |
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112 | .equ DDB0 = 0 ; |
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113 | .equ DDB1 = 1 ; |
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114 | .equ DDB2 = 2 ; |
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115 | .equ DDB3 = 3 ; |
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116 | .equ DDB4 = 4 ; |
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117 | |||
118 | ; PINB - Input Pins, Port B |
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119 | .equ PINB0 = 0 ; |
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120 | .equ PINB1 = 1 ; |
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121 | .equ PINB2 = 2 ; |
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122 | .equ PINB3 = 3 ; |
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123 | .equ PINB4 = 4 ; |
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124 | .equ PINB5 = 5 ; |
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125 | |||
126 | |||
127 | ; ***** TIMER_COUNTER_0 ************** |
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128 | ; TIMSK - Timer/Counter Interrupt Mask Register |
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129 | .equ TOIE0 = 1 ; Timer/Counter0 Overflow Interrupt Enable |
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130 | |||
131 | ; TIFR - Timer/Counter Interrupt Flag register |
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132 | .equ TOV0 = 1 ; Timer/Counter0 Overflow Flag |
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133 | |||
134 | ; TCCR0 - Timer/Counter0 Control Register |
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135 | .equ CS00 = 0 ; Clock Select0 bit 0 |
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136 | .equ CS01 = 1 ; Clock Select0 bit 1 |
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137 | .equ CS02 = 2 ; Clock Select0 bit 2 |
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138 | |||
139 | ; TCNT0 - Timer Counter 0 |
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140 | .equ TCNT00 = 0 ; Timer Counter 0 bit 0 |
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141 | .equ TCNT01 = 1 ; Timer Counter 0 bit 1 |
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142 | .equ TCNT02 = 2 ; Timer Counter 0 bit 2 |
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143 | .equ TCNT03 = 3 ; Timer Counter 0 bit 3 |
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144 | .equ TCNT04 = 4 ; Timer Counter 0 bit 4 |
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145 | .equ TCNT05 = 5 ; Timer Counter 0 bit 5 |
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146 | .equ TCNT06 = 6 ; Timer Counter 0 bit 6 |
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147 | .equ TCNT07 = 7 ; Timer Counter 0 bit 7 |
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148 | |||
149 | |||
150 | ; ***** WATCHDOG ********************* |
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151 | ; WDTCR - Watchdog Timer Control Register |
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152 | .equ WDP0 = 0 ; Watch Dog Timer Prescaler bit 0 |
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153 | .equ WDP1 = 1 ; Watch Dog Timer Prescaler bit 1 |
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154 | .equ WDP2 = 2 ; Watch Dog Timer Prescaler bit 2 |
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155 | .equ WDE = 3 ; Watch Dog Enable |
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156 | .equ WDTOE = 4 ; RW |
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157 | .equ WDDE = WDTOE ; For compatibility |
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158 | |||
159 | |||
160 | ; ***** CPU ************************** |
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161 | ; SREG - Status Register |
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162 | .equ SREG_C = 0 ; Carry Flag |
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163 | .equ SREG_Z = 1 ; Zero Flag |
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164 | .equ SREG_N = 2 ; Negative Flag |
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165 | .equ SREG_V = 3 ; Two's Complement Overflow Flag |
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166 | .equ SREG_S = 4 ; Sign Bit |
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167 | .equ SREG_H = 5 ; Half Carry Flag |
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168 | .equ SREG_T = 6 ; Bit Copy Storage |
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169 | .equ SREG_I = 7 ; Global Interrupt Enable |
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170 | |||
171 | ; MCUCR - MCU Control Register |
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172 | .equ ISC00 = 0 ; Interrupt Sense Control 0 bit 0 |
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173 | .equ ISC01 = 1 ; Interrupt Sense Control 0 bit 1 |
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174 | .equ SM = 4 ; Sleep Mode |
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175 | .equ SE = 5 ; Sleep Enable |
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176 | |||
177 | ; MCUSR - MCU Status register |
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178 | .equ PORF = 0 ; Power-On Reset Flag |
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179 | .equ EXTRF = 1 ; External Reset Flag |
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180 | |||
181 | |||
182 | |||
183 | ; ***** LOCKSBITS ******************************************************** |
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184 | .equ LB1 = 0 ; Lockbit |
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185 | .equ LB2 = 1 ; Lockbit |
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186 | |||
187 | |||
188 | ; ***** FUSES ************************************************************ |
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189 | ; LOW fuse bits |
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190 | |||
191 | |||
192 | |||
193 | ; ***** CPU REGISTER DEFINITIONS ***************************************** |
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194 | .def XH = r27 |
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195 | .def XL = r26 |
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196 | .def YH = r29 |
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197 | .def YL = r28 |
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198 | .def ZH = r31 |
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199 | .def ZL = r30 |
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200 | |||
201 | |||
202 | |||
203 | ; ***** DATA MEMORY DECLARATIONS ***************************************** |
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204 | .equ FLASHEND = 0x01ff ; Note: Word address |
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205 | .equ IOEND = 0x003f |
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206 | .equ SRAM_SIZE = 0 |
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207 | .equ RAMEND = 0x0000 |
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208 | .equ XRAMEND = 0x0000 |
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209 | .equ E2END = 0x0000 |
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210 | .equ EEPROMEND = 0x0000 |
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211 | .equ EEADRBITS = 4294967295 |
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212 | #pragma AVRPART MEMORY PROG_FLASH 1024 |
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213 | #pragma AVRPART MEMORY EEPROM 0 |
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214 | #pragma AVRPART MEMORY INT_SRAM SIZE 0 |
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215 | #pragma AVRPART MEMORY INT_SRAM START_ADDR 0x0 |
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216 | |||
217 | |||
218 | |||
219 | |||
220 | |||
221 | ; ***** INTERRUPT VECTORS ************************************************ |
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222 | .equ INT0addr = 0x0001 ; External Interrupt 0 |
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223 | .equ PCI0addr = 0x0002 ; External Interrupt Request 0 |
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224 | .equ OVF0addr = 0x0003 ; Timer/Counter0 Overflow |
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225 | .equ ACIaddr = 0x0004 ; Analog Comparator |
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226 | |||
227 | .equ INT_VECTORS_SIZE = 5 ; size in words |
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228 | |||
229 | #pragma AVRPART CORE INSTRUCTIONS_NOT_SUPPORTED break |
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230 | |||
231 | #endif /* _TN11DEF_INC_ */ |
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232 | |||
233 | ; ***** END OF FILE ****************************************************** |