WebSVN – Kolibri OS – Blame – /contrib/toolchain/avra/includes/m649def.inc

Rev	Author	Line No.	Line
6400	punk_joker	1	;*** THIS IS A MACHINE GENERATED FILE - DO NOT EDIT ******************
		2	;*** Created: 2005-01-11 10:31 *** Source: ATmega649.xml *********
		3	;*************************************************************************
		4	;* A P P L I C A T I O N N O T E F O R T H E A V R F A M I L Y
		5	;*
		6	;* Number : AVR000
		7	;* File Name : "m649def.inc"
		8	;* Title : Register/Bit Definitions for the ATmega649
		9	;* Date : 2005-01-11
		10	;* Version : 2.14
		11	;* Support E-mail : avr@atmel.com
		12	;* Target MCU : ATmega649
		13	;*
		14	;* DESCRIPTION
		15	;* When including this file in the assembly program file, all I/O register
		16	;* names and I/O register bit names appearing in the data book can be used.
		17	;* In addition, the six registers forming the three data pointers X, Y and
		18	;* Z have been assigned names XL - ZH. Highest RAM address for Internal
		19	;* SRAM is also defined
		20	;*
		21	;* The Register names are represented by their hexadecimal address.
		22	;*
		23	;* The Register Bit names are represented by their bit number (0-7).
		24	;*
		25	;* Please observe the difference in using the bit names with instructions
		26	;* such as "sbr"/"cbr" (set/clear bit in register) and "sbrs"/"sbrc"
		27	;* (skip if bit in register set/cleared). The following example illustrates
		28	;* this:
		29	;*
		30	;* in r16,PORTB ;read PORTB latch
		31	;* sbr r16,(1<
		32	;* out PORTB,r16 ;output to PORTB
		33	;*
		34	;* in r16,TIFR ;read the Timer Interrupt Flag Register
		35	;* sbrc r16,TOV0 ;test the overflow flag (use bit#)
		36	;* rjmp TOV0_is_set ;jump if set
		37	;* ... ;otherwise do something else
		38	;*************************************************************************
		39
		40	#ifndef _M649DEF_INC_
		41	#define _M649DEF_INC_
		42
		43
		44	#pragma partinc 0
		45
		46	; *** SPECIFY DEVICE *************************************************
		47	.device ATmega649
		48	#pragma AVRPART ADMIN PART_NAME ATmega649
		49	.equ SIGNATURE_000 = 0x1e
		50	.equ SIGNATURE_001 = 0x96
		51	.equ SIGNATURE_002 = 0x03
		52
		53	#pragma AVRPART CORE CORE_VERSION V2E
		54
		55
		56	; *** I/O REGISTER DEFINITIONS ***************************************
		57	; NOTE:
		58	; Definitions marked "MEMORY MAPPED"are extended I/O ports
		59	; and cannot be used with IN/OUT instructions
		60	.equ LCDDR19 = 0xff ; MEMORY MAPPED
		61	.equ LCDDR18 = 0xfe ; MEMORY MAPPED
		62	.equ LCDDR17 = 0xfd ; MEMORY MAPPED
		63	.equ LCDDR16 = 0xfc ; MEMORY MAPPED
		64	.equ LCDDR15 = 0xfb ; MEMORY MAPPED
		65	.equ LCDDR14 = 0xfa ; MEMORY MAPPED
		66	.equ LCDDR13 = 0xf9 ; MEMORY MAPPED
		67	.equ LCDDR12 = 0xf8 ; MEMORY MAPPED
		68	.equ LCDDR11 = 0xf7 ; MEMORY MAPPED
		69	.equ LCDDR10 = 0xf6 ; MEMORY MAPPED
		70	.equ LCDDR9 = 0xf5 ; MEMORY MAPPED
		71	.equ LCDDR8 = 0xf4 ; MEMORY MAPPED
		72	.equ LCDDR7 = 0xf3 ; MEMORY MAPPED
		73	.equ LCDDR6 = 0xf2 ; MEMORY MAPPED
		74	.equ LCDDR5 = 0xf1 ; MEMORY MAPPED
		75	.equ LCDDR4 = 0xf0 ; MEMORY MAPPED
		76	.equ LCDDR3 = 0xef ; MEMORY MAPPED
		77	.equ LCDDR2 = 0xee ; MEMORY MAPPED
		78	.equ LCDDR1 = 0xed ; MEMORY MAPPED
		79	.equ LCDDR0 = 0xec ; MEMORY MAPPED
		80	.equ LCDCCR = 0xe7 ; MEMORY MAPPED
		81	.equ LCDFRR = 0xe6 ; MEMORY MAPPED
		82	.equ LCDCRB = 0xe5 ; MEMORY MAPPED
		83	.equ LCDCRA = 0xe4 ; MEMORY MAPPED
		84	.equ PORTJ = 0xdd ; MEMORY MAPPED
		85	.equ DDRJ = 0xdc ; MEMORY MAPPED
		86	.equ PINJ = 0xdb ; MEMORY MAPPED
		87	.equ PORTH = 0xda ; MEMORY MAPPED
		88	.equ DDRH = 0xd9 ; MEMORY MAPPED
		89	.equ PINH = 0xd8 ; MEMORY MAPPED
		90	.equ UDR = 0xc6 ; MEMORY MAPPED
		91	.equ UBRRH = 0xc5 ; MEMORY MAPPED
		92	.equ UBRRL = 0xc4 ; MEMORY MAPPED
		93	.equ UCSRC = 0xc2 ; MEMORY MAPPED
		94	.equ UCSRB = 0xc1 ; MEMORY MAPPED
		95	.equ UCSRA = 0xc0 ; MEMORY MAPPED
		96	.equ USIDR = 0xba ; MEMORY MAPPED
		97	.equ USISR = 0xb9 ; MEMORY MAPPED
		98	.equ USICR = 0xb8 ; MEMORY MAPPED
		99	.equ ASSR = 0xb6 ; MEMORY MAPPED
		100	.equ OCR2A = 0xb3 ; MEMORY MAPPED
		101	.equ TCNT2 = 0xb2 ; MEMORY MAPPED
		102	.equ TCCR2A = 0xb0 ; MEMORY MAPPED
		103	.equ OCR1BH = 0x8b ; MEMORY MAPPED
		104	.equ OCR1BL = 0x8a ; MEMORY MAPPED
		105	.equ OCR1AH = 0x89 ; MEMORY MAPPED
		106	.equ OCR1AL = 0x88 ; MEMORY MAPPED
		107	.equ ICR1H = 0x87 ; MEMORY MAPPED
		108	.equ ICR1L = 0x86 ; MEMORY MAPPED
		109	.equ TCNT1H = 0x85 ; MEMORY MAPPED
		110	.equ TCNT1L = 0x84 ; MEMORY MAPPED
		111	.equ TCCR1C = 0x82 ; MEMORY MAPPED
		112	.equ TCCR1B = 0x81 ; MEMORY MAPPED
		113	.equ TCCR1A = 0x80 ; MEMORY MAPPED
		114	.equ DIDR1 = 0x7f ; MEMORY MAPPED
		115	.equ DIDR0 = 0x7e ; MEMORY MAPPED
		116	.equ ADMUX = 0x7c ; MEMORY MAPPED
		117	.equ ADCSRB = 0x7b ; MEMORY MAPPED
		118	.equ ADCSRA = 0x7a ; MEMORY MAPPED
		119	.equ ADCH = 0x79 ; MEMORY MAPPED
		120	.equ ADCL = 0x78 ; MEMORY MAPPED
		121	.equ PCMSK3 = 0x73 ; MEMORY MAPPED
		122	.equ TIMSK2 = 0x70 ; MEMORY MAPPED
		123	.equ TIMSK1 = 0x6f ; MEMORY MAPPED
		124	.equ TIMSK0 = 0x6e ; MEMORY MAPPED
		125	.equ PCMSK2 = 0x6d ; MEMORY MAPPED
		126	.equ PCMSK1 = 0x6c ; MEMORY MAPPED
		127	.equ PCMSK0 = 0x6b ; MEMORY MAPPED
		128	.equ EICRA = 0x69 ; MEMORY MAPPED
		129	.equ OSCCAL = 0x66 ; MEMORY MAPPED
		130	.equ PRR = 0x64 ; MEMORY MAPPED
		131	.equ CLKPR = 0x61 ; MEMORY MAPPED
		132	.equ WDTCR = 0x60 ; MEMORY MAPPED
		133	.equ SREG = 0x3f
		134	.equ SPH = 0x3e
		135	.equ SPL = 0x3d
		136	.equ SPMCSR = 0x37
		137	.equ MCUCR = 0x35
		138	.equ MCUSR = 0x34
		139	.equ SMCR = 0x33
		140	.equ OCDR = 0x31
		141	.equ ACSR = 0x30
		142	.equ SPDR = 0x2e
		143	.equ SPSR = 0x2d
		144	.equ SPCR = 0x2c
		145	.equ GPIOR2 = 0x2b
		146	.equ GPIOR1 = 0x2a
		147	.equ OCR0A = 0x27
		148	.equ TCNT0 = 0x26
		149	.equ TCCR0A = 0x24
		150	.equ GTCCR = 0x23
		151	.equ EEARH = 0x22
		152	.equ EEARL = 0x21
		153	.equ EEDR = 0x20
		154	.equ EECR = 0x1f
		155	.equ GPIOR0 = 0x1e
		156	.equ EIMSK = 0x1d
		157	.equ EIFR = 0x1c
		158	.equ TIFR2 = 0x17
		159	.equ TIFR1 = 0x16
		160	.equ TIFR0 = 0x15
		161	.equ PORTG = 0x14
		162	.equ DDRG = 0x13
		163	.equ PING = 0x12
		164	.equ PORTF = 0x11
		165	.equ DDRF = 0x10
		166	.equ PINF = 0x0f
		167	.equ PORTE = 0x0e
		168	.equ DDRE = 0x0d
		169	.equ PINE = 0x0c
		170	.equ PORTD = 0x0b
		171	.equ DDRD = 0x0a
		172	.equ PIND = 0x09
		173	.equ PORTC = 0x08
		174	.equ DDRC = 0x07
		175	.equ PINC = 0x06
		176	.equ PORTB = 0x05
		177	.equ DDRB = 0x04
		178	.equ PINB = 0x03
		179	.equ PORTA = 0x02
		180	.equ DDRA = 0x01
		181	.equ PINA = 0x00
		182
		183
		184	; *** BIT DEFINITIONS ************************************************
		185
		186	; *** AD_CONVERTER ***************
		187	; ADMUX - The ADC multiplexer Selection Register
		188	.equ MUX0 = 0 ; Analog Channel and Gain Selection Bits
		189	.equ MUX1 = 1 ; Analog Channel and Gain Selection Bits
		190	.equ MUX2 = 2 ; Analog Channel and Gain Selection Bits
		191	.equ MUX3 = 3 ; Analog Channel and Gain Selection Bits
		192	.equ MUX4 = 4 ; Analog Channel and Gain Selection Bits
		193	.equ ADLAR = 5 ; Left Adjust Result
		194	.equ REFS0 = 6 ; Reference Selection Bit 0
		195	.equ REFS1 = 7 ; Reference Selection Bit 1
		196
		197	; ADCSRA - The ADC Control and Status register
		198	.equ ADPS0 = 0 ; ADC Prescaler Select Bits
		199	.equ ADPS1 = 1 ; ADC Prescaler Select Bits
		200	.equ ADPS2 = 2 ; ADC Prescaler Select Bits
		201	.equ ADIE = 3 ; ADC Interrupt Enable
		202	.equ ADIF = 4 ; ADC Interrupt Flag
		203	.equ ADATE = 5 ; ADC Auto Trigger Enable
		204	.equ ADSC = 6 ; ADC Start Conversion
		205	.equ ADEN = 7 ; ADC Enable
		206
		207	; ADCH - ADC Data Register High Byte
		208	.equ ADCH0 = 0 ; ADC Data Register High Byte Bit 0
		209	.equ ADCH1 = 1 ; ADC Data Register High Byte Bit 1
		210	.equ ADCH2 = 2 ; ADC Data Register High Byte Bit 2
		211	.equ ADCH3 = 3 ; ADC Data Register High Byte Bit 3
		212	.equ ADCH4 = 4 ; ADC Data Register High Byte Bit 4
		213	.equ ADCH5 = 5 ; ADC Data Register High Byte Bit 5
		214	.equ ADCH6 = 6 ; ADC Data Register High Byte Bit 6
		215	.equ ADCH7 = 7 ; ADC Data Register High Byte Bit 7
		216
		217	; ADCL - ADC Data Register Low Byte
		218	.equ ADCL0 = 0 ; ADC Data Register Low Byte Bit 0
		219	.equ ADCL1 = 1 ; ADC Data Register Low Byte Bit 1
		220	.equ ADCL2 = 2 ; ADC Data Register Low Byte Bit 2
		221	.equ ADCL3 = 3 ; ADC Data Register Low Byte Bit 3
		222	.equ ADCL4 = 4 ; ADC Data Register Low Byte Bit 4
		223	.equ ADCL5 = 5 ; ADC Data Register Low Byte Bit 5
		224	.equ ADCL6 = 6 ; ADC Data Register Low Byte Bit 6
		225	.equ ADCL7 = 7 ; ADC Data Register Low Byte Bit 7
		226
		227	; ADCSRB - ADC Control and Status Register B
		228	.equ ADTS0 = 0 ; ADC Auto Trigger Source 0
		229	.equ ADTS1 = 1 ; ADC Auto Trigger Source 1
		230	.equ ADTS2 = 2 ; ADC Auto Trigger Source 2
		231
		232	; DIDR0 - Digital Input Disable Register 0
		233	.equ ADC0D = 0 ; ADC0 Digital input Disable
		234	.equ ADC1D = 1 ; ADC1 Digital input Disable
		235	.equ ADC2D = 2 ; ADC2 Digital input Disable
		236	.equ ADC3D = 3 ; ADC3 Digital input Disable
		237	.equ ADC4D = 4 ; ADC4 Digital input Disable
		238	.equ ADC5D = 5 ; ADC5 Digital input Disable
		239	.equ ADC6D = 6 ; ADC6 Digital input Disable
		240	.equ ADC7D = 7 ; ADC7 Digital input Disable
		241
		242
		243	; *** ANALOG_COMPARATOR **********
		244	; ADCSRB - ADC Control and Status Register B
		245	.equ ACME = 6 ; Analog Comparator Multiplexer Enable
		246
		247	; ACSR - Analog Comparator Control And Status Register
		248	.equ ACIS0 = 0 ; Analog Comparator Interrupt Mode Select bit 0
		249	.equ ACIS1 = 1 ; Analog Comparator Interrupt Mode Select bit 1
		250	.equ ACIC = 2 ; Analog Comparator Input Capture Enable
		251	.equ ACIE = 3 ; Analog Comparator Interrupt Enable
		252	.equ ACI = 4 ; Analog Comparator Interrupt Flag
		253	.equ ACO = 5 ; Analog Compare Output
		254	.equ ACBG = 6 ; Analog Comparator Bandgap Select
		255	.equ ACD = 7 ; Analog Comparator Disable
		256
		257	; DIDR1 - Digital Input Disable Register 1
		258	.equ AIN0D = 0 ; AIN0 Digital Input Disable
		259	.equ AIN1D = 1 ; AIN1 Digital Input Disable
		260
		261
		262	; *** SPI ************************
		263	; SPDR - SPI Data Register
		264	.equ SPDR0 = 0 ; SPI Data Register bit 0
		265	.equ SPDR1 = 1 ; SPI Data Register bit 1
		266	.equ SPDR2 = 2 ; SPI Data Register bit 2
		267	.equ SPDR3 = 3 ; SPI Data Register bit 3
		268	.equ SPDR4 = 4 ; SPI Data Register bit 4
		269	.equ SPDR5 = 5 ; SPI Data Register bit 5
		270	.equ SPDR6 = 6 ; SPI Data Register bit 6
		271	.equ SPDR7 = 7 ; SPI Data Register bit 7
		272
		273	; SPSR - SPI Status Register
		274	.equ SPI2X = 0 ; Double SPI Speed Bit
		275	.equ WCOL = 6 ; Write Collision Flag
		276	.equ SPIF = 7 ; SPI Interrupt Flag
		277
		278	; SPCR - SPI Control Register
		279	.equ SPR0 = 0 ; SPI Clock Rate Select 0
		280	.equ SPR1 = 1 ; SPI Clock Rate Select 1
		281	.equ CPHA = 2 ; Clock Phase
		282	.equ CPOL = 3 ; Clock polarity
		283	.equ MSTR = 4 ; Master/Slave Select
		284	.equ DORD = 5 ; Data Order
		285	.equ SPE = 6 ; SPI Enable
		286	.equ SPIE = 7 ; SPI Interrupt Enable
		287
		288
		289	; *** USI ************************
		290	; USIDR - USI Data Register
		291	.equ USIDR0 = 0 ; USI Data Register bit 0
		292	.equ USIDR1 = 1 ; USI Data Register bit 1
		293	.equ USIDR2 = 2 ; USI Data Register bit 2
		294	.equ USIDR3 = 3 ; USI Data Register bit 3
		295	.equ USIDR4 = 4 ; USI Data Register bit 4
		296	.equ USIDR5 = 5 ; USI Data Register bit 5
		297	.equ USIDR6 = 6 ; USI Data Register bit 6
		298	.equ USIDR7 = 7 ; USI Data Register bit 7
		299
		300	; USISR - USI Status Register
		301	.equ USICNT0 = 0 ; USI Counter Value Bit 0
		302	.equ USICNT1 = 1 ; USI Counter Value Bit 1
		303	.equ USICNT2 = 2 ; USI Counter Value Bit 2
		304	.equ USICNT3 = 3 ; USI Counter Value Bit 3
		305	.equ USIDC = 4 ; Data Output Collision
		306	.equ USIPF = 5 ; Stop Condition Flag
		307	.equ USIOIF = 6 ; Counter Overflow Interrupt Flag
		308	.equ USISIF = 7 ; Start Condition Interrupt Flag
		309
		310	; USICR - USI Control Register
		311	.equ USITC = 0 ; Toggle Clock Port Pin
		312	.equ USICLK = 1 ; Clock Strobe
		313	.equ USICS0 = 2 ; USI Clock Source Select Bit 0
		314	.equ USICS1 = 3 ; USI Clock Source Select Bit 1
		315	.equ USIWM0 = 4 ; USI Wire Mode Bit 0
		316	.equ USIWM1 = 5 ; USI Wire Mode Bit 1
		317	.equ USIOIE = 6 ; Counter Overflow Interrupt Enable
		318	.equ USISIE = 7 ; Start Condition Interrupt Enable
		319
		320
		321	; *** USART0 *********************
		322	; UDR - USART I/O Data Register
		323	.equ UDR0 = UDR ; For compatibility
		324	.equ UDR00 = 0 ; USART I/O Data Register bit 0
		325	.equ UDR01 = 1 ; USART I/O Data Register bit 1
		326	.equ UDR02 = 2 ; USART I/O Data Register bit 2
		327	.equ UDR03 = 3 ; USART I/O Data Register bit 3
		328	.equ UDR04 = 4 ; USART I/O Data Register bit 4
		329	.equ UDR05 = 5 ; USART I/O Data Register bit 5
		330	.equ UDR06 = 6 ; USART I/O Data Register bit 6
		331	.equ UDR07 = 7 ; USART I/O Data Register bit 7
		332
		333	; UCSRA - USART Control and Status Register A
		334	.equ UCSR0A = UCSRA ; For compatibility
		335	.equ USR = UCSRA ; For compatibility
		336	.equ MPCM = 0 ; Multi-processor Communication Mode
		337	.equ MPCM0 = MPCM ; For compatibility
		338	.equ U2X = 1 ; Double the USART Transmission Speed
		339	.equ U2X0 = U2X ; For compatibility
		340	.equ UPE = 2 ; USART Parity Error
		341	.equ UPE0 = UPE ; For compatibility
		342	.equ DOR = 3 ; Data OverRun
		343	.equ DOR0 = DOR ; For compatibility
		344	.equ FE = 4 ; Framing Error
		345	.equ FE0 = FE ; For compatibility
		346	.equ UDRE = 5 ; USART Data Register Empty
		347	.equ UDRE0 = UDRE ; For compatibility
		348	.equ TXC = 6 ; USART Transmit Complete
		349	.equ TXC0 = TXC ; For compatibility
		350	.equ RXC = 7 ; USART Receive Complete
		351	.equ RXC0 = RXC ; For compatibility
		352
		353	; UCSRB - USART Control and Status Register B
		354	.equ UCSR0B = UCSRB ; For compatibility
		355	.equ UCR = UCSRB ; For compatibility
		356	.equ TXB8 = 0 ; Transmit Data Bit 8
		357	.equ TXB80 = TXB8 ; For compatibility
		358	.equ RXB8 = 1 ; Receive Data Bit 8
		359	.equ RXB80 = RXB8 ; For compatibility
		360	.equ UCSZ2 = 2 ; Character Size
		361	.equ UCSZ02 = UCSZ2 ; For compatibility
		362	.equ TXEN = 3 ; Transmitter Enable
		363	.equ TXEN0 = TXEN ; For compatibility
		364	.equ RXEN = 4 ; Receiver Enable
		365	.equ RXEN0 = RXEN ; For compatibility
		366	.equ UDRIE = 5 ; USART Data Register Empty Interrupt Enable
		367	.equ UDRIE0 = UDRIE ; For compatibility
		368	.equ TXCIE = 6 ; TX Complete Interrupt Enable
		369	.equ TXCIE0 = TXCIE ; For compatibility
		370	.equ RXCIE = 7 ; RX Complete Interrupt Enable
		371	.equ RXCIE0 = RXCIE ; For compatibility
		372
		373	; UCSRC - USART Control and Status Register C
		374	.equ UCSR0C = UCSRC ; For compatibility
		375	.equ UCPOL = 0 ; Clock Polarity
		376	.equ UCPOL0 = UCPOL ; For compatibility
		377	.equ UCSZ0 = 1 ; Character Size
		378	.equ UCSZ00 = UCSZ0 ; For compatibility
		379	.equ UCSZ1 = 2 ; Character Size
		380	.equ UCSZ01 = UCSZ1 ; For compatibility
		381	.equ USBS = 3 ; Stop Bit Select
		382	.equ USBS0 = USBS ; For compatibility
		383	.equ UPM0 = 4 ; Parity Mode Bit 0
		384	.equ UPM00 = UPM0 ; For compatibility
		385	.equ UPM1 = 5 ; Parity Mode Bit 1
		386	.equ UPM01 = UPM1 ; For compatibility
		387	.equ UMSEL = 6 ; USART Mode Select
		388	.equ UMSEL0 = UMSEL ; For compatibility
		389
		390	.equ UBRR0H = UBRRH ; For compatibility
		391	.equ UBRR0L = UBRRL ; For compatibility
		392	.equ UBRR0 = UBRRL ; For compatibility
		393	.equ UBRR = UBRRL ; For compatibility
		394
		395	; *** CPU ************************
		396	; SREG - Status Register
		397	.equ SREG_C = 0 ; Carry Flag
		398	.equ SREG_Z = 1 ; Zero Flag
		399	.equ SREG_N = 2 ; Negative Flag
		400	.equ SREG_V = 3 ; Two's Complement Overflow Flag
		401	.equ SREG_S = 4 ; Sign Bit
		402	.equ SREG_H = 5 ; Half Carry Flag
		403	.equ SREG_T = 6 ; Bit Copy Storage
		404	.equ SREG_I = 7 ; Global Interrupt Enable
		405
		406	; MCUCR - MCU Control Register
		407	.equ IVCE = 0 ; Interrupt Vector Change Enable
		408	.equ IVSEL = 1 ; Interrupt Vector Select
		409	.equ PUD = 4 ; Pull-up disable
		410
		411	; MCUSR - MCU Status Register
		412	.equ PORF = 0 ; Power-on reset flag
		413	.equ EXTRF = 1 ; External Reset Flag
		414	.equ BORF = 2 ; Brown-out Reset Flag
		415	.equ WDRF = 3 ; Watchdog Reset Flag
		416	.equ JTRF = 4 ; JTAG Reset Flag
		417
		418	; OSCCAL - Oscillator Calibration Value
		419	.equ CAL0 = 0 ; Oscillator Calibration Value Bit0
		420	.equ CAL1 = 1 ; Oscillator Calibration Value Bit1
		421	.equ CAL2 = 2 ; Oscillator Calibration Value Bit2
		422	.equ CAL3 = 3 ; Oscillator Calibration Value Bit3
		423	.equ CAL4 = 4 ; Oscillator Calibration Value Bit4
		424	.equ CAL5 = 5 ; Oscillator Calibration Value Bit5
		425	.equ CAL6 = 6 ; Oscillator Calibration Value Bit6
		426	.equ CAL7 = 7 ; Oscillator Calibration Value Bit7
		427
		428	; CLKPR - Clock Prescale Register
		429	.equ CLKPS0 = 0 ; Clock Prescaler Select Bit 0
		430	.equ CLKPS1 = 1 ; Clock Prescaler Select Bit 1
		431	.equ CLKPS2 = 2 ; Clock Prescaler Select Bit 2
		432	.equ CLKPS3 = 3 ; Clock Prescaler Select Bit 3
		433	.equ CLKPCE = 7 ; Clock Prescaler Change Enable
		434
		435	; PRR - Power Reduction Register
		436	.equ PRADC = 0 ; Power Reduction ADC
		437	.equ PRUSART0 = 1 ; Power Reduction USART
		438	.equ PRSPI = 2 ; Power Reduction Serial Peripheral Interface
		439	.equ PRTIM1 = 3 ; Power Reduction Timer/Counter1
		440	.equ PRLCD = 4 ; Power Reduction LCD
		441
		442	; SMCR - Sleep Mode Control Register
		443	.equ SE = 0 ; Sleep Enable
		444	.equ SM0 = 1 ; Sleep Mode Select bit 0
		445	.equ SM1 = 2 ; Sleep Mode Select bit 1
		446	.equ SM2 = 3 ; Sleep Mode Select bit 2
		447
		448	; GPIOR2 - General Purpose IO Register 2
		449	.equ GPIOR20 = 0 ; General Purpose IO Register 2 bit 0
		450	.equ GPIOR21 = 1 ; General Purpose IO Register 2 bit 1
		451	.equ GPIOR22 = 2 ; General Purpose IO Register 2 bit 2
		452	.equ GPIOR23 = 3 ; General Purpose IO Register 2 bit 3
		453	.equ GPIOR24 = 4 ; General Purpose IO Register 2 bit 4
		454	.equ GPIOR25 = 5 ; General Purpose IO Register 2 bit 5
		455	.equ GPIOR26 = 6 ; General Purpose IO Register 2 bit 6
		456	.equ GPIOR27 = 7 ; General Purpose IO Register 2 bit 7
		457
		458	; GPIOR1 - General Purpose IO Register 1
		459	.equ GPIOR10 = 0 ; General Purpose IO Register 1 bit 0
		460	.equ GPIOR11 = 1 ; General Purpose IO Register 1 bit 1
		461	.equ GPIOR12 = 2 ; General Purpose IO Register 1 bit 2
		462	.equ GPIOR13 = 3 ; General Purpose IO Register 1 bit 3
		463	.equ GPIOR14 = 4 ; General Purpose IO Register 1 bit 4
		464	.equ GPIOR15 = 5 ; General Purpose IO Register 1 bit 5
		465	.equ GPIOR16 = 6 ; General Purpose IO Register 1 bit 6
		466	.equ GPIOR17 = 7 ; General Purpose IO Register 1 bit 7
		467
		468	; GPIOR0 - General Purpose IO Register 0
		469	.equ GPIOR00 = 0 ; General Purpose IO Register 0 bit 0
		470	.equ GPIOR01 = 1 ; General Purpose IO Register 0 bit 1
		471	.equ GPIOR02 = 2 ; General Purpose IO Register 0 bit 2
		472	.equ GPIOR03 = 3 ; General Purpose IO Register 0 bit 3
		473	.equ GPIOR04 = 4 ; General Purpose IO Register 0 bit 4
		474	.equ GPIOR05 = 5 ; General Purpose IO Register 0 bit 5
		475	.equ GPIOR06 = 6 ; General Purpose IO Register 0 bit 6
		476	.equ GPIOR07 = 7 ; General Purpose IO Register 0 bit 7
		477
		478
		479	; *** JTAG ***********************
		480	; OCDR - On-Chip Debug Related Register in I/O Memory
		481	.equ OCDR0 = 0 ; On-Chip Debug Register Bit 0
		482	.equ OCDR1 = 1 ; On-Chip Debug Register Bit 1
		483	.equ OCDR2 = 2 ; On-Chip Debug Register Bit 2
		484	.equ OCDR3 = 3 ; On-Chip Debug Register Bit 3
		485	.equ OCDR4 = 4 ; On-Chip Debug Register Bit 4
		486	.equ OCDR5 = 5 ; On-Chip Debug Register Bit 5
		487	.equ OCDR6 = 6 ; On-Chip Debug Register Bit 6
		488	.equ OCDR7 = 7 ; On-Chip Debug Register Bit 7
		489	.equ IDRD = OCDR7 ; For compatibility
		490
		491	; MCUCR - MCU Control Register
		492	.equ JTD = 7 ; JTAG Interface Disable
		493
		494	; MCUSR - MCU Status Register
		495	;.equ JTRF = 4 ; JTAG Reset Flag
		496
		497
		498	; *** MISC ***********************
		499	; LCDCRA - LCD Control Register A
		500	.equ LCDBL = 0 ; LCD Blanking
		501	.equ LCDIE = 3 ; LCD Interrupt Enable
		502	.equ LCDIF = 4 ; LCD Interrupt Flag
		503	.equ LCDAB = 6 ; LCD A or B waveform
		504	.equ LCDEN = 7 ; LCD Enable
		505
		506	; LCDCRB - LCD Control and Status Register B
		507	.equ LCDPM0 = 0 ; LCD Port Mask 0
		508	.equ LCDPM1 = 1 ; LCD Port Mask 1
		509	.equ LCDPM2 = 2 ; LCD Port Mask 2
		510	.equ LCDPM3 = 3 ; LCD Port Mask 3
		511	.equ LCDMUX0 = 4 ; LCD Mux Select 0
		512	.equ LCDMUX1 = 5 ; LCD Mux Select 1
		513	.equ LCD2B = 6 ; LCD 1/2 Bias Select
		514	.equ LCDCS = 7 ; LCD CLock Select
		515
		516	; LCDFRR - LCD Frame Rate Register
		517	.equ LCDCD0 = 0 ; LCD Clock Divider 0
		518	.equ LCDCD1 = 1 ; LCD Clock Divider 1
		519	.equ LCDCD2 = 2 ; LCD Clock Divider 2
		520	.equ LCDPS0 = 4 ; LCD Prescaler Select 0
		521	.equ LCDPS1 = 5 ; LCD Prescaler Select 1
		522	.equ LCDPS2 = 6 ; LCD Prescaler Select 2
		523
		524	; LCDCCR - LCD Contrast Control Register
		525	.equ LCDCC0 = 0 ; LCD Contrast Control 0
		526	.equ LCDCC1 = 1 ; LCD Contrast Control 1
		527	.equ LCDCC2 = 2 ; LCD Contrast Control 2
		528	.equ LCDCC3 = 3 ; LCD Contrast Control 3
		529	.equ LCDDC0 = 5 ;
		530	.equ LCDDC1 = 6 ;
		531	.equ LCDDC2 = 7 ;
		532
		533	; LCDDR18 - LCD Data Register 18
		534	.equ SEG324 = 0 ;
		535
		536	; LCDDR17 - LCD Data Register 17
		537	.equ SEG316 = 0 ;
		538	.equ SEG317 = 1 ;
		539	.equ SEG318 = 2 ;
		540	.equ SEG319 = 3 ;
		541	.equ SEG320 = 4 ;
		542	.equ SEG321 = 5 ;
		543	.equ SEG322 = 6 ;
		544	.equ SEG323 = 7 ;
		545
		546	; LCDDR16 - LCD Data Register 16
		547	.equ SEG308 = 0 ;
		548	.equ SEG309 = 1 ;
		549	.equ SEG310 = 2 ;
		550	.equ SEG311 = 3 ;
		551	.equ SEG312 = 4 ;
		552	.equ SEG313 = 5 ;
		553	.equ SEG314 = 6 ;
		554	.equ SEG315 = 7 ;
		555
		556	; LCDDR15 - LCD Data Register 15
		557	.equ SEG300 = 0 ;
		558	.equ SEG301 = 1 ;
		559	.equ SEG302 = 2 ;
		560	.equ SEG303 = 3 ;
		561	.equ SEG304 = 4 ;
		562	.equ SEG305 = 5 ;
		563	.equ SEG306 = 6 ;
		564	.equ SEG307 = 7 ;
		565
		566	; LCDDR13 - LCD Data Register 13
		567	.equ SEG224 = 0 ;
		568
		569	; LCDDR12 - LCD Data Register 12
		570	.equ SEG216 = 0 ;
		571	.equ SEG217 = 1 ;
		572	.equ SEG218 = 2 ;
		573	.equ SEG219 = 3 ;
		574	.equ SEG220 = 4 ;
		575	.equ SEG221 = 5 ;
		576	.equ SEG222 = 6 ;
		577	.equ SEG223 = 7 ;
		578
		579	; LCDDR11 - LCD Data Register 11
		580	.equ SEG208 = 0 ;
		581	.equ SEG209 = 1 ;
		582	.equ SEG210 = 2 ;
		583	.equ SEG211 = 3 ;
		584	.equ SEG212 = 4 ;
		585	.equ SEG213 = 5 ;
		586	.equ SEG214 = 6 ;
		587	.equ SEG215 = 7 ;
		588
		589	; LCDDR10 - LCD Data Register 10
		590	.equ SEG200 = 0 ;
		591	.equ SEG201 = 1 ;
		592	.equ SEG202 = 2 ;
		593	.equ SEG203 = 3 ;
		594	.equ SEG204 = 4 ;
		595	.equ SEG205 = 5 ;
		596	.equ SEG206 = 6 ;
		597	.equ SEG207 = 7 ;
		598
		599	; LCDDR8 - LCD Data Register 8
		600	.equ SEG124 = 0 ;
		601
		602	; LCDDR7 - LCD Data Register 7
		603	.equ SEG116 = 0 ;
		604	.equ SEG117 = 1 ;
		605	.equ SEG118 = 2 ;
		606	.equ SEG119 = 3 ;
		607	.equ SEG120 = 4 ;
		608	.equ SEG121 = 5 ;
		609	.equ SEG122 = 6 ;
		610	.equ SEG123 = 7 ;
		611
		612	; LCDDR6 - LCD Data Register 6
		613	.equ SEG108 = 0 ;
		614	.equ SEG109 = 1 ;
		615	.equ SEG110 = 2 ;
		616	.equ SEG111 = 3 ;
		617	.equ SEG112 = 4 ;
		618	.equ SEG113 = 5 ;
		619	.equ SEG114 = 6 ;
		620	.equ SEG115 = 7 ;
		621
		622	; LCDDR5 - LCD Data Register 5
		623	.equ SEG100 = 0 ;
		624	.equ SEG101 = 1 ;
		625	.equ SEG102 = 2 ;
		626	.equ SEG103 = 3 ;
		627	.equ SEG104 = 4 ;
		628	.equ SEG105 = 5 ;
		629	.equ SEG106 = 6 ;
		630	.equ SEG107 = 7 ;
		631
		632	; LCDDR3 - LCD Data Register 3
		633	.equ SEG024 = 0 ;
		634
		635	; LCDDR2 - LCD Data Register 2
		636	.equ SEG016 = 0 ;
		637	.equ SEG017 = 1 ;
		638	.equ SEG018 = 2 ;
		639	.equ SEG019 = 3 ;
		640	.equ SEG020 = 4 ;
		641	.equ SEG021 = 5 ;
		642	.equ SEG022 = 6 ;
		643	.equ SEG023 = 7 ;
		644
		645	; LCDDR1 - LCD Data Register 1
		646	.equ SEG008 = 0 ;
		647	.equ SEG009 = 1 ;
		648	.equ SEG010 = 2 ;
		649	.equ SEG011 = 3 ;
		650	.equ SEG012 = 4 ;
		651	.equ SEG013 = 5 ;
		652	.equ SEG014 = 6 ;
		653	.equ SEG015 = 7 ;
		654
		655	; LCDDR0 - LCD Data Register 0
		656	.equ SEG000 = 0 ;
		657	.equ SEG001 = 1 ;
		658	.equ SEG002 = 2 ;
		659	.equ SEG003 = 3 ;
		660	.equ SEG004 = 4 ;
		661	.equ SEG005 = 5 ;
		662	.equ SEG006 = 6 ;
		663	.equ SEG007 = 7 ;
		664
		665
		666	; *** EXTERNAL_INTERRUPT *********
		667	; EICRA - External Interrupt Control Register A
		668	.equ ISC00 = 0 ; External Interrupt Sense Control 0 Bit 0
		669	.equ ISC01 = 1 ; External Interrupt Sense Control 0 Bit 1
		670
		671	; EIMSK - External Interrupt Mask Register
		672	.equ INT0 = 0 ; External Interrupt Request 0 Enable
		673	.equ PCIE0 = 4 ; Pin Change Interrupt Enable 0
		674	.equ PCIE1 = 5 ; Pin Change Interrupt Enable 1
		675	.equ PCIE2 = 6 ; Pin Change Interrupt Enable 2
		676	.equ PCIE3 = 7 ; Pin Change Interrupt Enable 3
		677
		678	; EIFR - External Interrupt Flag Register
		679	.equ INTF0 = 0 ; External Interrupt Flag 0
		680	.equ PCIF0 = 4 ; Pin Change Interrupt Flag 0
		681	.equ PCIF1 = 5 ; Pin Change Interrupt Flag 1
		682	.equ PCIF2 = 6 ; Pin Change Interrupt Flag 2
		683	.equ PCIF3 = 7 ; Pin Change Interrupt Flag 3
		684
		685
		686	; *** EEPROM *********************
		687	; EEDR - EEPROM Data Register
		688	.equ EEDR0 = 0 ; EEPROM Data Register bit 0
		689	.equ EEDR1 = 1 ; EEPROM Data Register bit 1
		690	.equ EEDR2 = 2 ; EEPROM Data Register bit 2
		691	.equ EEDR3 = 3 ; EEPROM Data Register bit 3
		692	.equ EEDR4 = 4 ; EEPROM Data Register bit 4
		693	.equ EEDR5 = 5 ; EEPROM Data Register bit 5
		694	.equ EEDR6 = 6 ; EEPROM Data Register bit 6
		695	.equ EEDR7 = 7 ; EEPROM Data Register bit 7
		696
		697	; EECR - EEPROM Control Register
		698	.equ EERE = 0 ; EEPROM Read Enable
		699	.equ EEWE = 1 ; EEPROM Write Enable
		700	.equ EEMWE = 2 ; EEPROM Master Write Enable
		701	.equ EERIE = 3 ; EEPROM Ready Interrupt Enable
		702
		703
		704	; *** PORTA **********************
		705	; PORTA - Port A Data Register
		706	.equ PORTA0 = 0 ; Port A Data Register bit 0
		707	.equ PA0 = 0 ; For compatibility
		708	.equ PORTA1 = 1 ; Port A Data Register bit 1
		709	.equ PA1 = 1 ; For compatibility
		710	.equ PORTA2 = 2 ; Port A Data Register bit 2
		711	.equ PA2 = 2 ; For compatibility
		712	.equ PORTA3 = 3 ; Port A Data Register bit 3
		713	.equ PA3 = 3 ; For compatibility
		714	.equ PORTA4 = 4 ; Port A Data Register bit 4
		715	.equ PA4 = 4 ; For compatibility
		716	.equ PORTA5 = 5 ; Port A Data Register bit 5
		717	.equ PA5 = 5 ; For compatibility
		718	.equ PORTA6 = 6 ; Port A Data Register bit 6
		719	.equ PA6 = 6 ; For compatibility
		720	.equ PORTA7 = 7 ; Port A Data Register bit 7
		721	.equ PA7 = 7 ; For compatibility
		722
		723	; DDRA - Port A Data Direction Register
		724	.equ DDA0 = 0 ; Data Direction Register, Port A, bit 0
		725	.equ DDA1 = 1 ; Data Direction Register, Port A, bit 1
		726	.equ DDA2 = 2 ; Data Direction Register, Port A, bit 2
		727	.equ DDA3 = 3 ; Data Direction Register, Port A, bit 3
		728	.equ DDA4 = 4 ; Data Direction Register, Port A, bit 4
		729	.equ DDA5 = 5 ; Data Direction Register, Port A, bit 5
		730	.equ DDA6 = 6 ; Data Direction Register, Port A, bit 6
		731	.equ DDA7 = 7 ; Data Direction Register, Port A, bit 7
		732
		733	; PINA - Port A Input Pins
		734	.equ PINA0 = 0 ; Input Pins, Port A bit 0
		735	.equ PINA1 = 1 ; Input Pins, Port A bit 1
		736	.equ PINA2 = 2 ; Input Pins, Port A bit 2
		737	.equ PINA3 = 3 ; Input Pins, Port A bit 3
		738	.equ PINA4 = 4 ; Input Pins, Port A bit 4
		739	.equ PINA5 = 5 ; Input Pins, Port A bit 5
		740	.equ PINA6 = 6 ; Input Pins, Port A bit 6
		741	.equ PINA7 = 7 ; Input Pins, Port A bit 7
		742
		743
		744	; *** PORTB **********************
		745	; PORTB - Port B Data Register
		746	.equ PORTB0 = 0 ; Port B Data Register bit 0
		747	.equ PB0 = 0 ; For compatibility
		748	.equ PORTB1 = 1 ; Port B Data Register bit 1
		749	.equ PB1 = 1 ; For compatibility
		750	.equ PORTB2 = 2 ; Port B Data Register bit 2
		751	.equ PB2 = 2 ; For compatibility
		752	.equ PORTB3 = 3 ; Port B Data Register bit 3
		753	.equ PB3 = 3 ; For compatibility
		754	.equ PORTB4 = 4 ; Port B Data Register bit 4
		755	.equ PB4 = 4 ; For compatibility
		756	.equ PORTB5 = 5 ; Port B Data Register bit 5
		757	.equ PB5 = 5 ; For compatibility
		758	.equ PORTB6 = 6 ; Port B Data Register bit 6
		759	.equ PB6 = 6 ; For compatibility
		760	.equ PORTB7 = 7 ; Port B Data Register bit 7
		761	.equ PB7 = 7 ; For compatibility
		762
		763	; DDRB - Port B Data Direction Register
		764	.equ DDB0 = 0 ; Port B Data Direction Register bit 0
		765	.equ DDB1 = 1 ; Port B Data Direction Register bit 1
		766	.equ DDB2 = 2 ; Port B Data Direction Register bit 2
		767	.equ DDB3 = 3 ; Port B Data Direction Register bit 3
		768	.equ DDB4 = 4 ; Port B Data Direction Register bit 4
		769	.equ DDB5 = 5 ; Port B Data Direction Register bit 5
		770	.equ DDB6 = 6 ; Port B Data Direction Register bit 6
		771	.equ DDB7 = 7 ; Port B Data Direction Register bit 7
		772
		773	; PINB - Port B Input Pins
		774	.equ PINB0 = 0 ; Port B Input Pins bit 0
		775	.equ PINB1 = 1 ; Port B Input Pins bit 1
		776	.equ PINB2 = 2 ; Port B Input Pins bit 2
		777	.equ PINB3 = 3 ; Port B Input Pins bit 3
		778	.equ PINB4 = 4 ; Port B Input Pins bit 4
		779	.equ PINB5 = 5 ; Port B Input Pins bit 5
		780	.equ PINB6 = 6 ; Port B Input Pins bit 6
		781	.equ PINB7 = 7 ; Port B Input Pins bit 7
		782
		783
		784	; *** PORTC **********************
		785	; PORTC - Port C Data Register
		786	.equ PORTC0 = 0 ; Port C Data Register bit 0
		787	.equ PC0 = 0 ; For compatibility
		788	.equ PORTC1 = 1 ; Port C Data Register bit 1
		789	.equ PC1 = 1 ; For compatibility
		790	.equ PORTC2 = 2 ; Port C Data Register bit 2
		791	.equ PC2 = 2 ; For compatibility
		792	.equ PORTC3 = 3 ; Port C Data Register bit 3
		793	.equ PC3 = 3 ; For compatibility
		794	.equ PORTC4 = 4 ; Port C Data Register bit 4
		795	.equ PC4 = 4 ; For compatibility
		796	.equ PORTC5 = 5 ; Port C Data Register bit 5
		797	.equ PC5 = 5 ; For compatibility
		798	.equ PORTC6 = 6 ; Port C Data Register bit 6
		799	.equ PC6 = 6 ; For compatibility
		800	.equ PORTC7 = 7 ; Port C Data Register bit 7
		801	.equ PC7 = 7 ; For compatibility
		802
		803	; DDRC - Port C Data Direction Register
		804	.equ DDC0 = 0 ; Port C Data Direction Register bit 0
		805	.equ DDC1 = 1 ; Port C Data Direction Register bit 1
		806	.equ DDC2 = 2 ; Port C Data Direction Register bit 2
		807	.equ DDC3 = 3 ; Port C Data Direction Register bit 3
		808	.equ DDC4 = 4 ; Port C Data Direction Register bit 4
		809	.equ DDC5 = 5 ; Port C Data Direction Register bit 5
		810	.equ DDC6 = 6 ; Port C Data Direction Register bit 6
		811	.equ DDC7 = 7 ; Port C Data Direction Register bit 7
		812
		813	; PINC - Port C Input Pins
		814	.equ PINC0 = 0 ; Port C Input Pins bit 0
		815	.equ PINC1 = 1 ; Port C Input Pins bit 1
		816	.equ PINC2 = 2 ; Port C Input Pins bit 2
		817	.equ PINC3 = 3 ; Port C Input Pins bit 3
		818	.equ PINC4 = 4 ; Port C Input Pins bit 4
		819	.equ PINC5 = 5 ; Port C Input Pins bit 5
		820	.equ PINC6 = 6 ; Port C Input Pins bit 6
		821	.equ PINC7 = 7 ; Port C Input Pins bit 7
		822
		823
		824	; *** PORTD **********************
		825	; PORTD - Port D Data Register
		826	.equ PORTD0 = 0 ; Port D Data Register bit 0
		827	.equ PD0 = 0 ; For compatibility
		828	.equ PORTD1 = 1 ; Port D Data Register bit 1
		829	.equ PD1 = 1 ; For compatibility
		830	.equ PORTD2 = 2 ; Port D Data Register bit 2
		831	.equ PD2 = 2 ; For compatibility
		832	.equ PORTD3 = 3 ; Port D Data Register bit 3
		833	.equ PD3 = 3 ; For compatibility
		834	.equ PORTD4 = 4 ; Port D Data Register bit 4
		835	.equ PD4 = 4 ; For compatibility
		836	.equ PORTD5 = 5 ; Port D Data Register bit 5
		837	.equ PD5 = 5 ; For compatibility
		838	.equ PORTD6 = 6 ; Port D Data Register bit 6
		839	.equ PD6 = 6 ; For compatibility
		840	.equ PORTD7 = 7 ; Port D Data Register bit 7
		841	.equ PD7 = 7 ; For compatibility
		842
		843	; DDRD - Port D Data Direction Register
		844	.equ DDD0 = 0 ; Port D Data Direction Register bit 0
		845	.equ DDD1 = 1 ; Port D Data Direction Register bit 1
		846	.equ DDD2 = 2 ; Port D Data Direction Register bit 2
		847	.equ DDD3 = 3 ; Port D Data Direction Register bit 3
		848	.equ DDD4 = 4 ; Port D Data Direction Register bit 4
		849	.equ DDD5 = 5 ; Port D Data Direction Register bit 5
		850	.equ DDD6 = 6 ; Port D Data Direction Register bit 6
		851	.equ DDD7 = 7 ; Port D Data Direction Register bit 7
		852
		853	; PIND - Port D Input Pins
		854	.equ PIND0 = 0 ; Port D Input Pins bit 0
		855	.equ PIND1 = 1 ; Port D Input Pins bit 1
		856	.equ PIND2 = 2 ; Port D Input Pins bit 2
		857	.equ PIND3 = 3 ; Port D Input Pins bit 3
		858	.equ PIND4 = 4 ; Port D Input Pins bit 4
		859	.equ PIND5 = 5 ; Port D Input Pins bit 5
		860	.equ PIND6 = 6 ; Port D Input Pins bit 6
		861	.equ PIND7 = 7 ; Port D Input Pins bit 7
		862
		863
		864	; *** PORTE **********************
		865	; PORTE - Data Register, Port E
		866	.equ PORTE0 = 0 ;
		867	.equ PE0 = 0 ; For compatibility
		868	.equ PORTE1 = 1 ;
		869	.equ PE1 = 1 ; For compatibility
		870	.equ PORTE2 = 2 ;
		871	.equ PE2 = 2 ; For compatibility
		872	.equ PORTE3 = 3 ;
		873	.equ PE3 = 3 ; For compatibility
		874	.equ PORTE4 = 4 ;
		875	.equ PE4 = 4 ; For compatibility
		876	.equ PORTE5 = 5 ;
		877	.equ PE5 = 5 ; For compatibility
		878	.equ PORTE6 = 6 ;
		879	.equ PE6 = 6 ; For compatibility
		880	.equ PORTE7 = 7 ;
		881	.equ PE7 = 7 ; For compatibility
		882
		883	; DDRE - Data Direction Register, Port E
		884	.equ DDE0 = 0 ;
		885	.equ DDE1 = 1 ;
		886	.equ DDE2 = 2 ;
		887	.equ DDE3 = 3 ;
		888	.equ DDE4 = 4 ;
		889	.equ DDE5 = 5 ;
		890	.equ DDE6 = 6 ;
		891	.equ DDE7 = 7 ;
		892
		893	; PINE - Input Pins, Port E
		894	.equ PINE0 = 0 ;
		895	.equ PINE1 = 1 ;
		896	.equ PINE2 = 2 ;
		897	.equ PINE3 = 3 ;
		898	.equ PINE4 = 4 ;
		899	.equ PINE5 = 5 ;
		900	.equ PINE6 = 6 ;
		901	.equ PINE7 = 7 ;
		902
		903
		904	; *** PORTF **********************
		905	; PORTF - Data Register, Port F
		906	.equ PORTF0 = 0 ;
		907	.equ PF0 = 0 ; For compatibility
		908	.equ PORTF1 = 1 ;
		909	.equ PF1 = 1 ; For compatibility
		910	.equ PORTF2 = 2 ;
		911	.equ PF2 = 2 ; For compatibility
		912	.equ PORTF3 = 3 ;
		913	.equ PF3 = 3 ; For compatibility
		914	.equ PORTF4 = 4 ;
		915	.equ PF4 = 4 ; For compatibility
		916	.equ PORTF5 = 5 ;
		917	.equ PF5 = 5 ; For compatibility
		918	.equ PORTF6 = 6 ;
		919	.equ PF6 = 6 ; For compatibility
		920	.equ PORTF7 = 7 ;
		921	.equ PF7 = 7 ; For compatibility
		922
		923	; DDRF - Data Direction Register, Port F
		924	.equ DDF0 = 0 ;
		925	.equ DDF1 = 1 ;
		926	.equ DDF2 = 2 ;
		927	.equ DDF3 = 3 ;
		928	.equ DDF4 = 4 ;
		929	.equ DDF5 = 5 ;
		930	.equ DDF6 = 6 ;
		931	.equ DDF7 = 7 ;
		932
		933	; PINF - Input Pins, Port F
		934	.equ PINF0 = 0 ;
		935	.equ PINF1 = 1 ;
		936	.equ PINF2 = 2 ;
		937	.equ PINF3 = 3 ;
		938	.equ PINF4 = 4 ;
		939	.equ PINF5 = 5 ;
		940	.equ PINF6 = 6 ;
		941	.equ PINF7 = 7 ;
		942
		943
		944	; *** PORTG **********************
		945	; PORTG - Port G Data Register
		946	.equ PORTG0 = 0 ;
		947	.equ PG0 = 0 ; For compatibility
		948	.equ PORTG1 = 1 ;
		949	.equ PG1 = 1 ; For compatibility
		950	.equ PORTG2 = 2 ;
		951	.equ PG2 = 2 ; For compatibility
		952	.equ PORTG3 = 3 ;
		953	.equ PG3 = 3 ; For compatibility
		954	.equ PORTG4 = 4 ;
		955	.equ PG4 = 4 ; For compatibility
		956
		957	; DDRG - Port G Data Direction Register
		958	.equ DDG0 = 0 ;
		959	.equ DDG1 = 1 ;
		960	.equ DDG2 = 2 ;
		961	.equ DDG3 = 3 ;
		962	.equ DDG4 = 4 ;
		963
		964	; PING - Port G Input Pins
		965	.equ PING0 = 0 ;
		966	.equ PING1 = 1 ;
		967	.equ PING2 = 2 ;
		968	.equ PING3 = 3 ;
		969	.equ PING4 = 4 ;
		970	.equ PING5 = 5 ;
		971
		972
		973	; *** TIMER_COUNTER_0 ************
		974	; TCCR0A - Timer/Counter0 Control Register
		975	.equ CS00 = 0 ; Clock Select 1
		976	.equ CS01 = 1 ; Clock Select 1
		977	.equ CS02 = 2 ; Clock Select 2
		978	.equ WGM01 = 3 ; Waveform Generation Mode 1
		979	.equ COM0A0 = 4 ; Compare match Output Mode 0
		980	.equ COM0A1 = 5 ; Compare Match Output Mode 1
		981	.equ WGM00 = 6 ; Waveform Generation Mode 0
		982	.equ FOC0A = 7 ; Force Output Compare
		983
		984	; TCNT0 - Timer/Counter0
		985	.equ TCNT0_0 = 0 ;
		986	.equ TCNT0_1 = 1 ;
		987	.equ TCNT0_2 = 2 ;
		988	.equ TCNT0_3 = 3 ;
		989	.equ TCNT0_4 = 4 ;
		990	.equ TCNT0_5 = 5 ;
		991	.equ TCNT0_6 = 6 ;
		992	.equ TCNT0_7 = 7 ;
		993
		994	; OCR0A - Timer/Counter0 Output Compare Register
		995	.equ OCR0A0 = 0 ;
		996	.equ OCR0A1 = 1 ;
		997	.equ OCR0A2 = 2 ;
		998	.equ OCR0A3 = 3 ;
		999	.equ OCR0A4 = 4 ;
		1000	.equ OCR0A5 = 5 ;
		1001	.equ OCR0A6 = 6 ;
		1002	.equ OCR0A7 = 7 ;
		1003
		1004	; TIMSK0 - Timer/Counter0 Interrupt Mask Register
		1005	.equ TOIE0 = 0 ; Timer/Counter0 Overflow Interrupt Enable
		1006	.equ OCIE0A = 1 ; Timer/Counter0 Output Compare Match Interrupt Enable
		1007
		1008	; TIFR0 - Timer/Counter0 Interrupt Flag register
		1009	.equ TOV0 = 0 ; Timer/Counter0 Overflow Flag
		1010	.equ OCF0A = 1 ; Timer/Counter0 Output Compare Flag 0
		1011
		1012	; GTCCR - General Timer/Control Register
		1013	.equ PSR310 = 0 ; Prescaler Reset Timer/Counter1 and Timer/Counter0
		1014	.equ PSR10 = PSR310 ; For compatibility
		1015	.equ PSR0 = PSR310 ; For compatibility
		1016	.equ PSR1 = PSR310 ; For compatibility
		1017	.equ PSR3 = PSR310 ; For compatibility
		1018	.equ TSM = 7 ; Timer/Counter Synchronization Mode
		1019
		1020
		1021	; *** TIMER_COUNTER_1 ************
		1022	; TIMSK1 - Timer/Counter1 Interrupt Mask Register
		1023	.equ TOIE1 = 0 ; Timer/Counter1 Overflow Interrupt Enable
		1024	.equ OCIE1A = 1 ; Timer/Counter1 Output Compare A Match Interrupt Enable
		1025	.equ OCIE1B = 2 ; Timer/Counter1 Output Compare B Match Interrupt Enable
		1026	.equ ICIE1 = 5 ; Timer/Counter1 Input Capture Interrupt Enable
		1027
		1028	; TIFR1 - Timer/Counter1 Interrupt Flag register
		1029	.equ TOV1 = 0 ; Timer/Counter1 Overflow Flag
		1030	.equ OCF1A = 1 ; Output Compare Flag 1A
		1031	.equ OCF1B = 2 ; Output Compare Flag 1B
		1032	.equ ICF1 = 5 ; Input Capture Flag 1
		1033
		1034	; TCCR1A - Timer/Counter1 Control Register A
		1035	.equ WGM10 = 0 ; Waveform Generation Mode
		1036	.equ WGM11 = 1 ; Waveform Generation Mode
		1037	.equ COM1B0 = 4 ; Compare Output Mode 1B, bit 0
		1038	.equ COM1B1 = 5 ; Compare Output Mode 1B, bit 1
		1039	.equ COM1A0 = 6 ; Compare Output Mode 1A, bit 0
		1040	.equ COM1A1 = 7 ; Compare Output Mode 1A, bit 1
		1041
		1042	; TCCR1B - Timer/Counter1 Control Register B
		1043	.equ CS10 = 0 ; Prescaler source of Timer/Counter 1
		1044	.equ CS11 = 1 ; Prescaler source of Timer/Counter 1
		1045	.equ CS12 = 2 ; Prescaler source of Timer/Counter 1
		1046	.equ WGM12 = 3 ; Waveform Generation Mode
		1047	.equ WGM13 = 4 ; Waveform Generation Mode
		1048	.equ ICES1 = 6 ; Input Capture 1 Edge Select
		1049	.equ ICNC1 = 7 ; Input Capture 1 Noise Canceler
		1050
		1051	; TCCR1C - Timer/Counter 1 Control Register C
		1052	.equ FOC1B = 6 ; Force Output Compare 1B
		1053	.equ FOC1A = 7 ; Force Output Compare 1A
		1054
		1055
		1056	; *** TIMER_COUNTER_2 ************
		1057	; TIMSK2 - Timer/Counter2 Interrupt Mask register
		1058	.equ TOIE2 = 0 ; Timer/Counter2 Overflow Interrupt Enable
		1059	.equ OCIE2A = 1 ; Timer/Counter2 Output Compare Match Interrupt Enable
		1060
		1061	; TIFR2 - Timer/Counter2 Interrupt Flag Register
		1062	.equ TOV2 = 0 ; Timer/Counter2 Overflow Flag
		1063	.equ OCF2A = 1 ; Timer/Counter2 Output Compare Flag 2
		1064
		1065	; TCCR2A - Timer/Counter2 Control Register
		1066	.equ CS20 = 0 ; Clock Select bit 0
		1067	.equ CS21 = 1 ; Clock Select bit 1
		1068	.equ CS22 = 2 ; Clock Select bit 2
		1069	.equ WGM21 = 3 ; Waveform Generation Mode
		1070	.equ COM2A0 = 4 ; Compare Output Mode bit 0
		1071	.equ COM2A1 = 5 ; Compare Output Mode bit 1
		1072	.equ WGM20 = 6 ; Waveform Generation Mode
		1073	.equ FOC2A = 7 ; Force Output Compare A
		1074
		1075	; TCNT2 - Timer/Counter2
		1076	.equ TCNT2_0 = 0 ; Timer/Counter 2 bit 0
		1077	.equ TCNT2_1 = 1 ; Timer/Counter 2 bit 1
		1078	.equ TCNT2_2 = 2 ; Timer/Counter 2 bit 2
		1079	.equ TCNT2_3 = 3 ; Timer/Counter 2 bit 3
		1080	.equ TCNT2_4 = 4 ; Timer/Counter 2 bit 4
		1081	.equ TCNT2_5 = 5 ; Timer/Counter 2 bit 5
		1082	.equ TCNT2_6 = 6 ; Timer/Counter 2 bit 6
		1083	.equ TCNT2_7 = 7 ; Timer/Counter 2 bit 7
		1084
		1085	; OCR2A - Timer/Counter2 Output Compare Register
		1086	.equ OCR2A0 = 0 ; Timer/Counter2 Output Compare Register Bit 0
		1087	.equ OCR2A1 = 1 ; Timer/Counter2 Output Compare Register Bit 1
		1088	.equ OCR2A2 = 2 ; Timer/Counter2 Output Compare Register Bit 2
		1089	.equ OCR2A3 = 3 ; Timer/Counter2 Output Compare Register Bit 3
		1090	.equ OCR2A4 = 4 ; Timer/Counter2 Output Compare Register Bit 4
		1091	.equ OCR2A5 = 5 ; Timer/Counter2 Output Compare Register Bit 5
		1092	.equ OCR2A6 = 6 ; Timer/Counter2 Output Compare Register Bit 6
		1093	.equ OCR2A7 = 7 ; Timer/Counter2 Output Compare Register Bit 7
		1094
		1095	; GTCCR - General Timer/Counter Control Register
		1096	.equ PSR2 = 1 ; Prescaler Reset Timer/Counter2
		1097
		1098	; ASSR - Asynchronous Status Register
		1099	.equ TCR2UB = 0 ; TCR2UB: Timer/Counter Control Register2 Update Busy
		1100	.equ OCR2UB = 1 ; Output Compare Register2 Update Busy
		1101	.equ TCN2UB = 2 ; TCN2UB: Timer/Counter2 Update Busy
		1102	.equ AS2 = 3 ; AS2: Asynchronous Timer/Counter2
		1103	.equ EXCLK = 4 ; Enable External Clock Interrupt
		1104
		1105
		1106	; *** WATCHDOG *******************
		1107	; WDTCR - Watchdog Timer Control Register
		1108	.equ WDTCSR = WDTCR ; For compatibility
		1109	.equ WDP0 = 0 ; Watch Dog Timer Prescaler bit 0
		1110	.equ WDP1 = 1 ; Watch Dog Timer Prescaler bit 1
		1111	.equ WDP2 = 2 ; Watch Dog Timer Prescaler bit 2
		1112	.equ WDE = 3 ; Watch Dog Enable
		1113	.equ WDCE = 4 ; Watchdog Change Enable
		1114	.equ WDTOE = WDCE ; For compatibility
		1115
		1116
		1117	; *** BOOT_LOAD ******************
		1118	; SPMCSR - Store Program Memory Control Register
		1119	.equ SPMCR = SPMCSR ; For compatibility
		1120	.equ SPMEN = 0 ; Store Program Memory Enable
		1121	.equ PGERS = 1 ; Page Erase
		1122	.equ PGWRT = 2 ; Page Write
		1123	.equ BLBSET = 3 ; Boot Lock Bit Set
		1124	.equ RWWSRE = 4 ; Read While Write section read enable
		1125	.equ ASRE = RWWSRE ; For compatibility
		1126	.equ RWWSB = 6 ; Read While Write Section Busy
		1127	.equ ASB = RWWSB ; For compatibility
		1128	.equ SPMIE = 7 ; SPM Interrupt Enable
		1129
		1130
		1131
		1132	; *** LOCKSBITS ******************************************************
		1133	.equ LB1 = 0 ; Lock bit
		1134	.equ LB2 = 1 ; Lock bit
		1135	.equ BLB01 = 2 ; Boot Lock bit
		1136	.equ BLB02 = 3 ; Boot Lock bit
		1137	.equ BLB11 = 4 ; Boot lock bit
		1138	.equ BLB12 = 5 ; Boot lock bit
		1139
		1140
		1141	; *** FUSES **********************************************************
		1142	; LOW fuse bits
		1143	.equ CKSEL0 = 0 ; Select Clock Source
		1144	.equ CKSEL1 = 1 ; Select Clock Source
		1145	.equ CKSEL2 = 2 ; Select Clock Source
		1146	.equ CKSEL3 = 3 ; Select Clock Source
		1147	.equ SUT0 = 4 ; Select start-up time
		1148	.equ SUT1 = 5 ; Select start-up time
		1149	.equ CKOUT = 6 ; Oscillator options
		1150	.equ CLKDIV8 = 7 ; Divide clock by 8
		1151
		1152	; HIGH fuse bits
		1153	.equ BOOTRST = 0 ; Select Reset Vector
		1154	.equ BOOTSZ0 = 1 ; Select Boot Size
		1155	.equ BOOTSZ1 = 2 ; Select Boot Size
		1156	.equ EESAVE = 3 ; EEPROM memory is preserved through chip erase
		1157	.equ WDTON = 4 ; Watchdog timer always on
		1158	.equ SPIEN = 5 ; Enable Serial programming and Data Downloading
		1159	.equ JTAGEN = 6 ; Enable JTAG
		1160	.equ OCDEN = 7 ; Enable OCD
		1161
		1162	; EXTENDED fuse bits
		1163	.equ RSTDISBL = 0 ; External Reset Disable
		1164	.equ BODLEVEL0 = 1 ; Brown-out Detector trigger level
		1165	.equ BODLEVEL1 = 2 ; Brown-out Detector trigger level
		1166
		1167
		1168
		1169	; *** CPU REGISTER DEFINITIONS ***************************************
		1170	.def XH = r27
		1171	.def XL = r26
		1172	.def YH = r29
		1173	.def YL = r28
		1174	.def ZH = r31
		1175	.def ZL = r30
		1176
		1177
		1178
		1179	; *** DATA MEMORY DECLARATIONS ***************************************
		1180	.equ FLASHEND = 0x7fff ; Note: Word address
		1181	.equ IOEND = 0x00ff
		1182	.equ SRAM_START = 0x0100
		1183	.equ SRAM_SIZE = 4096
		1184	.equ RAMEND = 0x10ff
		1185	.equ XRAMEND = 0x0000
		1186	.equ E2END = 0x07ff
		1187	.equ EEPROMEND = 0x07ff
		1188	.equ EEADRBITS = 11
		1189	#pragma AVRPART MEMORY PROG_FLASH 65536
		1190	#pragma AVRPART MEMORY EEPROM 2048
		1191	#pragma AVRPART MEMORY INT_SRAM SIZE 4096
		1192	#pragma AVRPART MEMORY INT_SRAM START_ADDR 0x100
		1193
		1194
		1195
		1196	; *** BOOTLOADER DECLARATIONS ****************************************
		1197	.equ NRWW_START_ADDR = 0x7000
		1198	.equ NRWW_STOP_ADDR = 0x7fff
		1199	.equ RWW_START_ADDR = 0x0
		1200	.equ RWW_STOP_ADDR = 0x6fff
		1201	.equ PAGESIZE = 128
		1202	.equ FIRSTBOOTSTART = 0x7e00
		1203	.equ SECONDBOOTSTART = 0x7c00
		1204	.equ THIRDBOOTSTART = 0x7800
		1205	.equ FOURTHBOOTSTART = 0x7000
		1206	.equ SMALLBOOTSTART = FIRSTBOOTSTART
		1207	.equ LARGEBOOTSTART = FOURTHBOOTSTART
		1208
		1209
		1210
		1211	; *** INTERRUPT VECTORS **********************************************
		1212	.equ INT0addr = 0x0002 ; External Interrupt Request 0
		1213	.equ PCI0addr = 0x0004 ; Pin Change Interrupt Request 0
		1214	.equ PCI1addr = 0x0006 ; Pin Change Interrupt Request 1
		1215	.equ OC2addr = 0x0008 ; Timer/Counter2 Compare Match
		1216	.equ OVF2addr = 0x000a ; Timer/Counter2 Overflow
		1217	.equ ICP1addr = 0x000c ; Timer/Counter1 Capture Event
		1218	.equ OC1Aaddr = 0x000e ; Timer/Counter1 Compare Match A
		1219	.equ OC1Baddr = 0x0010 ; Timer/Counter Compare Match B
		1220	.equ OVF1addr = 0x0012 ; Timer/Counter1 Overflow
		1221	.equ OC0addr = 0x0014 ; Timer/Counter0 Compare Match
		1222	.equ OVF0addr = 0x0016 ; Timer/Counter0 Overflow
		1223	.equ SPIaddr = 0x0018 ; SPI Serial Transfer Complete
		1224	.equ URXC0addr = 0x001a ; USART0, Rx Complete
		1225	.equ URXCaddr = 0x001a ; For compatibility
		1226	.equ UDRE0addr = 0x001c ; USART0 Data register Empty
		1227	.equ UDREaddr = 0x001c ; For compatibility
		1228	.equ UTXC0addr = 0x001e ; USART0, Tx Complete
		1229	.equ UTXCaddr = 0x001e ; For compatibility
		1230	.equ USI_STARTaddr = 0x0020 ; USI Start Condition
		1231	.equ USI_OVFaddr = 0x0022 ; USI Overflow
		1232	.equ ACIaddr = 0x0024 ; Analog Comparator
		1233	.equ ADCCaddr = 0x0026 ; ADC Conversion Complete
		1234	.equ ERDYaddr = 0x0028 ; EEPROM Ready
		1235	.equ SPMRaddr = 0x002a ; Store Program Memory Read
		1236	.equ LCDSFaddr = 0x002c ; LCD Start of Frame
		1237
		1238	.equ INT_VECTORS_SIZE = 46 ; size in words
		1239
		1240	#endif /* _M649DEF_INC_ */
		1241
		1242	; *** END OF FILE ****************************************************

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(root)/contrib/toolchain/avra/includes/m649def.inc – Rev 6400