WebSVN – Kolibri OS – Blame – /contrib/toolchain/avra/includes/m165def.inc

Rev	Author	Line No.	Line
6400	punk_joker	1	;*** THIS IS A MACHINE GENERATED FILE - DO NOT EDIT ******************
		2	;*** Created: 2005-01-11 10:30 *** Source: ATmega165.xml *********
		3	;*************************************************************************
		4	;* A P P L I C A T I O N N O T E F O R T H E A V R F A M I L Y
		5	;*
		6	;* Number : AVR000
		7	;* File Name : "m165def.inc"
		8	;* Title : Register/Bit Definitions for the ATmega165
		9	;* Date : 2005-01-11
		10	;* Version : 2.14
		11	;* Support E-mail : avr@atmel.com
		12	;* Target MCU : ATmega165
		13	;*
		14	;* DESCRIPTION
		15	;* When including this file in the assembly program file, all I/O register
		16	;* names and I/O register bit names appearing in the data book can be used.
		17	;* In addition, the six registers forming the three data pointers X, Y and
		18	;* Z have been assigned names XL - ZH. Highest RAM address for Internal
		19	;* SRAM is also defined
		20	;*
		21	;* The Register names are represented by their hexadecimal address.
		22	;*
		23	;* The Register Bit names are represented by their bit number (0-7).
		24	;*
		25	;* Please observe the difference in using the bit names with instructions
		26	;* such as "sbr"/"cbr" (set/clear bit in register) and "sbrs"/"sbrc"
		27	;* (skip if bit in register set/cleared). The following example illustrates
		28	;* this:
		29	;*
		30	;* in r16,PORTB ;read PORTB latch
		31	;* sbr r16,(1<
		32	;* out PORTB,r16 ;output to PORTB
		33	;*
		34	;* in r16,TIFR ;read the Timer Interrupt Flag Register
		35	;* sbrc r16,TOV0 ;test the overflow flag (use bit#)
		36	;* rjmp TOV0_is_set ;jump if set
		37	;* ... ;otherwise do something else
		38	;*************************************************************************
		39
		40	#ifndef _M165DEF_INC_
		41	#define _M165DEF_INC_
		42
		43
		44	#pragma partinc 0
		45
		46	; *** SPECIFY DEVICE *************************************************
		47	.device ATmega165
		48	#pragma AVRPART ADMIN PART_NAME ATmega165
		49	.equ SIGNATURE_000 = 0x1e
		50	.equ SIGNATURE_001 = 0x94
		51	.equ SIGNATURE_002 = 0x07
		52
		53	#pragma AVRPART CORE CORE_VERSION V2E
		54
		55
		56	; *** I/O REGISTER DEFINITIONS ***************************************
		57	; NOTE:
		58	; Definitions marked "MEMORY MAPPED"are extended I/O ports
		59	; and cannot be used with IN/OUT instructions
		60	.equ UDR = 0xc6 ; MEMORY MAPPED
		61	.equ UBRRH = 0xc5 ; MEMORY MAPPED
		62	.equ UBRRL = 0xc4 ; MEMORY MAPPED
		63	.equ UCSRC = 0xc2 ; MEMORY MAPPED
		64	.equ UCSRB = 0xc1 ; MEMORY MAPPED
		65	.equ UCSRA = 0xc0 ; MEMORY MAPPED
		66	.equ USIDR = 0xba ; MEMORY MAPPED
		67	.equ USISR = 0xb9 ; MEMORY MAPPED
		68	.equ USICR = 0xb8 ; MEMORY MAPPED
		69	.equ ASSR = 0xb6 ; MEMORY MAPPED
		70	.equ OCR2A = 0xb3 ; MEMORY MAPPED
		71	.equ TCNT2 = 0xb2 ; MEMORY MAPPED
		72	.equ TCCR2B = 0xb1 ; MEMORY MAPPED
		73	.equ TCCR2A = 0xb0 ; MEMORY MAPPED
		74	.equ OCR1BH = 0x8b ; MEMORY MAPPED
		75	.equ OCR1BL = 0x8a ; MEMORY MAPPED
		76	.equ OCR1AH = 0x89 ; MEMORY MAPPED
		77	.equ OCR1AL = 0x88 ; MEMORY MAPPED
		78	.equ ICR1H = 0x87 ; MEMORY MAPPED
		79	.equ ICR1L = 0x86 ; MEMORY MAPPED
		80	.equ TCNT1H = 0x85 ; MEMORY MAPPED
		81	.equ TCNT1L = 0x84 ; MEMORY MAPPED
		82	.equ TCCR1C = 0x82 ; MEMORY MAPPED
		83	.equ TCCR1B = 0x81 ; MEMORY MAPPED
		84	.equ TCCR1A = 0x80 ; MEMORY MAPPED
		85	.equ DIDR1 = 0x7f ; MEMORY MAPPED
		86	.equ DIDR0 = 0x7e ; MEMORY MAPPED
		87	.equ ADMUX = 0x7c ; MEMORY MAPPED
		88	.equ ADCSRB = 0x7b ; MEMORY MAPPED
		89	.equ ADCSRA = 0x7a ; MEMORY MAPPED
		90	.equ ADCH = 0x79 ; MEMORY MAPPED
		91	.equ ADCL = 0x78 ; MEMORY MAPPED
		92	.equ TIMSK2 = 0x70 ; MEMORY MAPPED
		93	.equ TIMSK1 = 0x6f ; MEMORY MAPPED
		94	.equ TIMSK0 = 0x6e ; MEMORY MAPPED
		95	.equ PCMSK1 = 0x6c ; MEMORY MAPPED
		96	.equ PCMSK0 = 0x6b ; MEMORY MAPPED
		97	.equ EICRA = 0x69 ; MEMORY MAPPED
		98	.equ OSCCAL = 0x66 ; MEMORY MAPPED
		99	.equ PRR = 0x64 ; MEMORY MAPPED
		100	.equ CLKPR = 0x61 ; MEMORY MAPPED
		101	.equ WDTCR = 0x60 ; MEMORY MAPPED
		102	.equ SREG = 0x3f
		103	.equ SPH = 0x3e
		104	.equ SPL = 0x3d
		105	.equ SPMCSR = 0x37
		106	.equ MCUCR = 0x35
		107	.equ MCUSR = 0x34
		108	.equ SMCR = 0x33
		109	.equ OCDR = 0x31
		110	.equ ACSR = 0x30
		111	.equ SPDR = 0x2e
		112	.equ SPSR = 0x2d
		113	.equ SPCR = 0x2c
		114	.equ GPIOR2 = 0x2b
		115	.equ GPIOR1 = 0x2a
		116	.equ OCR0A = 0x27
		117	.equ TCNT0 = 0x26
		118	.equ TCCR0A = 0x24
		119	.equ GTCCR = 0x23
		120	.equ EEARH = 0x22
		121	.equ EEARL = 0x21
		122	.equ EEDR = 0x20
		123	.equ EECR = 0x1f
		124	.equ GPIOR0 = 0x1e
		125	.equ EIMSK = 0x1d
		126	.equ EIFR = 0x1c
		127	.equ TIFR2 = 0x17
		128	.equ TIFR1 = 0x16
		129	.equ TIFR0 = 0x15
		130	.equ PORTG = 0x14
		131	.equ DDRG = 0x13
		132	.equ PING = 0x12
		133	.equ PORTF = 0x11
		134	.equ DDRF = 0x10
		135	.equ PINF = 0x0f
		136	.equ PORTE = 0x0e
		137	.equ DDRE = 0x0d
		138	.equ PINE = 0x0c
		139	.equ PORTD = 0x0b
		140	.equ DDRD = 0x0a
		141	.equ PIND = 0x09
		142	.equ PORTC = 0x08
		143	.equ DDRC = 0x07
		144	.equ PINC = 0x06
		145	.equ PORTB = 0x05
		146	.equ DDRB = 0x04
		147	.equ PINB = 0x03
		148	.equ PORTA = 0x02
		149	.equ DDRA = 0x01
		150	.equ PINA = 0x00
		151
		152
		153	; *** BIT DEFINITIONS ************************************************
		154
		155	; *** TIMER_COUNTER_0 ************
		156	; TCCR0A - Timer/Counter0 Control Register
		157	.equ CS00 = 0 ; Clock Select 1
		158	.equ CS01 = 1 ; Clock Select 1
		159	.equ CS02 = 2 ; Clock Select 2
		160	.equ WGM01 = 3 ; Waveform Generation Mode 1
		161	.equ COM0A0 = 4 ; Compare match Output Mode 0
		162	.equ COM0A1 = 5 ; Compare Match Output Mode 1
		163	.equ WGM00 = 6 ; Waveform Generation Mode 0
		164	.equ FOC0A = 7 ; Force Output Compare
		165
		166	; TCNT0 - Timer/Counter0
		167	.equ TCNT0_0 = 0 ;
		168	.equ TCNT0_1 = 1 ;
		169	.equ TCNT0_2 = 2 ;
		170	.equ TCNT0_3 = 3 ;
		171	.equ TCNT0_4 = 4 ;
		172	.equ TCNT0_5 = 5 ;
		173	.equ TCNT0_6 = 6 ;
		174	.equ TCNT0_7 = 7 ;
		175
		176	; OCR0A - Timer/Counter0 Output Compare Register
		177	.equ OCR0A0 = 0 ;
		178	.equ OCR0A1 = 1 ;
		179	.equ OCR0A2 = 2 ;
		180	.equ OCR0A3 = 3 ;
		181	.equ OCR0A4 = 4 ;
		182	.equ OCR0A5 = 5 ;
		183	.equ OCR0A6 = 6 ;
		184	.equ OCR0A7 = 7 ;
		185
		186	; TIMSK0 - Timer/Counter0 Interrupt Mask Register
		187	.equ TOIE0 = 0 ; Timer/Counter0 Overflow Interrupt Enable
		188	.equ OCIE0A = 1 ; Timer/Counter0 Output Compare Match Interrupt Enable
		189
		190	; TIFR0 - Timer/Counter0 Interrupt Flag register
		191	.equ TOV0 = 0 ; Timer/Counter0 Overflow Flag
		192	.equ OCF0A = 1 ; Timer/Counter0 Output Compare Flag 0
		193
		194	; GTCCR - General Timer/Control Register
		195	.equ PSR310 = 0 ; Prescaler Reset Timer/Counter1 and Timer/Counter0
		196	.equ PSR10 = PSR310 ; For compatibility
		197	.equ PSR0 = PSR310 ; For compatibility
		198	.equ PSR1 = PSR310 ; For compatibility
		199	.equ PSR3 = PSR310 ; For compatibility
		200	.equ TSM = 7 ; Timer/Counter Synchronization Mode
		201
		202
		203	; *** TIMER_COUNTER_1 ************
		204	; TIMSK1 - Timer/Counter1 Interrupt Mask Register
		205	.equ TOIE1 = 0 ; Timer/Counter1 Overflow Interrupt Enable
		206	.equ OCIE1A = 1 ; Timer/Counter1 Output Compare A Match Interrupt Enable
		207	.equ OCIE1B = 2 ; Timer/Counter1 Output Compare B Match Interrupt Enable
		208	.equ ICIE1 = 5 ; Timer/Counter1 Input Capture Interrupt Enable
		209
		210	; TIFR1 - Timer/Counter1 Interrupt Flag register
		211	.equ TOV1 = 0 ; Timer/Counter1 Overflow Flag
		212	.equ OCF1A = 1 ; Output Compare Flag 1A
		213	.equ OCF1B = 2 ; Output Compare Flag 1B
		214	.equ ICF1 = 5 ; Input Capture Flag 1
		215
		216	; TCCR1A - Timer/Counter1 Control Register A
		217	.equ WGM10 = 0 ; Waveform Generation Mode
		218	.equ WGM11 = 1 ; Waveform Generation Mode
		219	.equ COM1B0 = 4 ; Compare Output Mode 1B, bit 0
		220	.equ COM1B1 = 5 ; Compare Output Mode 1B, bit 1
		221	.equ COM1A0 = 6 ; Compare Output Mode 1A, bit 0
		222	.equ COM1A1 = 7 ; Compare Output Mode 1A, bit 1
		223
		224	; TCCR1B - Timer/Counter1 Control Register B
		225	.equ CS10 = 0 ; Prescaler source of Timer/Counter 1
		226	.equ CS11 = 1 ; Prescaler source of Timer/Counter 1
		227	.equ CS12 = 2 ; Prescaler source of Timer/Counter 1
		228	.equ WGM12 = 3 ; Waveform Generation Mode
		229	.equ WGM13 = 4 ; Waveform Generation Mode
		230	.equ ICES1 = 6 ; Input Capture 1 Edge Select
		231	.equ ICNC1 = 7 ; Input Capture 1 Noise Canceler
		232
		233	; TCCR1C - Timer/Counter 1 Control Register C
		234	.equ FOC1B = 6 ; Force Output Compare 1B
		235	.equ FOC1A = 7 ; Force Output Compare 1A
		236
		237
		238	; *** TIMER_COUNTER_2 ************
		239	; TIMSK2 - Timer/Counter2 Interrupt Mask register
		240	.equ TOIE2 = 0 ; Timer/Counter2 Overflow Interrupt Enable
		241	.equ OCIE2A = 1 ; Timer/Counter2 Output Compare Match Interrupt Enable
		242
		243	; TIFR2 - Timer/Counter2 Interrupt Flag Register
		244	.equ TOV2 = 0 ; Timer/Counter2 Overflow Flag
		245	.equ OCF2A = 1 ; Timer/Counter2 Output Compare Flag 2
		246
		247	; TCCR2A - Timer/Counter2 Control Register
		248	.equ CS20 = 0 ; Clock Select bit 0
		249	.equ CS21 = 1 ; Clock Select bit 1
		250	.equ CS22 = 2 ; Clock Select bit 2
		251	.equ WGM21 = 3 ; Waveform Generation Mode
		252	.equ COM2A0 = 4 ; Compare Output Mode bit 0
		253	.equ COM2A1 = 5 ; Compare Output Mode bit 1
		254	.equ WGM20 = 6 ; Waveform Generation Mode
		255	.equ FOC2A = 7 ; Force Output Compare A
		256
		257	; TCNT2 - Timer/Counter2
		258	.equ TCNT2_0 = 0 ; Timer/Counter 2 bit 0
		259	.equ TCNT2_1 = 1 ; Timer/Counter 2 bit 1
		260	.equ TCNT2_2 = 2 ; Timer/Counter 2 bit 2
		261	.equ TCNT2_3 = 3 ; Timer/Counter 2 bit 3
		262	.equ TCNT2_4 = 4 ; Timer/Counter 2 bit 4
		263	.equ TCNT2_5 = 5 ; Timer/Counter 2 bit 5
		264	.equ TCNT2_6 = 6 ; Timer/Counter 2 bit 6
		265	.equ TCNT2_7 = 7 ; Timer/Counter 2 bit 7
		266
		267	; OCR2A - Timer/Counter2 Output Compare Register
		268	.equ OCR2A0 = 0 ; Timer/Counter2 Output Compare Register Bit 0
		269	.equ OCR2A1 = 1 ; Timer/Counter2 Output Compare Register Bit 1
		270	.equ OCR2A2 = 2 ; Timer/Counter2 Output Compare Register Bit 2
		271	.equ OCR2A3 = 3 ; Timer/Counter2 Output Compare Register Bit 3
		272	.equ OCR2A4 = 4 ; Timer/Counter2 Output Compare Register Bit 4
		273	.equ OCR2A5 = 5 ; Timer/Counter2 Output Compare Register Bit 5
		274	.equ OCR2A6 = 6 ; Timer/Counter2 Output Compare Register Bit 6
		275	.equ OCR2A7 = 7 ; Timer/Counter2 Output Compare Register Bit 7
		276
		277	; GTCCR - General Timer/Counter Control Register
		278	.equ PSR2 = 1 ; Prescaler Reset Timer/Counter2
		279
		280	; ASSR - Asynchronous Status Register
		281	.equ TCR2UB = 0 ; TCR2UB: Timer/Counter Control Register2 Update Busy
		282	.equ OCR2UB = 1 ; Output Compare Register2 Update Busy
		283	.equ TCN2UB = 2 ; TCN2UB: Timer/Counter2 Update Busy
		284	.equ AS2 = 3 ; AS2: Asynchronous Timer/Counter2
		285	.equ EXCLK = 4 ; Enable External Clock Interrupt
		286
		287
		288	; *** WATCHDOG *******************
		289	; WDTCR - Watchdog Timer Control Register
		290	.equ WDTCSR = WDTCR ; For compatibility
		291	.equ WDP0 = 0 ; Watch Dog Timer Prescaler bit 0
		292	.equ WDP1 = 1 ; Watch Dog Timer Prescaler bit 1
		293	.equ WDP2 = 2 ; Watch Dog Timer Prescaler bit 2
		294	.equ WDE = 3 ; Watch Dog Enable
		295	.equ WDCE = 4 ; Watchdog Change Enable
		296	.equ WDTOE = WDCE ; For compatibility
		297
		298
		299	; *** EEPROM *********************
		300	; EEDR - EEPROM Data Register
		301	.equ EEDR0 = 0 ; EEPROM Data Register bit 0
		302	.equ EEDR1 = 1 ; EEPROM Data Register bit 1
		303	.equ EEDR2 = 2 ; EEPROM Data Register bit 2
		304	.equ EEDR3 = 3 ; EEPROM Data Register bit 3
		305	.equ EEDR4 = 4 ; EEPROM Data Register bit 4
		306	.equ EEDR5 = 5 ; EEPROM Data Register bit 5
		307	.equ EEDR6 = 6 ; EEPROM Data Register bit 6
		308	.equ EEDR7 = 7 ; EEPROM Data Register bit 7
		309
		310	; EECR - EEPROM Control Register
		311	.equ EERE = 0 ; EEPROM Read Enable
		312	.equ EEWE = 1 ; EEPROM Write Enable
		313	.equ EEMWE = 2 ; EEPROM Master Write Enable
		314	.equ EEWEE = EEMWE ; For compatibility
		315	.equ EERIE = 3 ; EEPROM Ready Interrupt Enable
		316
		317
		318	; *** SPI ************************
		319	; SPDR - SPI Data Register
		320	.equ SPDR0 = 0 ; SPI Data Register bit 0
		321	.equ SPDR1 = 1 ; SPI Data Register bit 1
		322	.equ SPDR2 = 2 ; SPI Data Register bit 2
		323	.equ SPDR3 = 3 ; SPI Data Register bit 3
		324	.equ SPDR4 = 4 ; SPI Data Register bit 4
		325	.equ SPDR5 = 5 ; SPI Data Register bit 5
		326	.equ SPDR6 = 6 ; SPI Data Register bit 6
		327	.equ SPDR7 = 7 ; SPI Data Register bit 7
		328
		329	; SPSR - SPI Status Register
		330	.equ SPI2X = 0 ; Double SPI Speed Bit
		331	.equ WCOL = 6 ; Write Collision Flag
		332	.equ SPIF = 7 ; SPI Interrupt Flag
		333
		334	; SPCR - SPI Control Register
		335	.equ SPR0 = 0 ; SPI Clock Rate Select 0
		336	.equ SPR1 = 1 ; SPI Clock Rate Select 1
		337	.equ CPHA = 2 ; Clock Phase
		338	.equ CPOL = 3 ; Clock polarity
		339	.equ MSTR = 4 ; Master/Slave Select
		340	.equ DORD = 5 ; Data Order
		341	.equ SPE = 6 ; SPI Enable
		342	.equ SPIE = 7 ; SPI Interrupt Enable
		343
		344
		345	; *** PORTA **********************
		346	; PORTA - Port A Data Register
		347	.equ PORTA0 = 0 ; Port A Data Register bit 0
		348	.equ PA0 = 0 ; For compatibility
		349	.equ PORTA1 = 1 ; Port A Data Register bit 1
		350	.equ PA1 = 1 ; For compatibility
		351	.equ PORTA2 = 2 ; Port A Data Register bit 2
		352	.equ PA2 = 2 ; For compatibility
		353	.equ PORTA3 = 3 ; Port A Data Register bit 3
		354	.equ PA3 = 3 ; For compatibility
		355	.equ PORTA4 = 4 ; Port A Data Register bit 4
		356	.equ PA4 = 4 ; For compatibility
		357	.equ PORTA5 = 5 ; Port A Data Register bit 5
		358	.equ PA5 = 5 ; For compatibility
		359	.equ PORTA6 = 6 ; Port A Data Register bit 6
		360	.equ PA6 = 6 ; For compatibility
		361	.equ PORTA7 = 7 ; Port A Data Register bit 7
		362	.equ PA7 = 7 ; For compatibility
		363
		364	; DDRA - Port A Data Direction Register
		365	.equ DDA0 = 0 ; Data Direction Register, Port A, bit 0
		366	.equ DDA1 = 1 ; Data Direction Register, Port A, bit 1
		367	.equ DDA2 = 2 ; Data Direction Register, Port A, bit 2
		368	.equ DDA3 = 3 ; Data Direction Register, Port A, bit 3
		369	.equ DDA4 = 4 ; Data Direction Register, Port A, bit 4
		370	.equ DDA5 = 5 ; Data Direction Register, Port A, bit 5
		371	.equ DDA6 = 6 ; Data Direction Register, Port A, bit 6
		372	.equ DDA7 = 7 ; Data Direction Register, Port A, bit 7
		373
		374	; PINA - Port A Input Pins
		375	.equ PINA0 = 0 ; Input Pins, Port A bit 0
		376	.equ PINA1 = 1 ; Input Pins, Port A bit 1
		377	.equ PINA2 = 2 ; Input Pins, Port A bit 2
		378	.equ PINA3 = 3 ; Input Pins, Port A bit 3
		379	.equ PINA4 = 4 ; Input Pins, Port A bit 4
		380	.equ PINA5 = 5 ; Input Pins, Port A bit 5
		381	.equ PINA6 = 6 ; Input Pins, Port A bit 6
		382	.equ PINA7 = 7 ; Input Pins, Port A bit 7
		383
		384
		385	; *** PORTB **********************
		386	; PORTB - Port B Data Register
		387	.equ PORTB0 = 0 ; Port B Data Register bit 0
		388	.equ PB0 = 0 ; For compatibility
		389	.equ PORTB1 = 1 ; Port B Data Register bit 1
		390	.equ PB1 = 1 ; For compatibility
		391	.equ PORTB2 = 2 ; Port B Data Register bit 2
		392	.equ PB2 = 2 ; For compatibility
		393	.equ PORTB3 = 3 ; Port B Data Register bit 3
		394	.equ PB3 = 3 ; For compatibility
		395	.equ PORTB4 = 4 ; Port B Data Register bit 4
		396	.equ PB4 = 4 ; For compatibility
		397	.equ PORTB5 = 5 ; Port B Data Register bit 5
		398	.equ PB5 = 5 ; For compatibility
		399	.equ PORTB6 = 6 ; Port B Data Register bit 6
		400	.equ PB6 = 6 ; For compatibility
		401	.equ PORTB7 = 7 ; Port B Data Register bit 7
		402	.equ PB7 = 7 ; For compatibility
		403
		404	; DDRB - Port B Data Direction Register
		405	.equ DDB0 = 0 ; Port B Data Direction Register bit 0
		406	.equ DDB1 = 1 ; Port B Data Direction Register bit 1
		407	.equ DDB2 = 2 ; Port B Data Direction Register bit 2
		408	.equ DDB3 = 3 ; Port B Data Direction Register bit 3
		409	.equ DDB4 = 4 ; Port B Data Direction Register bit 4
		410	.equ DDB5 = 5 ; Port B Data Direction Register bit 5
		411	.equ DDB6 = 6 ; Port B Data Direction Register bit 6
		412	.equ DDB7 = 7 ; Port B Data Direction Register bit 7
		413
		414	; PINB - Port B Input Pins
		415	.equ PINB0 = 0 ; Port B Input Pins bit 0
		416	.equ PINB1 = 1 ; Port B Input Pins bit 1
		417	.equ PINB2 = 2 ; Port B Input Pins bit 2
		418	.equ PINB3 = 3 ; Port B Input Pins bit 3
		419	.equ PINB4 = 4 ; Port B Input Pins bit 4
		420	.equ PINB5 = 5 ; Port B Input Pins bit 5
		421	.equ PINB6 = 6 ; Port B Input Pins bit 6
		422	.equ PINB7 = 7 ; Port B Input Pins bit 7
		423
		424
		425	; *** PORTC **********************
		426	; PORTC - Port C Data Register
		427	.equ PORTC0 = 0 ; Port C Data Register bit 0
		428	.equ PC0 = 0 ; For compatibility
		429	.equ PORTC1 = 1 ; Port C Data Register bit 1
		430	.equ PC1 = 1 ; For compatibility
		431	.equ PORTC2 = 2 ; Port C Data Register bit 2
		432	.equ PC2 = 2 ; For compatibility
		433	.equ PORTC3 = 3 ; Port C Data Register bit 3
		434	.equ PC3 = 3 ; For compatibility
		435	.equ PORTC4 = 4 ; Port C Data Register bit 4
		436	.equ PC4 = 4 ; For compatibility
		437	.equ PORTC5 = 5 ; Port C Data Register bit 5
		438	.equ PC5 = 5 ; For compatibility
		439	.equ PORTC6 = 6 ; Port C Data Register bit 6
		440	.equ PC6 = 6 ; For compatibility
		441	.equ PORTC7 = 7 ; Port C Data Register bit 7
		442	.equ PC7 = 7 ; For compatibility
		443
		444	; DDRC - Port C Data Direction Register
		445	.equ DDC0 = 0 ; Port C Data Direction Register bit 0
		446	.equ DDC1 = 1 ; Port C Data Direction Register bit 1
		447	.equ DDC2 = 2 ; Port C Data Direction Register bit 2
		448	.equ DDC3 = 3 ; Port C Data Direction Register bit 3
		449	.equ DDC4 = 4 ; Port C Data Direction Register bit 4
		450	.equ DDC5 = 5 ; Port C Data Direction Register bit 5
		451	.equ DDC6 = 6 ; Port C Data Direction Register bit 6
		452	.equ DDC7 = 7 ; Port C Data Direction Register bit 7
		453
		454	; PINC - Port C Input Pins
		455	.equ PINC0 = 0 ; Port C Input Pins bit 0
		456	.equ PINC1 = 1 ; Port C Input Pins bit 1
		457	.equ PINC2 = 2 ; Port C Input Pins bit 2
		458	.equ PINC3 = 3 ; Port C Input Pins bit 3
		459	.equ PINC4 = 4 ; Port C Input Pins bit 4
		460	.equ PINC5 = 5 ; Port C Input Pins bit 5
		461	.equ PINC6 = 6 ; Port C Input Pins bit 6
		462	.equ PINC7 = 7 ; Port C Input Pins bit 7
		463
		464
		465	; *** PORTD **********************
		466	; PORTD - Port D Data Register
		467	.equ PORTD0 = 0 ; Port D Data Register bit 0
		468	.equ PD0 = 0 ; For compatibility
		469	.equ PORTD1 = 1 ; Port D Data Register bit 1
		470	.equ PD1 = 1 ; For compatibility
		471	.equ PORTD2 = 2 ; Port D Data Register bit 2
		472	.equ PD2 = 2 ; For compatibility
		473	.equ PORTD3 = 3 ; Port D Data Register bit 3
		474	.equ PD3 = 3 ; For compatibility
		475	.equ PORTD4 = 4 ; Port D Data Register bit 4
		476	.equ PD4 = 4 ; For compatibility
		477	.equ PORTD5 = 5 ; Port D Data Register bit 5
		478	.equ PD5 = 5 ; For compatibility
		479	.equ PORTD6 = 6 ; Port D Data Register bit 6
		480	.equ PD6 = 6 ; For compatibility
		481	.equ PORTD7 = 7 ; Port D Data Register bit 7
		482	.equ PD7 = 7 ; For compatibility
		483
		484	; DDRD - Port D Data Direction Register
		485	.equ DDD0 = 0 ; Port D Data Direction Register bit 0
		486	.equ DDD1 = 1 ; Port D Data Direction Register bit 1
		487	.equ DDD2 = 2 ; Port D Data Direction Register bit 2
		488	.equ DDD3 = 3 ; Port D Data Direction Register bit 3
		489	.equ DDD4 = 4 ; Port D Data Direction Register bit 4
		490	.equ DDD5 = 5 ; Port D Data Direction Register bit 5
		491	.equ DDD6 = 6 ; Port D Data Direction Register bit 6
		492	.equ DDD7 = 7 ; Port D Data Direction Register bit 7
		493
		494	; PIND - Port D Input Pins
		495	.equ PIND0 = 0 ; Port D Input Pins bit 0
		496	.equ PIND1 = 1 ; Port D Input Pins bit 1
		497	.equ PIND2 = 2 ; Port D Input Pins bit 2
		498	.equ PIND3 = 3 ; Port D Input Pins bit 3
		499	.equ PIND4 = 4 ; Port D Input Pins bit 4
		500	.equ PIND5 = 5 ; Port D Input Pins bit 5
		501	.equ PIND6 = 6 ; Port D Input Pins bit 6
		502	.equ PIND7 = 7 ; Port D Input Pins bit 7
		503
		504
		505	; *** ANALOG_COMPARATOR **********
		506	; ADCSRB - ADC Control and Status Register B
		507	.equ ACME = 6 ; Analog Comparator Multiplexer Enable
		508
		509	; ACSR - Analog Comparator Control And Status Register
		510	.equ ACIS0 = 0 ; Analog Comparator Interrupt Mode Select bit 0
		511	.equ ACIS1 = 1 ; Analog Comparator Interrupt Mode Select bit 1
		512	.equ ACIC = 2 ; Analog Comparator Input Capture Enable
		513	.equ ACIE = 3 ; Analog Comparator Interrupt Enable
		514	.equ ACI = 4 ; Analog Comparator Interrupt Flag
		515	.equ ACO = 5 ; Analog Compare Output
		516	.equ ACBG = 6 ; Analog Comparator Bandgap Select
		517	.equ ACD = 7 ; Analog Comparator Disable
		518
		519	; DIDR1 - Digital Input Disable Register 1
		520	.equ AIN0D = 0 ; AIN0 Digital Input Disable
		521	.equ AIN1D = 1 ; AIN1 Digital Input Disable
		522
		523
		524	; *** PORTE **********************
		525	; PORTE - Data Register, Port E
		526	.equ PORTE0 = 0 ;
		527	.equ PE0 = 0 ; For compatibility
		528	.equ PORTE1 = 1 ;
		529	.equ PE1 = 1 ; For compatibility
		530	.equ PORTE2 = 2 ;
		531	.equ PE2 = 2 ; For compatibility
		532	.equ PORTE3 = 3 ;
		533	.equ PE3 = 3 ; For compatibility
		534	.equ PORTE4 = 4 ;
		535	.equ PE4 = 4 ; For compatibility
		536	.equ PORTE5 = 5 ;
		537	.equ PE5 = 5 ; For compatibility
		538	.equ PORTE6 = 6 ;
		539	.equ PE6 = 6 ; For compatibility
		540	.equ PORTE7 = 7 ;
		541	.equ PE7 = 7 ; For compatibility
		542
		543	; DDRE - Data Direction Register, Port E
		544	.equ DDE0 = 0 ;
		545	.equ DDE1 = 1 ;
		546	.equ DDE2 = 2 ;
		547	.equ DDE3 = 3 ;
		548	.equ DDE4 = 4 ;
		549	.equ DDE5 = 5 ;
		550	.equ DDE6 = 6 ;
		551	.equ DDE7 = 7 ;
		552
		553	; PINE - Input Pins, Port E
		554	.equ PINE0 = 0 ;
		555	.equ PINE1 = 1 ;
		556	.equ PINE2 = 2 ;
		557	.equ PINE3 = 3 ;
		558	.equ PINE4 = 4 ;
		559	.equ PINE5 = 5 ;
		560	.equ PINE6 = 6 ;
		561	.equ PINE7 = 7 ;
		562
		563
		564	; *** PORTF **********************
		565	; PORTF - Data Register, Port F
		566	.equ PORTF0 = 0 ;
		567	.equ PF0 = 0 ; For compatibility
		568	.equ PORTF1 = 1 ;
		569	.equ PF1 = 1 ; For compatibility
		570	.equ PORTF2 = 2 ;
		571	.equ PF2 = 2 ; For compatibility
		572	.equ PORTF3 = 3 ;
		573	.equ PF3 = 3 ; For compatibility
		574	.equ PORTF4 = 4 ;
		575	.equ PF4 = 4 ; For compatibility
		576	.equ PORTF5 = 5 ;
		577	.equ PF5 = 5 ; For compatibility
		578	.equ PORTF6 = 6 ;
		579	.equ PF6 = 6 ; For compatibility
		580	.equ PORTF7 = 7 ;
		581	.equ PF7 = 7 ; For compatibility
		582
		583	; DDRF - Data Direction Register, Port F
		584	.equ DDF0 = 0 ;
		585	.equ DDF1 = 1 ;
		586	.equ DDF2 = 2 ;
		587	.equ DDF3 = 3 ;
		588	.equ DDF4 = 4 ;
		589	.equ DDF5 = 5 ;
		590	.equ DDF6 = 6 ;
		591	.equ DDF7 = 7 ;
		592
		593	; PINF - Input Pins, Port F
		594	.equ PINF0 = 0 ;
		595	.equ PINF1 = 1 ;
		596	.equ PINF2 = 2 ;
		597	.equ PINF3 = 3 ;
		598	.equ PINF4 = 4 ;
		599	.equ PINF5 = 5 ;
		600	.equ PINF6 = 6 ;
		601	.equ PINF7 = 7 ;
		602
		603
		604	; *** PORTG **********************
		605	; PORTG - Port G Data Register
		606	.equ PORTG0 = 0 ;
		607	.equ PG0 = 0 ; For compatibility
		608	.equ PORTG1 = 1 ;
		609	.equ PG1 = 1 ; For compatibility
		610	.equ PORTG2 = 2 ;
		611	.equ PG2 = 2 ; For compatibility
		612	.equ PORTG3 = 3 ;
		613	.equ PG3 = 3 ; For compatibility
		614	.equ PORTG4 = 4 ;
		615	.equ PG4 = 4 ; For compatibility
		616
		617	; DDRG - Port G Data Direction Register
		618	.equ DDG0 = 0 ;
		619	.equ DDG1 = 1 ;
		620	.equ DDG2 = 2 ;
		621	.equ DDG3 = 3 ;
		622	.equ DDG4 = 4 ;
		623
		624	; PING - Port G Input Pins
		625	.equ PING0 = 0 ;
		626	.equ PING1 = 1 ;
		627	.equ PING2 = 2 ;
		628	.equ PING3 = 3 ;
		629	.equ PING4 = 4 ;
		630	.equ PING5 = 5 ;
		631
		632
		633	; *** JTAG ***********************
		634	; OCDR - On-Chip Debug Related Register in I/O Memory
		635	.equ OCDR0 = 0 ; On-Chip Debug Register Bit 0
		636	.equ OCDR1 = 1 ; On-Chip Debug Register Bit 1
		637	.equ OCDR2 = 2 ; On-Chip Debug Register Bit 2
		638	.equ OCDR3 = 3 ; On-Chip Debug Register Bit 3
		639	.equ OCDR4 = 4 ; On-Chip Debug Register Bit 4
		640	.equ OCDR5 = 5 ; On-Chip Debug Register Bit 5
		641	.equ OCDR6 = 6 ; On-Chip Debug Register Bit 6
		642	.equ OCDR7 = 7 ; On-Chip Debug Register Bit 7
		643	.equ IDRD = OCDR7 ; For compatibility
		644
		645	; MCUCR - MCU Control Register
		646	.equ JTD = 7 ; JTAG Interface Disable
		647
		648	; MCUSR - MCU Status Register
		649	.equ JTRF = 4 ; JTAG Reset Flag
		650
		651
		652	; *** EXTERNAL_INTERRUPT *********
		653	; EICRA - External Interrupt Control Register
		654	.equ ISC00 = 0 ; External Interrupt Sense Control 0 Bit 0
		655	.equ ISC01 = 1 ; External Interrupt Sense Control 0 Bit 1
		656
		657	; EIMSK - External Interrupt Mask Register
		658	.equ INT0 = 0 ; External Interrupt Request 0 Enable
		659	.equ PCIE0 = 6 ; Pin Change Interrupt Enable 0
		660	.equ PCIE1 = 7 ; Pin Change Interrupt Enable 1
		661
		662	; EIFR - External Interrupt Flag Register
		663	.equ INTF0 = 0 ; External Interrupt Flag 0
		664	.equ PCIF0 = 6 ; Pin Change Interrupt Flag 0
		665	.equ PCIF1 = 7 ; Pin Change Interrupt Flag 1
		666
		667	; PCMSK1 - Pin Change Mask Register 1
		668	.equ PCINT8 = 0 ; Pin Change Enable Mask 8
		669	.equ PCINT9 = 1 ; Pin Change Enable Mask 9
		670	.equ PCINT10 = 2 ; Pin Change Enable Mask 10
		671	.equ PCINT11 = 3 ; Pin Change Enable Mask 11
		672	.equ PCINT12 = 4 ; Pin Change Enable Mask 12
		673	.equ PCINT13 = 5 ; Pin Change Enable Mask 13
		674	.equ PCINT14 = 6 ; Pin Change Enable Mask 14
		675	.equ PCINT15 = 7 ; Pin Change Enable Mask 15
		676
		677	; PCMSK0 - Pin Change Mask Register 0
		678	.equ PCINT0 = 0 ; Pin Change Enable Mask 0
		679	.equ PCINT1 = 1 ; Pin Change Enable Mask 1
		680	.equ PCINT2 = 2 ; Pin Change Enable Mask 2
		681	.equ PCINT3 = 3 ; Pin Change Enable Mask 3
		682	.equ PCINT4 = 4 ; Pin Change Enable Mask 4
		683	.equ PCINT5 = 5 ; Pin Change Enable Mask 5
		684	.equ PCINT6 = 6 ; Pin Change Enable Mask 6
		685	.equ PCINT7 = 7 ; Pin Change Enable Mask 7
		686
		687
		688	; *** USI ************************
		689	; USIDR - USI Data Register
		690	.equ USIDR0 = 0 ; USI Data Register bit 0
		691	.equ USIDR1 = 1 ; USI Data Register bit 1
		692	.equ USIDR2 = 2 ; USI Data Register bit 2
		693	.equ USIDR3 = 3 ; USI Data Register bit 3
		694	.equ USIDR4 = 4 ; USI Data Register bit 4
		695	.equ USIDR5 = 5 ; USI Data Register bit 5
		696	.equ USIDR6 = 6 ; USI Data Register bit 6
		697	.equ USIDR7 = 7 ; USI Data Register bit 7
		698
		699	; USISR - USI Status Register
		700	.equ USICNT0 = 0 ; USI Counter Value Bit 0
		701	.equ USICNT1 = 1 ; USI Counter Value Bit 1
		702	.equ USICNT2 = 2 ; USI Counter Value Bit 2
		703	.equ USICNT3 = 3 ; USI Counter Value Bit 3
		704	.equ USIDC = 4 ; Data Output Collision
		705	.equ USIPF = 5 ; Stop Condition Flag
		706	.equ USIOIF = 6 ; Counter Overflow Interrupt Flag
		707	.equ USISIF = 7 ; Start Condition Interrupt Flag
		708
		709	; USICR - USI Control Register
		710	.equ USITC = 0 ; Toggle Clock Port Pin
		711	.equ USICLK = 1 ; Clock Strobe
		712	.equ USICS0 = 2 ; USI Clock Source Select Bit 0
		713	.equ USICS1 = 3 ; USI Clock Source Select Bit 1
		714	.equ USIWM0 = 4 ; USI Wire Mode Bit 0
		715	.equ USIWM1 = 5 ; USI Wire Mode Bit 1
		716	.equ USIOIE = 6 ; Counter Overflow Interrupt Enable
		717	.equ USISIE = 7 ; Start Condition Interrupt Enable
		718
		719
		720	; *** AD_CONVERTER ***************
		721	; ADMUX - The ADC multiplexer Selection Register
		722	.equ MUX0 = 0 ; Analog Channel and Gain Selection Bits
		723	.equ MUX1 = 1 ; Analog Channel and Gain Selection Bits
		724	.equ MUX2 = 2 ; Analog Channel and Gain Selection Bits
		725	.equ MUX3 = 3 ; Analog Channel and Gain Selection Bits
		726	.equ MUX4 = 4 ; Analog Channel and Gain Selection Bits
		727	.equ ADLAR = 5 ; Left Adjust Result
		728	.equ REFS0 = 6 ; Reference Selection Bit 0
		729	.equ REFS1 = 7 ; Reference Selection Bit 1
		730
		731	; ADCSRA - The ADC Control and Status register
		732	.equ ADPS0 = 0 ; ADC Prescaler Select Bits
		733	.equ ADPS1 = 1 ; ADC Prescaler Select Bits
		734	.equ ADPS2 = 2 ; ADC Prescaler Select Bits
		735	.equ ADIE = 3 ; ADC Interrupt Enable
		736	.equ ADIF = 4 ; ADC Interrupt Flag
		737	.equ ADATE = 5 ; ADC Auto Trigger Enable
		738	.equ ADSC = 6 ; ADC Start Conversion
		739	.equ ADEN = 7 ; ADC Enable
		740
		741	; ADCH - ADC Data Register High Byte
		742	.equ ADCH0 = 0 ; ADC Data Register High Byte Bit 0
		743	.equ ADCH1 = 1 ; ADC Data Register High Byte Bit 1
		744	.equ ADCH2 = 2 ; ADC Data Register High Byte Bit 2
		745	.equ ADCH3 = 3 ; ADC Data Register High Byte Bit 3
		746	.equ ADCH4 = 4 ; ADC Data Register High Byte Bit 4
		747	.equ ADCH5 = 5 ; ADC Data Register High Byte Bit 5
		748	.equ ADCH6 = 6 ; ADC Data Register High Byte Bit 6
		749	.equ ADCH7 = 7 ; ADC Data Register High Byte Bit 7
		750
		751	; ADCL - ADC Data Register Low Byte
		752	.equ ADCL0 = 0 ; ADC Data Register Low Byte Bit 0
		753	.equ ADCL1 = 1 ; ADC Data Register Low Byte Bit 1
		754	.equ ADCL2 = 2 ; ADC Data Register Low Byte Bit 2
		755	.equ ADCL3 = 3 ; ADC Data Register Low Byte Bit 3
		756	.equ ADCL4 = 4 ; ADC Data Register Low Byte Bit 4
		757	.equ ADCL5 = 5 ; ADC Data Register Low Byte Bit 5
		758	.equ ADCL6 = 6 ; ADC Data Register Low Byte Bit 6
		759	.equ ADCL7 = 7 ; ADC Data Register Low Byte Bit 7
		760
		761	; ADCSRB - ADC Control and Status Register B
		762	.equ ADTS0 = 0 ; ADC Auto Trigger Source 0
		763	.equ ADTS1 = 1 ; ADC Auto Trigger Source 1
		764	.equ ADTS2 = 2 ; ADC Auto Trigger Source 2
		765
		766	; DIDR0 - Digital Input Disable Register 0
		767	.equ ADC0D = 0 ; ADC0 Digital input Disable
		768	.equ ADC1D = 1 ; ADC1 Digital input Disable
		769	.equ ADC2D = 2 ; ADC2 Digital input Disable
		770	.equ ADC3D = 3 ; ADC3 Digital input Disable
		771	.equ ADC4D = 4 ; ADC4 Digital input Disable
		772	.equ ADC5D = 5 ; ADC5 Digital input Disable
		773	.equ ADC6D = 6 ; ADC6 Digital input Disable
		774	.equ ADC7D = 7 ; ADC7 Digital input Disable
		775
		776
		777	; *** BOOT_LOAD ******************
		778	; SPMCSR - Store Program Memory Control Register
		779	.equ SPMCR = SPMCSR ; For compatibility
		780	.equ SPMEN = 0 ; Store Program Memory Enable
		781	.equ PGERS = 1 ; Page Erase
		782	.equ PGWRT = 2 ; Page Write
		783	.equ BLBSET = 3 ; Boot Lock Bit Set
		784	.equ RWWSRE = 4 ; Read While Write section read enable
		785	.equ ASRE = RWWSRE ; For compatibility
		786	.equ RWWSB = 6 ; Read While Write Section Busy
		787	.equ ASB = RWWSB ; For compatibility
		788	.equ SPMIE = 7 ; SPM Interrupt Enable
		789
		790
		791	; *** USART0 *********************
		792	; UDR - USART I/O Data Register
		793	.equ UDR0 = UDR ; For compatibility
		794	.equ UDR00 = 0 ; USART I/O Data Register bit 0
		795	.equ UDR01 = 1 ; USART I/O Data Register bit 1
		796	.equ UDR02 = 2 ; USART I/O Data Register bit 2
		797	.equ UDR03 = 3 ; USART I/O Data Register bit 3
		798	.equ UDR04 = 4 ; USART I/O Data Register bit 4
		799	.equ UDR05 = 5 ; USART I/O Data Register bit 5
		800	.equ UDR06 = 6 ; USART I/O Data Register bit 6
		801	.equ UDR07 = 7 ; USART I/O Data Register bit 7
		802
		803	; UCSRA - USART Control and Status Register A
		804	.equ UCSR0A = UCSRA ; For compatibility
		805	.equ USR = UCSRA ; For compatibility
		806	.equ MPCM = 0 ; Multi-processor Communication Mode
		807	.equ MPCM0 = MPCM ; For compatibility
		808	.equ U2X = 1 ; Double the USART Transmission Speed
		809	.equ U2X0 = U2X ; For compatibility
		810	.equ UPE = 2 ; USART Parity Error
		811	.equ UPE0 = UPE ; For compatibility
		812	.equ DOR = 3 ; Data OverRun
		813	.equ DOR0 = DOR ; For compatibility
		814	.equ FE = 4 ; Framing Error
		815	.equ FE0 = FE ; For compatibility
		816	.equ UDRE = 5 ; USART Data Register Empty
		817	.equ UDRE0 = UDRE ; For compatibility
		818	.equ TXC = 6 ; USART Transmit Complete
		819	.equ TXC0 = TXC ; For compatibility
		820	.equ RXC = 7 ; USART Receive Complete
		821	.equ RXC0 = RXC ; For compatibility
		822
		823	; UCSRB - USART Control and Status Register B
		824	.equ UCSR0B = UCSRB ; For compatibility
		825	.equ UCR = UCSRB ; For compatibility
		826	.equ TXB8 = 0 ; Transmit Data Bit 8
		827	.equ TXB80 = TXB8 ; For compatibility
		828	.equ RXB8 = 1 ; Receive Data Bit 8
		829	.equ RXB80 = RXB8 ; For compatibility
		830	.equ UCSZ2 = 2 ; Character Size
		831	.equ UCSZ02 = UCSZ2 ; For compatibility
		832	.equ TXEN = 3 ; Transmitter Enable
		833	.equ TXEN0 = TXEN ; For compatibility
		834	.equ RXEN = 4 ; Receiver Enable
		835	.equ RXEN0 = RXEN ; For compatibility
		836	.equ UDRIE = 5 ; USART Data Register Empty Interrupt Enable
		837	.equ UDRIE0 = UDRIE ; For compatibility
		838	.equ TXCIE = 6 ; TX Complete Interrupt Enable
		839	.equ TXCIE0 = TXCIE ; For compatibility
		840	.equ RXCIE = 7 ; RX Complete Interrupt Enable
		841	.equ RXCIE0 = RXCIE ; For compatibility
		842
		843	; UCSRC - USART Control and Status Register C
		844	.equ UCSR0C = UCSRC ; For compatibility
		845	.equ UCPOL = 0 ; Clock Polarity
		846	.equ UCPOL0 = UCPOL ; For compatibility
		847	.equ UCSZ0 = 1 ; Character Size
		848	.equ UCSZ00 = UCSZ0 ; For compatibility
		849	.equ UCSZ1 = 2 ; Character Size
		850	.equ UCSZ01 = UCSZ1 ; For compatibility
		851	.equ USBS = 3 ; Stop Bit Select
		852	.equ USBS0 = USBS ; For compatibility
		853	.equ UPM0 = 4 ; Parity Mode Bit 0
		854	.equ UPM00 = UPM0 ; For compatibility
		855	.equ UPM1 = 5 ; Parity Mode Bit 1
		856	.equ UPM01 = UPM1 ; For compatibility
		857	.equ UMSEL = 6 ; USART Mode Select
		858	.equ UMSEL0 = UMSEL ; For compatibility
		859
		860	.equ UBRR0H = UBRRH ; For compatibility
		861	.equ UBRR0L = UBRRL ; For compatibility
		862	.equ UBRR0 = UBRRL ; For compatibility
		863	.equ UBRR = UBRRL ; For compatibility
		864
		865	; *** CPU ************************
		866	; SREG - Status Register
		867	.equ SREG_C = 0 ; Carry Flag
		868	.equ SREG_Z = 1 ; Zero Flag
		869	.equ SREG_N = 2 ; Negative Flag
		870	.equ SREG_V = 3 ; Two's Complement Overflow Flag
		871	.equ SREG_S = 4 ; Sign Bit
		872	.equ SREG_H = 5 ; Half Carry Flag
		873	.equ SREG_T = 6 ; Bit Copy Storage
		874	.equ SREG_I = 7 ; Global Interrupt Enable
		875
		876	; MCUCR - MCU Control Register
		877	.equ IVCE = 0 ; Interrupt Vector Change Enable
		878	.equ IVSEL = 1 ; Interrupt Vector Select
		879	.equ PUD = 4 ; Pull-up disable
		880
		881	; MCUSR - MCU Status Register
		882	.equ PORF = 0 ; Power-on reset flag
		883	.equ EXTRF = 1 ; External Reset Flag
		884	.equ BORF = 2 ; Brown-out Reset Flag
		885	.equ WDRF = 3 ; Watchdog Reset Flag
		886	;.equ JTRF = 4 ; JTAG Reset Flag
		887
		888	; OSCCAL - Oscillator Calibration Value
		889	.equ CAL0 = 0 ; Oscillator Calibration Value Bit0
		890	.equ CAL1 = 1 ; Oscillator Calibration Value Bit1
		891	.equ CAL2 = 2 ; Oscillator Calibration Value Bit2
		892	.equ CAL3 = 3 ; Oscillator Calibration Value Bit3
		893	.equ CAL4 = 4 ; Oscillator Calibration Value Bit4
		894	.equ CAL5 = 5 ; Oscillator Calibration Value Bit5
		895	.equ CAL6 = 6 ; Oscillator Calibration Value Bit6
		896	.equ CAL7 = 7 ; Oscillator Calibration Value Bit7
		897
		898	; CLKPR - Clock Prescale Register
		899	.equ CLKPS0 = 0 ; Clock Prescaler Select Bit 0
		900	.equ CLKPS1 = 1 ; Clock Prescaler Select Bit 1
		901	.equ CLKPS2 = 2 ; Clock Prescaler Select Bit 2
		902	.equ CLKPS3 = 3 ; Clock Prescaler Select Bit 3
		903	.equ CLKPCE = 7 ; Clock Prescaler Change Enable
		904
		905	; PRR - Power Reduction Register
		906	.equ PRADC = 0 ; Power Reduction ADC
		907	.equ PRUSART0 = 1 ; Power Reduction USART
		908	.equ PRSPI = 2 ; Power Reduction Serial Peripheral Interface
		909	.equ PRTIM1 = 3 ; Power Reduction Timer/Counter1
		910
		911	; SMCR - Sleep Mode Control Register
		912	.equ SE = 0 ; Sleep Enable
		913	.equ SM0 = 1 ; Sleep Mode Select bit 0
		914	.equ SM1 = 2 ; Sleep Mode Select bit 1
		915	.equ SM2 = 3 ; Sleep Mode Select bit 2
		916
		917	; GPIOR2 - General Purpose IO Register 2
		918	.equ GPIOR20 = 0 ; General Purpose IO Register 2 bit 0
		919	.equ GPIOR21 = 1 ; General Purpose IO Register 2 bit 1
		920	.equ GPIOR22 = 2 ; General Purpose IO Register 2 bit 2
		921	.equ GPIOR23 = 3 ; General Purpose IO Register 2 bit 3
		922	.equ GPIOR24 = 4 ; General Purpose IO Register 2 bit 4
		923	.equ GPIOR25 = 5 ; General Purpose IO Register 2 bit 5
		924	.equ GPIOR26 = 6 ; General Purpose IO Register 2 bit 6
		925	.equ GPIOR27 = 7 ; General Purpose IO Register 2 bit 7
		926
		927	; GPIOR1 - General Purpose IO Register 1
		928	.equ GPIOR10 = 0 ; General Purpose IO Register 1 bit 0
		929	.equ GPIOR11 = 1 ; General Purpose IO Register 1 bit 1
		930	.equ GPIOR12 = 2 ; General Purpose IO Register 1 bit 2
		931	.equ GPIOR13 = 3 ; General Purpose IO Register 1 bit 3
		932	.equ GPIOR14 = 4 ; General Purpose IO Register 1 bit 4
		933	.equ GPIOR15 = 5 ; General Purpose IO Register 1 bit 5
		934	.equ GPIOR16 = 6 ; General Purpose IO Register 1 bit 6
		935	.equ GPIOR17 = 7 ; General Purpose IO Register 1 bit 7
		936
		937	; GPIOR0 - General Purpose IO Register 0
		938	.equ GPIOR00 = 0 ; General Purpose IO Register 0 bit 0
		939	.equ GPIOR01 = 1 ; General Purpose IO Register 0 bit 1
		940	.equ GPIOR02 = 2 ; General Purpose IO Register 0 bit 2
		941	.equ GPIOR03 = 3 ; General Purpose IO Register 0 bit 3
		942	.equ GPIOR04 = 4 ; General Purpose IO Register 0 bit 4
		943	.equ GPIOR05 = 5 ; General Purpose IO Register 0 bit 5
		944	.equ GPIOR06 = 6 ; General Purpose IO Register 0 bit 6
		945	.equ GPIOR07 = 7 ; General Purpose IO Register 0 bit 7
		946
		947
		948
		949	; *** LOCKSBITS ******************************************************
		950	.equ LB1 = 0 ; Lock bit
		951	.equ LB2 = 1 ; Lock bit
		952	.equ BLB01 = 2 ; Boot Lock bit
		953	.equ BLB02 = 3 ; Boot Lock bit
		954	.equ BLB11 = 4 ; Boot lock bit
		955	.equ BLB12 = 5 ; Boot lock bit
		956
		957
		958	; *** FUSES **********************************************************
		959	; LOW fuse bits
		960	.equ CKSEL0 = 0 ; Select Clock Source
		961	.equ CKSEL1 = 1 ; Select Clock Source
		962	.equ CKSEL2 = 2 ; Select Clock Source
		963	.equ CKSEL3 = 3 ; Select Clock Source
		964	.equ SUT0 = 4 ; Select start-up time
		965	.equ SUT1 = 5 ; Select start-up time
		966	.equ CKOUT = 6 ; Oscillator options
		967	.equ CLKDIV8 = 7 ; Divide clock by 8
		968
		969	; HIGH fuse bits
		970	.equ BOOTRST = 0 ; Select Reset Vector
		971	.equ BOOTSZ0 = 1 ; Select Boot Size
		972	.equ BOOTSZ1 = 2 ; Select Boot Size
		973	.equ EESAVE = 3 ; EEPROM memory is preserved through chip erase
		974	.equ WDTON = 4 ; Watchdog timer always on
		975	.equ SPIEN = 5 ; Enable Serial programming and Data Downloading
		976	.equ JTAGEN = 6 ; Enable JTAG
		977	.equ OCDEN = 7 ; Enable OCD
		978
		979	; EXTENDED fuse bits
		980	.equ RESERVED = 0 ; Reserved for future use
		981	.equ BODLEVEL0 = 1 ; Brown-out Detector trigger level
		982	.equ BODLEVEL1 = 2 ; Brown-out Detector trigger level
		983	.equ BODLEVEL2 = 3 ; Brown out detector trigger level
		984
		985
		986
		987	; *** CPU REGISTER DEFINITIONS ***************************************
		988	.def XH = r27
		989	.def XL = r26
		990	.def YH = r29
		991	.def YL = r28
		992	.def ZH = r31
		993	.def ZL = r30
		994
		995
		996
		997	; *** DATA MEMORY DECLARATIONS ***************************************
		998	.equ FLASHEND = 0x1fff ; Note: Word address
		999	.equ IOEND = 0x00ff
		1000	.equ SRAM_START = 0x0100
		1001	.equ SRAM_SIZE = 1024
		1002	.equ RAMEND = 0x04ff
		1003	.equ XRAMEND = 0x0000
		1004	.equ E2END = 0x01ff
		1005	.equ EEPROMEND = 0x01ff
		1006	.equ EEADRBITS = 9
		1007	#pragma AVRPART MEMORY PROG_FLASH 16384
		1008	#pragma AVRPART MEMORY EEPROM 512
		1009	#pragma AVRPART MEMORY INT_SRAM SIZE 1024
		1010	#pragma AVRPART MEMORY INT_SRAM START_ADDR 0x100
		1011
		1012
		1013
		1014	; *** BOOTLOADER DECLARATIONS ****************************************
		1015	.equ NRWW_START_ADDR = 0x1c00
		1016	.equ NRWW_STOP_ADDR = 0x1fff
		1017	.equ RWW_START_ADDR = 0x0
		1018	.equ RWW_STOP_ADDR = 0x1bff
		1019	.equ PAGESIZE = 64
		1020	.equ FIRSTBOOTSTART = 0x1f80
		1021	.equ SECONDBOOTSTART = 0x1f00
		1022	.equ THIRDBOOTSTART = 0x1e00
		1023	.equ FOURTHBOOTSTART = 0x1c00
		1024	.equ SMALLBOOTSTART = FIRSTBOOTSTART
		1025	.equ LARGEBOOTSTART = FOURTHBOOTSTART
		1026
		1027
		1028
		1029	; *** INTERRUPT VECTORS **********************************************
		1030	.equ INT0addr = 0x0002 ; External Interrupt Request 0
		1031	.equ PCI0addr = 0x0004 ; Pin Change Interrupt Request 0
		1032	.equ PCI1addr = 0x0006 ; Pin Change Interrupt Request 1
		1033	.equ OC2addr = 0x0008 ; Timer/Counter2 Compare Match
		1034	.equ OVF2addr = 0x000a ; Timer/Counter2 Overflow
		1035	.equ ICP1addr = 0x000c ; Timer/Counter1 Capture Event
		1036	.equ OC1Aaddr = 0x000e ; Timer/Counter1 Compare Match A
		1037	.equ OC1Baddr = 0x0010 ; Timer/Counter Compare Match B
		1038	.equ OVF1addr = 0x0012 ; Timer/Counter1 Overflow
		1039	.equ OC0addr = 0x0014 ; Timer/Counter0 Compare Match
		1040	.equ OVF0addr = 0x0016 ; Timer/Counter0 Overflow
		1041	.equ SPIaddr = 0x0018 ; SPI Serial Transfer Complete
		1042	.equ URXC0addr = 0x001a ; USART0, Rx Complete
		1043	.equ URXCaddr = 0x001a ; For compatibility
		1044	.equ UDRE0addr = 0x001c ; USART0 Data register Empty
		1045	.equ UDREaddr = 0x001c ; For compatibility
		1046	.equ UTXC0addr = 0x001e ; USART0, Tx Complete
		1047	.equ UTXCaddr = 0x001e ; For compatibility
		1048	.equ USI_STARTaddr = 0x0020 ; USI Start Condition
		1049	.equ USI_OVFaddr = 0x0022 ; USI Overflow
		1050	.equ ACIaddr = 0x0024 ; Analog Comparator
		1051	.equ ADCCaddr = 0x0026 ; ADC Conversion Complete
		1052	.equ ERDYaddr = 0x0028 ; EEPROM Ready
		1053	.equ SPMRaddr = 0x002a ; Store Program Memory Read
		1054
		1055	.equ INT_VECTORS_SIZE = 44 ; size in words
		1056
		1057	#endif /* _M165DEF_INC_ */
		1058
		1059	; *** END OF FILE ****************************************************

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(root)/contrib/toolchain/avra/includes/m165def.inc – Rev 6400