WebSVN – Kolibri OS – Blame – /contrib/toolchain/avra/includes/m128def.inc

Rev	Author	Line No.	Line
6400	punk_joker	1	;*** THIS IS A MACHINE GENERATED FILE - DO NOT EDIT ******************
		2	;*** Created: 2005-01-11 10:30 *** Source: ATmega128.xml *********
		3	;*************************************************************************
		4	;* A P P L I C A T I O N N O T E F O R T H E A V R F A M I L Y
		5	;*
		6	;* Number : AVR000
		7	;* File Name : "m128def.inc"
		8	;* Title : Register/Bit Definitions for the ATmega128
		9	;* Date : 2005-01-11
		10	;* Version : 2.14
		11	;* Support E-mail : avr@atmel.com
		12	;* Target MCU : ATmega128
		13	;*
		14	;* DESCRIPTION
		15	;* When including this file in the assembly program file, all I/O register
		16	;* names and I/O register bit names appearing in the data book can be used.
		17	;* In addition, the six registers forming the three data pointers X, Y and
		18	;* Z have been assigned names XL - ZH. Highest RAM address for Internal
		19	;* SRAM is also defined
		20	;*
		21	;* The Register names are represented by their hexadecimal address.
		22	;*
		23	;* The Register Bit names are represented by their bit number (0-7).
		24	;*
		25	;* Please observe the difference in using the bit names with instructions
		26	;* such as "sbr"/"cbr" (set/clear bit in register) and "sbrs"/"sbrc"
		27	;* (skip if bit in register set/cleared). The following example illustrates
		28	;* this:
		29	;*
		30	;* in r16,PORTB ;read PORTB latch
		31	;* sbr r16,(1<
		32	;* out PORTB,r16 ;output to PORTB
		33	;*
		34	;* in r16,TIFR ;read the Timer Interrupt Flag Register
		35	;* sbrc r16,TOV0 ;test the overflow flag (use bit#)
		36	;* rjmp TOV0_is_set ;jump if set
		37	;* ... ;otherwise do something else
		38	;*************************************************************************
		39
		40	#ifndef _M128DEF_INC_
		41	#define _M128DEF_INC_
		42
		43
		44	#pragma partinc 0
		45
		46	; *** SPECIFY DEVICE *************************************************
		47	.device ATmega128
		48	#pragma AVRPART ADMIN PART_NAME ATmega128
		49	.equ SIGNATURE_000 = 0x1e
		50	.equ SIGNATURE_001 = 0x97
		51	.equ SIGNATURE_002 = 0x02
		52
		53	#pragma AVRPART CORE CORE_VERSION V2E
		54
		55
		56	; *** I/O REGISTER DEFINITIONS ***************************************
		57	; NOTE:
		58	; Definitions marked "MEMORY MAPPED"are extended I/O ports
		59	; and cannot be used with IN/OUT instructions
		60	.equ UCSR1C = 0x9d ; MEMORY MAPPED
		61	.equ UDR1 = 0x9c ; MEMORY MAPPED
		62	.equ UCSR1A = 0x9b ; MEMORY MAPPED
		63	.equ UCSR1B = 0x9a ; MEMORY MAPPED
		64	.equ UBRR1L = 0x99 ; MEMORY MAPPED
		65	.equ UBRR1H = 0x98 ; MEMORY MAPPED
		66	.equ UCSR0C = 0x95 ; MEMORY MAPPED
		67	.equ UBRR0H = 0x90 ; MEMORY MAPPED
		68	.equ TCCR3C = 0x8c ; MEMORY MAPPED
		69	.equ TCCR3A = 0x8b ; MEMORY MAPPED
		70	.equ TCCR3B = 0x8a ; MEMORY MAPPED
		71	.equ TCNT3H = 0x89 ; MEMORY MAPPED
		72	.equ TCNT3L = 0x88 ; MEMORY MAPPED
		73	.equ OCR3AH = 0x87 ; MEMORY MAPPED
		74	.equ OCR3AL = 0x86 ; MEMORY MAPPED
		75	.equ OCR3BH = 0x85 ; MEMORY MAPPED
		76	.equ OCR3BL = 0x84 ; MEMORY MAPPED
		77	.equ OCR3CH = 0x83 ; MEMORY MAPPED
		78	.equ OCR3CL = 0x82 ; MEMORY MAPPED
		79	.equ ICR3H = 0x81 ; MEMORY MAPPED
		80	.equ ICR3L = 0x80 ; MEMORY MAPPED
		81	.equ ETIMSK = 0x7d ; MEMORY MAPPED
		82	.equ ETIFR = 0x7c ; MEMORY MAPPED
		83	.equ TCCR1C = 0x7a ; MEMORY MAPPED
		84	.equ OCR1CH = 0x79 ; MEMORY MAPPED
		85	.equ OCR1CL = 0x78 ; MEMORY MAPPED
		86	.equ TWCR = 0x74 ; MEMORY MAPPED
		87	.equ TWDR = 0x73 ; MEMORY MAPPED
		88	.equ TWAR = 0x72 ; MEMORY MAPPED
		89	.equ TWSR = 0x71 ; MEMORY MAPPED
		90	.equ TWBR = 0x70 ; MEMORY MAPPED
		91	.equ OSCCAL = 0x6f ; MEMORY MAPPED
		92	.equ XMCRA = 0x6d ; MEMORY MAPPED
		93	.equ XMCRB = 0x6c ; MEMORY MAPPED
		94	.equ EICRA = 0x6a ; MEMORY MAPPED
		95	.equ SPMCSR = 0x68 ; MEMORY MAPPED
		96	.equ PORTG = 0x65 ; MEMORY MAPPED
		97	.equ DDRG = 0x64 ; MEMORY MAPPED
		98	.equ PING = 0x63 ; MEMORY MAPPED
		99	.equ PORTF = 0x62 ; MEMORY MAPPED
		100	.equ DDRF = 0x61 ; MEMORY MAPPED
		101	.equ SREG = 0x3f
		102	.equ SPH = 0x3e
		103	.equ SPL = 0x3d
		104	.equ XDIV = 0x3c
		105	.equ RAMPZ = 0x3b
		106	.equ EICRB = 0x3a
		107	.equ EIMSK = 0x39
		108	.equ EIFR = 0x38
		109	.equ TIMSK = 0x37
		110	.equ TIFR = 0x36
		111	.equ MCUCR = 0x35
		112	.equ MCUCSR = 0x34
		113	.equ TCCR0 = 0x33
		114	.equ TCNT0 = 0x32
		115	.equ OCR0 = 0x31
		116	.equ ASSR = 0x30
		117	.equ TCCR1A = 0x2f
		118	.equ TCCR1B = 0x2e
		119	.equ TCNT1H = 0x2d
		120	.equ TCNT1L = 0x2c
		121	.equ OCR1AH = 0x2b
		122	.equ OCR1AL = 0x2a
		123	.equ OCR1BH = 0x29
		124	.equ OCR1BL = 0x28
		125	.equ ICR1H = 0x27
		126	.equ ICR1L = 0x26
		127	.equ TCCR2 = 0x25
		128	.equ TCNT2 = 0x24
		129	.equ OCR2 = 0x23
		130	.equ OCDR = 0x22
		131	.equ WDTCR = 0x21
		132	.equ SFIOR = 0x20
		133	.equ EEARH = 0x1f
		134	.equ EEARL = 0x1e
		135	.equ EEDR = 0x1d
		136	.equ EECR = 0x1c
		137	.equ PORTA = 0x1b
		138	.equ DDRA = 0x1a
		139	.equ PINA = 0x19
		140	.equ PORTB = 0x18
		141	.equ DDRB = 0x17
		142	.equ PINB = 0x16
		143	.equ PORTC = 0x15
		144	.equ DDRC = 0x14
		145	.equ PINC = 0x13
		146	.equ PORTD = 0x12
		147	.equ DDRD = 0x11
		148	.equ PIND = 0x10
		149	.equ SPDR = 0x0f
		150	.equ SPSR = 0x0e
		151	.equ SPCR = 0x0d
		152	.equ UDR0 = 0x0c
		153	.equ UCSR0A = 0x0b
		154	.equ UCSR0B = 0x0a
		155	.equ UBRR0L = 0x09
		156	.equ ACSR = 0x08
		157	.equ ADMUX = 0x07
		158	.equ ADCSRA = 0x06
		159	.equ ADCH = 0x05
		160	.equ ADCL = 0x04
		161	.equ PORTE = 0x03
		162	.equ DDRE = 0x02
		163	.equ PINE = 0x01
		164	.equ PINF = 0x00
		165
		166
		167	; *** BIT DEFINITIONS ************************************************
		168
		169	; *** ANALOG_COMPARATOR **********
		170	; SFIOR - Special Function IO Register
		171	.equ ACME = 3 ; Analog Comparator Multiplexer Enable
		172
		173	; ACSR - Analog Comparator Control And Status Register
		174	.equ ACIS0 = 0 ; Analog Comparator Interrupt Mode Select bit 0
		175	.equ ACIS1 = 1 ; Analog Comparator Interrupt Mode Select bit 1
		176	.equ ACIC = 2 ; Analog Comparator Input Capture Enable
		177	.equ ACIE = 3 ; Analog Comparator Interrupt Enable
		178	.equ ACI = 4 ; Analog Comparator Interrupt Flag
		179	.equ ACO = 5 ; Analog Compare Output
		180	.equ ACBG = 6 ; Analog Comparator Bandgap Select
		181	.equ ACD = 7 ; Analog Comparator Disable
		182
		183
		184	; *** AD_CONVERTER ***************
		185	; ADMUX - The ADC multiplexer Selection Register
		186	.equ MUX0 = 0 ; Analog Channel and Gain Selection Bits
		187	.equ MUX1 = 1 ; Analog Channel and Gain Selection Bits
		188	.equ MUX2 = 2 ; Analog Channel and Gain Selection Bits
		189	.equ MUX3 = 3 ; Analog Channel and Gain Selection Bits
		190	.equ MUX4 = 4 ; Analog Channel and Gain Selection Bits
		191	.equ ADLAR = 5 ; Left Adjust Result
		192	.equ REFS0 = 6 ; Reference Selection Bit 0
		193	.equ REFS1 = 7 ; Reference Selection Bit 1
		194
		195	; ADCSRA - The ADC Control and Status register
		196	.equ ADCSR = ADCSRA ; For compatibility
		197	.equ ADPS0 = 0 ; ADC Prescaler Select Bits
		198	.equ ADPS1 = 1 ; ADC Prescaler Select Bits
		199	.equ ADPS2 = 2 ; ADC Prescaler Select Bits
		200	.equ ADIE = 3 ; ADC Interrupt Enable
		201	.equ ADIF = 4 ; ADC Interrupt Flag
		202	.equ ADFR = 5 ; ADC Free Running Select
		203	.equ ADSC = 6 ; ADC Start Conversion
		204	.equ ADEN = 7 ; ADC Enable
		205
		206	; ADCH - ADC Data Register High Byte
		207	.equ ADCH0 = 0 ; ADC Data Register High Byte Bit 0
		208	.equ ADCH1 = 1 ; ADC Data Register High Byte Bit 1
		209	.equ ADCH2 = 2 ; ADC Data Register High Byte Bit 2
		210	.equ ADCH3 = 3 ; ADC Data Register High Byte Bit 3
		211	.equ ADCH4 = 4 ; ADC Data Register High Byte Bit 4
		212	.equ ADCH5 = 5 ; ADC Data Register High Byte Bit 5
		213	.equ ADCH6 = 6 ; ADC Data Register High Byte Bit 6
		214	.equ ADCH7 = 7 ; ADC Data Register High Byte Bit 7
		215
		216	; ADCL - ADC Data Register Low Byte
		217	.equ ADCL0 = 0 ; ADC Data Register Low Byte Bit 0
		218	.equ ADCL1 = 1 ; ADC Data Register Low Byte Bit 1
		219	.equ ADCL2 = 2 ; ADC Data Register Low Byte Bit 2
		220	.equ ADCL3 = 3 ; ADC Data Register Low Byte Bit 3
		221	.equ ADCL4 = 4 ; ADC Data Register Low Byte Bit 4
		222	.equ ADCL5 = 5 ; ADC Data Register Low Byte Bit 5
		223	.equ ADCL6 = 6 ; ADC Data Register Low Byte Bit 6
		224	.equ ADCL7 = 7 ; ADC Data Register Low Byte Bit 7
		225
		226
		227	; *** SPI ************************
		228	; SPDR - SPI Data Register
		229	.equ SPDR0 = 0 ; SPI Data Register bit 0
		230	.equ SPDR1 = 1 ; SPI Data Register bit 1
		231	.equ SPDR2 = 2 ; SPI Data Register bit 2
		232	.equ SPDR3 = 3 ; SPI Data Register bit 3
		233	.equ SPDR4 = 4 ; SPI Data Register bit 4
		234	.equ SPDR5 = 5 ; SPI Data Register bit 5
		235	.equ SPDR6 = 6 ; SPI Data Register bit 6
		236	.equ SPDR7 = 7 ; SPI Data Register bit 7
		237
		238	; SPSR - SPI Status Register
		239	.equ SPI2X = 0 ; Double SPI Speed Bit
		240	.equ WCOL = 6 ; Write Collision Flag
		241	.equ SPIF = 7 ; SPI Interrupt Flag
		242
		243	; SPCR - SPI Control Register
		244	.equ SPR0 = 0 ; SPI Clock Rate Select 0
		245	.equ SPR1 = 1 ; SPI Clock Rate Select 1
		246	.equ CPHA = 2 ; Clock Phase
		247	.equ CPOL = 3 ; Clock polarity
		248	.equ MSTR = 4 ; Master/Slave Select
		249	.equ DORD = 5 ; Data Order
		250	.equ SPE = 6 ; SPI Enable
		251	.equ SPIE = 7 ; SPI Interrupt Enable
		252
		253
		254	; *** TWI ************************
		255	; TWBR - TWI Bit Rate register
		256	.equ I2BR = TWBR ; For compatibility
		257	.equ TWBR0 = 0 ;
		258	.equ TWBR1 = 1 ;
		259	.equ TWBR2 = 2 ;
		260	.equ TWBR3 = 3 ;
		261	.equ TWBR4 = 4 ;
		262	.equ TWBR5 = 5 ;
		263	.equ TWBR6 = 6 ;
		264	.equ TWBR7 = 7 ;
		265
		266	; TWCR - TWI Control Register
		267	.equ I2CR = TWCR ; For compatibility
		268	.equ TWIE = 0 ; TWI Interrupt Enable
		269	.equ I2IE = TWIE ; For compatibility
		270	.equ TWEN = 2 ; TWI Enable Bit
		271	.equ I2EN = TWEN ; For compatibility
		272	.equ ENI2C = TWEN ; For compatibility
		273	.equ TWWC = 3 ; TWI Write Collition Flag
		274	.equ I2WC = TWWC ; For compatibility
		275	.equ TWSTO = 4 ; TWI Stop Condition Bit
		276	.equ I2STO = TWSTO ; For compatibility
		277	.equ TWSTA = 5 ; TWI Start Condition Bit
		278	.equ I2STA = TWSTA ; For compatibility
		279	.equ TWEA = 6 ; TWI Enable Acknowledge Bit
		280	.equ I2EA = TWEA ; For compatibility
		281	.equ TWINT = 7 ; TWI Interrupt Flag
		282	.equ I2INT = TWINT ; For compatibility
		283
		284	; TWSR - TWI Status Register
		285	.equ I2SR = TWSR ; For compatibility
		286	.equ TWPS0 = 0 ; TWI Prescaler
		287	.equ TWS0 = TWPS0 ; For compatibility
		288	.equ I2GCE = TWPS0 ; For compatibility
		289	.equ TWPS1 = 1 ; TWI Prescaler
		290	.equ TWS1 = TWPS1 ; For compatibility
		291	.equ TWS3 = 3 ; TWI Status
		292	.equ I2S3 = TWS3 ; For compatibility
		293	.equ TWS4 = 4 ; TWI Status
		294	.equ I2S4 = TWS4 ; For compatibility
		295	.equ TWS5 = 5 ; TWI Status
		296	.equ I2S5 = TWS5 ; For compatibility
		297	.equ TWS6 = 6 ; TWI Status
		298	.equ I2S6 = TWS6 ; For compatibility
		299	.equ TWS7 = 7 ; TWI Status
		300	.equ I2S7 = TWS7 ; For compatibility
		301
		302	; TWDR - TWI Data register
		303	.equ I2DR = TWDR ; For compatibility
		304	.equ TWD0 = 0 ; TWI Data Register Bit 0
		305	.equ TWD1 = 1 ; TWI Data Register Bit 1
		306	.equ TWD2 = 2 ; TWI Data Register Bit 2
		307	.equ TWD3 = 3 ; TWI Data Register Bit 3
		308	.equ TWD4 = 4 ; TWI Data Register Bit 4
		309	.equ TWD5 = 5 ; TWI Data Register Bit 5
		310	.equ TWD6 = 6 ; TWI Data Register Bit 6
		311	.equ TWD7 = 7 ; TWI Data Register Bit 7
		312
		313	; TWAR - TWI (Slave) Address register
		314	.equ I2AR = TWAR ; For compatibility
		315	.equ TWGCE = 0 ; TWI General Call Recognition Enable Bit
		316	.equ TWA0 = 1 ; TWI (Slave) Address register Bit 0
		317	.equ TWA1 = 2 ; TWI (Slave) Address register Bit 1
		318	.equ TWA2 = 3 ; TWI (Slave) Address register Bit 2
		319	.equ TWA3 = 4 ; TWI (Slave) Address register Bit 3
		320	.equ TWA4 = 5 ; TWI (Slave) Address register Bit 4
		321	.equ TWA5 = 6 ; TWI (Slave) Address register Bit 5
		322	.equ TWA6 = 7 ; TWI (Slave) Address register Bit 6
		323
		324
		325	; *** USART0 *********************
		326	; UDR0 - USART I/O Data Register
		327	.equ UDR00 = 0 ; USART I/O Data Register bit 0
		328	.equ UDR01 = 1 ; USART I/O Data Register bit 1
		329	.equ UDR02 = 2 ; USART I/O Data Register bit 2
		330	.equ UDR03 = 3 ; USART I/O Data Register bit 3
		331	.equ UDR04 = 4 ; USART I/O Data Register bit 4
		332	.equ UDR05 = 5 ; USART I/O Data Register bit 5
		333	.equ UDR06 = 6 ; USART I/O Data Register bit 6
		334	.equ UDR07 = 7 ; USART I/O Data Register bit 7
		335
		336	; UCSR0A - USART Control and Status Register A
		337	.equ MPCM0 = 0 ; Multi-processor Communication Mode
		338	.equ U2X0 = 1 ; Double the USART transmission speed
		339	.equ UPE0 = 2 ; Parity Error
		340	.equ DOR0 = 3 ; Data overRun
		341	.equ FE0 = 4 ; Framing Error
		342	.equ UDRE0 = 5 ; USART Data Register Empty
		343	.equ TXC0 = 6 ; USART Transmitt Complete
		344	.equ RXC0 = 7 ; USART Receive Complete
		345
		346	; UCSR0B - USART Control and Status Register B
		347	.equ TXB80 = 0 ; Transmit Data Bit 8
		348	.equ RXB80 = 1 ; Receive Data Bit 8
		349	.equ UCSZ02 = 2 ; Character Size
		350	.equ UCSZ2 = UCSZ02 ; For compatibility
		351	.equ TXEN0 = 3 ; Transmitter Enable
		352	.equ RXEN0 = 4 ; Receiver Enable
		353	.equ UDRIE0 = 5 ; USART Data register Empty Interrupt Enable
		354	.equ TXCIE0 = 6 ; TX Complete Interrupt Enable
		355	.equ RXCIE0 = 7 ; RX Complete Interrupt Enable
		356
		357	; UCSR0C - USART Control and Status Register C
		358	.equ UCPOL0 = 0 ; Clock Polarity
		359	.equ UCSZ00 = 1 ; Character Size
		360	.equ UCSZ01 = 2 ; Character Size
		361	.equ USBS0 = 3 ; Stop Bit Select
		362	.equ UPM00 = 4 ; Parity Mode Bit 0
		363	.equ UPM01 = 5 ; Parity Mode Bit 1
		364	.equ UMSEL0 = 6 ; USART Mode Select
		365
		366
		367	; *** USART1 *********************
		368	; UDR1 - USART I/O Data Register
		369	.equ UDR10 = 0 ; USART I/O Data Register bit 0
		370	.equ UDR11 = 1 ; USART I/O Data Register bit 1
		371	.equ UDR12 = 2 ; USART I/O Data Register bit 2
		372	.equ UDR13 = 3 ; USART I/O Data Register bit 3
		373	.equ UDR14 = 4 ; USART I/O Data Register bit 4
		374	.equ UDR15 = 5 ; USART I/O Data Register bit 5
		375	.equ UDR16 = 6 ; USART I/O Data Register bit 6
		376	.equ UDR17 = 7 ; USART I/O Data Register bit 7
		377
		378	; UCSR1A - USART Control and Status Register A
		379	.equ MPCM1 = 0 ; Multi-processor Communication Mode
		380	.equ U2X1 = 1 ; Double the USART transmission speed
		381	.equ UPE1 = 2 ; Parity Error
		382	.equ DOR1 = 3 ; Data overRun
		383	.equ FE1 = 4 ; Framing Error
		384	.equ UDRE1 = 5 ; USART Data Register Empty
		385	.equ TXC1 = 6 ; USART Transmitt Complete
		386	.equ RXC1 = 7 ; USART Receive Complete
		387
		388	; UCSR1B - USART Control and Status Register B
		389	.equ TXB81 = 0 ; Transmit Data Bit 8
		390	.equ RXB81 = 1 ; Receive Data Bit 8
		391	.equ UCSZ12 = 2 ; Character Size
		392	.equ TXEN1 = 3 ; Transmitter Enable
		393	.equ RXEN1 = 4 ; Receiver Enable
		394	.equ UDRIE1 = 5 ; USART Data register Empty Interrupt Enable
		395	.equ TXCIE1 = 6 ; TX Complete Interrupt Enable
		396	.equ RXCIE1 = 7 ; RX Complete Interrupt Enable
		397
		398	; UCSR1C - USART Control and Status Register C
		399	.equ UCPOL1 = 0 ; Clock Polarity
		400	.equ UCSZ10 = 1 ; Character Size
		401	.equ UCSZ11 = 2 ; Character Size
		402	.equ USBS1 = 3 ; Stop Bit Select
		403	.equ UPM10 = 4 ; Parity Mode Bit 0
		404	.equ UPM11 = 5 ; Parity Mode Bit 1
		405	.equ UMSEL1 = 6 ; USART Mode Select
		406
		407
		408	; *** CPU ************************
		409	; SREG - Status Register
		410	.equ SREG_C = 0 ; Carry Flag
		411	.equ SREG_Z = 1 ; Zero Flag
		412	.equ SREG_N = 2 ; Negative Flag
		413	.equ SREG_V = 3 ; Two's Complement Overflow Flag
		414	.equ SREG_S = 4 ; Sign Bit
		415	.equ SREG_H = 5 ; Half Carry Flag
		416	.equ SREG_T = 6 ; Bit Copy Storage
		417	.equ SREG_I = 7 ; Global Interrupt Enable
		418
		419	; MCUCR - MCU Control Register
		420	.equ IVCE = 0 ; Interrupt Vector Change Enable
		421	.equ IVSEL = 1 ; Interrupt Vector Select
		422	.equ SM2 = 2 ; Sleep Mode Select
		423	.equ SM0 = 3 ; Sleep Mode Select
		424	.equ SM1 = 4 ; Sleep Mode Select
		425	.equ SE = 5 ; Sleep Enable
		426	.equ SRW10 = 6 ; External SRAM Wait State Select
		427	.equ SRE = 7 ; External SRAM Enable
		428
		429	; XMCRA - External Memory Control Register A
		430	.equ SRW11 = 1 ; Wait state select bit upper page
		431	.equ SRW00 = 2 ; Wait state select bit lower page
		432	.equ SRW01 = 3 ; Wait state select bit lower page
		433	.equ SRL0 = 4 ; Wait state page limit
		434	.equ SRL1 = 5 ; Wait state page limit
		435	.equ SRL2 = 6 ; Wait state page limit
		436
		437	; XMCRB - External Memory Control Register B
		438	.equ XMM0 = 0 ; External Memory High Mask
		439	.equ XMM1 = 1 ; External Memory High Mask
		440	.equ XMM2 = 2 ; External Memory High Mask
		441	.equ XMBK = 7 ; External Memory Bus Keeper Enable
		442
		443	; OSCCAL - Oscillator Calibration Value
		444	.equ CAL0 = 0 ; Oscillator Calibration Value
		445	.equ CAL1 = 1 ; Oscillator Calibration Value
		446	.equ CAL2 = 2 ; Oscillator Calibration Value
		447	.equ CAL3 = 3 ; Oscillator Calibration Value
		448	.equ CAL4 = 4 ; Oscillator Calibration Value
		449	.equ CAL5 = 5 ; Oscillator Calibration Value
		450	.equ CAL6 = 6 ; Oscillator Calibration Value
		451	.equ CAL7 = 7 ; Oscillator Calibration Value
		452
		453	; XDIV - XTAL Divide Control Register
		454	.equ XDIV0 = 0 ; XTAl Divide Select Bit 0
		455	.equ XDIV1 = 1 ; XTAl Divide Select Bit 1
		456	.equ XDIV2 = 2 ; XTAl Divide Select Bit 2
		457	.equ XDIV3 = 3 ; XTAl Divide Select Bit 3
		458	.equ XDIV4 = 4 ; XTAl Divide Select Bit 4
		459	.equ XDIV5 = 5 ; XTAl Divide Select Bit 5
		460	.equ XDIV6 = 6 ; XTAl Divide Select Bit 6
		461	.equ XDIVEN = 7 ; XTAL Divide Enable
		462
		463	; MCUCSR - MCU Control And Status Register
		464	.equ PORF = 0 ; Power-on reset flag
		465	.equ EXTRF = 1 ; External Reset Flag
		466	.equ BORF = 2 ; Brown-out Reset Flag
		467	.equ WDRF = 3 ; Watchdog Reset Flag
		468	.equ JTRF = 4 ; JTAG Reset Flag
		469	.equ JTD = 7 ; JTAG Interface Disable
		470
		471	; RAMPZ - RAM Page Z Select Register
		472	.equ RAMPZ0 = 0 ; RAM Page Z Select Register Bit 0
		473
		474
		475	; *** BOOT_LOAD ******************
		476	; SPMCSR - Store Program Memory Control Register
		477	.equ SPMCR = SPMCSR ; For compatibility
		478	.equ SPMEN = 0 ; Store Program Memory Enable
		479	.equ PGERS = 1 ; Page Erase
		480	.equ PGWRT = 2 ; Page Write
		481	.equ BLBSET = 3 ; Boot Lock Bit Set
		482	.equ RWWSRE = 4 ; Read While Write section read enable
		483	.equ ASRE = RWWSRE ; For compatibility
		484	.equ RWWSB = 6 ; Read While Write Section Busy
		485	.equ ASB = RWWSB ; For compatibility
		486	.equ SPMIE = 7 ; SPM Interrupt Enable
		487
		488
		489	; *** JTAG ***********************
		490	; OCDR - On-Chip Debug Related Register in I/O Memory
		491	.equ OCDR0 = 0 ; On-Chip Debug Register Bit 0
		492	.equ OCDR1 = 1 ; On-Chip Debug Register Bit 1
		493	.equ OCDR2 = 2 ; On-Chip Debug Register Bit 2
		494	.equ OCDR3 = 3 ; On-Chip Debug Register Bit 3
		495	.equ OCDR4 = 4 ; On-Chip Debug Register Bit 4
		496	.equ OCDR5 = 5 ; On-Chip Debug Register Bit 5
		497	.equ OCDR6 = 6 ; On-Chip Debug Register Bit 6
		498	.equ OCDR7 = 7 ; On-Chip Debug Register Bit 7
		499	.equ IDRD = OCDR7 ; For compatibility
		500
		501	; MCUCSR - MCU Control And Status Register
		502	;.equ JTRF = 4 ; JTAG Reset Flag
		503	;.equ JTD = 7 ; JTAG Interface Disable
		504
		505
		506	; *** MISC ***********************
		507	; SFIOR - Special Function IO Register
		508	.equ PSR321 = 0 ; Prescaler Reset Timer/Counter3, Timer/Counter2, and Timer/Counter1
		509	.equ PSR1 = PSR321 ; For compatibility
		510	.equ PSR2 = PSR321 ; For compatibility
		511	.equ PSR3 = PSR321 ; For compatibility
		512	.equ PSR0 = 1 ; Prescaler Reset Timer/Counter0
		513	.equ PUD = 2 ; Pull Up Disable
		514	;.equ ACME = 3 ; Analog Comparator Multiplexer Enable
		515	.equ TSM = 7 ; Timer/Counter Synchronization Mode
		516
		517
		518	; *** EXTERNAL_INTERRUPT *********
		519	; EICRA - External Interrupt Control Register A
		520	.equ ISC00 = 0 ; External Interrupt Sense Control Bit
		521	.equ ISC01 = 1 ; External Interrupt Sense Control Bit
		522	.equ ISC10 = 2 ; External Interrupt Sense Control Bit
		523	.equ ISC11 = 3 ; External Interrupt Sense Control Bit
		524	.equ ISC20 = 4 ; External Interrupt Sense Control Bit
		525	.equ ISC21 = 5 ; External Interrupt Sense Control Bit
		526	.equ ISC30 = 6 ; External Interrupt Sense Control Bit
		527	.equ ISC31 = 7 ; External Interrupt Sense Control Bit
		528
		529	; EICRB - External Interrupt Control Register B
		530	.equ ISC40 = 0 ; External Interrupt 7-4 Sense Control Bit
		531	.equ ISC41 = 1 ; External Interrupt 7-4 Sense Control Bit
		532	.equ ISC50 = 2 ; External Interrupt 7-4 Sense Control Bit
		533	.equ ISC51 = 3 ; External Interrupt 7-4 Sense Control Bit
		534	.equ ISC60 = 4 ; External Interrupt 7-4 Sense Control Bit
		535	.equ ISC61 = 5 ; External Interrupt 7-4 Sense Control Bit
		536	.equ ISC70 = 6 ; External Interrupt 7-4 Sense Control Bit
		537	.equ ISC71 = 7 ; External Interrupt 7-4 Sense Control Bit
		538
		539	; EIMSK - External Interrupt Mask Register
		540	.equ GICR = EIMSK ; For compatibility
		541	.equ GIMSK = EIMSK ; For compatibility
		542	.equ INT0 = 0 ; External Interrupt Request 0 Enable
		543	.equ INT1 = 1 ; External Interrupt Request 1 Enable
		544	.equ INT2 = 2 ; External Interrupt Request 2 Enable
		545	.equ INT3 = 3 ; External Interrupt Request 3 Enable
		546	.equ INT4 = 4 ; External Interrupt Request 4 Enable
		547	.equ INT5 = 5 ; External Interrupt Request 5 Enable
		548	.equ INT6 = 6 ; External Interrupt Request 6 Enable
		549	.equ INT7 = 7 ; External Interrupt Request 7 Enable
		550
		551	; EIFR - External Interrupt Flag Register
		552	.equ GIFR = EIFR ; For compatibility
		553	.equ INTF0 = 0 ; External Interrupt Flag 0
		554	.equ INTF1 = 1 ; External Interrupt Flag 1
		555	.equ INTF2 = 2 ; External Interrupt Flag 2
		556	.equ INTF3 = 3 ; External Interrupt Flag 3
		557	.equ INTF4 = 4 ; External Interrupt Flag 4
		558	.equ INTF5 = 5 ; External Interrupt Flag 5
		559	.equ INTF6 = 6 ; External Interrupt Flag 6
		560	.equ INTF7 = 7 ; External Interrupt Flag 7
		561
		562
		563	; *** EEPROM *********************
		564	; EEDR - EEPROM Data Register
		565	.equ EEDR0 = 0 ; EEPROM Data Register bit 0
		566	.equ EEDR1 = 1 ; EEPROM Data Register bit 1
		567	.equ EEDR2 = 2 ; EEPROM Data Register bit 2
		568	.equ EEDR3 = 3 ; EEPROM Data Register bit 3
		569	.equ EEDR4 = 4 ; EEPROM Data Register bit 4
		570	.equ EEDR5 = 5 ; EEPROM Data Register bit 5
		571	.equ EEDR6 = 6 ; EEPROM Data Register bit 6
		572	.equ EEDR7 = 7 ; EEPROM Data Register bit 7
		573
		574	; EECR - EEPROM Control Register
		575	.equ EERE = 0 ; EEPROM Read Enable
		576	.equ EEWE = 1 ; EEPROM Write Enable
		577	.equ EEMWE = 2 ; EEPROM Master Write Enable
		578	.equ EERIE = 3 ; EEPROM Ready Interrupt Enable
		579
		580
		581	; *** PORTA **********************
		582	; PORTA - Port A Data Register
		583	.equ PORTA0 = 0 ; Port A Data Register bit 0
		584	.equ PA0 = 0 ; For compatibility
		585	.equ PORTA1 = 1 ; Port A Data Register bit 1
		586	.equ PA1 = 1 ; For compatibility
		587	.equ PORTA2 = 2 ; Port A Data Register bit 2
		588	.equ PA2 = 2 ; For compatibility
		589	.equ PORTA3 = 3 ; Port A Data Register bit 3
		590	.equ PA3 = 3 ; For compatibility
		591	.equ PORTA4 = 4 ; Port A Data Register bit 4
		592	.equ PA4 = 4 ; For compatibility
		593	.equ PORTA5 = 5 ; Port A Data Register bit 5
		594	.equ PA5 = 5 ; For compatibility
		595	.equ PORTA6 = 6 ; Port A Data Register bit 6
		596	.equ PA6 = 6 ; For compatibility
		597	.equ PORTA7 = 7 ; Port A Data Register bit 7
		598	.equ PA7 = 7 ; For compatibility
		599
		600	; DDRA - Port A Data Direction Register
		601	.equ DDA0 = 0 ; Data Direction Register, Port A, bit 0
		602	.equ DDA1 = 1 ; Data Direction Register, Port A, bit 1
		603	.equ DDA2 = 2 ; Data Direction Register, Port A, bit 2
		604	.equ DDA3 = 3 ; Data Direction Register, Port A, bit 3
		605	.equ DDA4 = 4 ; Data Direction Register, Port A, bit 4
		606	.equ DDA5 = 5 ; Data Direction Register, Port A, bit 5
		607	.equ DDA6 = 6 ; Data Direction Register, Port A, bit 6
		608	.equ DDA7 = 7 ; Data Direction Register, Port A, bit 7
		609
		610	; PINA - Port A Input Pins
		611	.equ PINA0 = 0 ; Input Pins, Port A bit 0
		612	.equ PINA1 = 1 ; Input Pins, Port A bit 1
		613	.equ PINA2 = 2 ; Input Pins, Port A bit 2
		614	.equ PINA3 = 3 ; Input Pins, Port A bit 3
		615	.equ PINA4 = 4 ; Input Pins, Port A bit 4
		616	.equ PINA5 = 5 ; Input Pins, Port A bit 5
		617	.equ PINA6 = 6 ; Input Pins, Port A bit 6
		618	.equ PINA7 = 7 ; Input Pins, Port A bit 7
		619
		620
		621	; *** PORTB **********************
		622	; PORTB - Port B Data Register
		623	.equ PORTB0 = 0 ; Port B Data Register bit 0
		624	.equ PB0 = 0 ; For compatibility
		625	.equ PORTB1 = 1 ; Port B Data Register bit 1
		626	.equ PB1 = 1 ; For compatibility
		627	.equ PORTB2 = 2 ; Port B Data Register bit 2
		628	.equ PB2 = 2 ; For compatibility
		629	.equ PORTB3 = 3 ; Port B Data Register bit 3
		630	.equ PB3 = 3 ; For compatibility
		631	.equ PORTB4 = 4 ; Port B Data Register bit 4
		632	.equ PB4 = 4 ; For compatibility
		633	.equ PORTB5 = 5 ; Port B Data Register bit 5
		634	.equ PB5 = 5 ; For compatibility
		635	.equ PORTB6 = 6 ; Port B Data Register bit 6
		636	.equ PB6 = 6 ; For compatibility
		637	.equ PORTB7 = 7 ; Port B Data Register bit 7
		638	.equ PB7 = 7 ; For compatibility
		639
		640	; DDRB - Port B Data Direction Register
		641	.equ DDB0 = 0 ; Port B Data Direction Register bit 0
		642	.equ DDB1 = 1 ; Port B Data Direction Register bit 1
		643	.equ DDB2 = 2 ; Port B Data Direction Register bit 2
		644	.equ DDB3 = 3 ; Port B Data Direction Register bit 3
		645	.equ DDB4 = 4 ; Port B Data Direction Register bit 4
		646	.equ DDB5 = 5 ; Port B Data Direction Register bit 5
		647	.equ DDB6 = 6 ; Port B Data Direction Register bit 6
		648	.equ DDB7 = 7 ; Port B Data Direction Register bit 7
		649
		650	; PINB - Port B Input Pins
		651	.equ PINB0 = 0 ; Port B Input Pins bit 0
		652	.equ PINB1 = 1 ; Port B Input Pins bit 1
		653	.equ PINB2 = 2 ; Port B Input Pins bit 2
		654	.equ PINB3 = 3 ; Port B Input Pins bit 3
		655	.equ PINB4 = 4 ; Port B Input Pins bit 4
		656	.equ PINB5 = 5 ; Port B Input Pins bit 5
		657	.equ PINB6 = 6 ; Port B Input Pins bit 6
		658	.equ PINB7 = 7 ; Port B Input Pins bit 7
		659
		660
		661	; *** PORTC **********************
		662	; PORTC - Port C Data Register
		663	.equ PORTC0 = 0 ; Port C Data Register bit 0
		664	.equ PC0 = 0 ; For compatibility
		665	.equ PORTC1 = 1 ; Port C Data Register bit 1
		666	.equ PC1 = 1 ; For compatibility
		667	.equ PORTC2 = 2 ; Port C Data Register bit 2
		668	.equ PC2 = 2 ; For compatibility
		669	.equ PORTC3 = 3 ; Port C Data Register bit 3
		670	.equ PC3 = 3 ; For compatibility
		671	.equ PORTC4 = 4 ; Port C Data Register bit 4
		672	.equ PC4 = 4 ; For compatibility
		673	.equ PORTC5 = 5 ; Port C Data Register bit 5
		674	.equ PC5 = 5 ; For compatibility
		675	.equ PORTC6 = 6 ; Port C Data Register bit 6
		676	.equ PC6 = 6 ; For compatibility
		677	.equ PORTC7 = 7 ; Port C Data Register bit 7
		678	.equ PC7 = 7 ; For compatibility
		679
		680	; DDRC - Port C Data Direction Register
		681	.equ DDC0 = 0 ; Port C Data Direction Register bit 0
		682	.equ DDC1 = 1 ; Port C Data Direction Register bit 1
		683	.equ DDC2 = 2 ; Port C Data Direction Register bit 2
		684	.equ DDC3 = 3 ; Port C Data Direction Register bit 3
		685	.equ DDC4 = 4 ; Port C Data Direction Register bit 4
		686	.equ DDC5 = 5 ; Port C Data Direction Register bit 5
		687	.equ DDC6 = 6 ; Port C Data Direction Register bit 6
		688	.equ DDC7 = 7 ; Port C Data Direction Register bit 7
		689
		690	; PINC - Port C Input Pins
		691	.equ PINC0 = 0 ; Port C Input Pins bit 0
		692	.equ PINC1 = 1 ; Port C Input Pins bit 1
		693	.equ PINC2 = 2 ; Port C Input Pins bit 2
		694	.equ PINC3 = 3 ; Port C Input Pins bit 3
		695	.equ PINC4 = 4 ; Port C Input Pins bit 4
		696	.equ PINC5 = 5 ; Port C Input Pins bit 5
		697	.equ PINC6 = 6 ; Port C Input Pins bit 6
		698	.equ PINC7 = 7 ; Port C Input Pins bit 7
		699
		700
		701	; *** PORTD **********************
		702	; PORTD - Port D Data Register
		703	.equ PORTD0 = 0 ; Port D Data Register bit 0
		704	.equ PD0 = 0 ; For compatibility
		705	.equ PORTD1 = 1 ; Port D Data Register bit 1
		706	.equ PD1 = 1 ; For compatibility
		707	.equ PORTD2 = 2 ; Port D Data Register bit 2
		708	.equ PD2 = 2 ; For compatibility
		709	.equ PORTD3 = 3 ; Port D Data Register bit 3
		710	.equ PD3 = 3 ; For compatibility
		711	.equ PORTD4 = 4 ; Port D Data Register bit 4
		712	.equ PD4 = 4 ; For compatibility
		713	.equ PORTD5 = 5 ; Port D Data Register bit 5
		714	.equ PD5 = 5 ; For compatibility
		715	.equ PORTD6 = 6 ; Port D Data Register bit 6
		716	.equ PD6 = 6 ; For compatibility
		717	.equ PORTD7 = 7 ; Port D Data Register bit 7
		718	.equ PD7 = 7 ; For compatibility
		719
		720	; DDRD - Port D Data Direction Register
		721	.equ DDD0 = 0 ; Port D Data Direction Register bit 0
		722	.equ DDD1 = 1 ; Port D Data Direction Register bit 1
		723	.equ DDD2 = 2 ; Port D Data Direction Register bit 2
		724	.equ DDD3 = 3 ; Port D Data Direction Register bit 3
		725	.equ DDD4 = 4 ; Port D Data Direction Register bit 4
		726	.equ DDD5 = 5 ; Port D Data Direction Register bit 5
		727	.equ DDD6 = 6 ; Port D Data Direction Register bit 6
		728	.equ DDD7 = 7 ; Port D Data Direction Register bit 7
		729
		730	; PIND - Port D Input Pins
		731	.equ PIND0 = 0 ; Port D Input Pins bit 0
		732	.equ PIND1 = 1 ; Port D Input Pins bit 1
		733	.equ PIND2 = 2 ; Port D Input Pins bit 2
		734	.equ PIND3 = 3 ; Port D Input Pins bit 3
		735	.equ PIND4 = 4 ; Port D Input Pins bit 4
		736	.equ PIND5 = 5 ; Port D Input Pins bit 5
		737	.equ PIND6 = 6 ; Port D Input Pins bit 6
		738	.equ PIND7 = 7 ; Port D Input Pins bit 7
		739
		740
		741	; *** PORTE **********************
		742	; PORTE - Data Register, Port E
		743	.equ PORTE0 = 0 ;
		744	.equ PE0 = 0 ; For compatibility
		745	.equ PORTE1 = 1 ;
		746	.equ PE1 = 1 ; For compatibility
		747	.equ PORTE2 = 2 ;
		748	.equ PE2 = 2 ; For compatibility
		749	.equ PORTE3 = 3 ;
		750	.equ PE3 = 3 ; For compatibility
		751	.equ PORTE4 = 4 ;
		752	.equ PE4 = 4 ; For compatibility
		753	.equ PORTE5 = 5 ;
		754	.equ PE5 = 5 ; For compatibility
		755	.equ PORTE6 = 6 ;
		756	.equ PE6 = 6 ; For compatibility
		757	.equ PORTE7 = 7 ;
		758	.equ PE7 = 7 ; For compatibility
		759
		760	; DDRE - Data Direction Register, Port E
		761	.equ DDE0 = 0 ;
		762	.equ DDE1 = 1 ;
		763	.equ DDE2 = 2 ;
		764	.equ DDE3 = 3 ;
		765	.equ DDE4 = 4 ;
		766	.equ DDE5 = 5 ;
		767	.equ DDE6 = 6 ;
		768	.equ DDE7 = 7 ;
		769
		770	; PINE - Input Pins, Port E
		771	.equ PINE0 = 0 ;
		772	.equ PINE1 = 1 ;
		773	.equ PINE2 = 2 ;
		774	.equ PINE3 = 3 ;
		775	.equ PINE4 = 4 ;
		776	.equ PINE5 = 5 ;
		777	.equ PINE6 = 6 ;
		778	.equ PINE7 = 7 ;
		779
		780
		781	; *** PORTF **********************
		782	; PORTF - Data Register, Port F
		783	.equ PORTF0 = 0 ;
		784	.equ PF0 = 0 ; For compatibility
		785	.equ PORTF1 = 1 ;
		786	.equ PF1 = 1 ; For compatibility
		787	.equ PORTF2 = 2 ;
		788	.equ PF2 = 2 ; For compatibility
		789	.equ PORTF3 = 3 ;
		790	.equ PF3 = 3 ; For compatibility
		791	.equ PORTF4 = 4 ;
		792	.equ PF4 = 4 ; For compatibility
		793	.equ PORTF5 = 5 ;
		794	.equ PF5 = 5 ; For compatibility
		795	.equ PORTF6 = 6 ;
		796	.equ PF6 = 6 ; For compatibility
		797	.equ PORTF7 = 7 ;
		798	.equ PF7 = 7 ; For compatibility
		799
		800	; DDRF - Data Direction Register, Port F
		801	.equ DDF0 = 0 ;
		802	.equ DDF1 = 1 ;
		803	.equ DDF2 = 2 ;
		804	.equ DDF3 = 3 ;
		805	.equ DDF4 = 4 ;
		806	.equ DDF5 = 5 ;
		807	.equ DDF6 = 6 ;
		808	.equ DDF7 = 7 ;
		809
		810	; PINF - Input Pins, Port F
		811	.equ PINF0 = 0 ;
		812	.equ PINF1 = 1 ;
		813	.equ PINF2 = 2 ;
		814	.equ PINF3 = 3 ;
		815	.equ PINF4 = 4 ;
		816	.equ PINF5 = 5 ;
		817	.equ PINF6 = 6 ;
		818	.equ PINF7 = 7 ;
		819
		820
		821	; *** PORTG **********************
		822	; PORTG - Data Register, Port G
		823	.equ PORTG0 = 0 ;
		824	.equ PG0 = 0 ; For compatibility
		825	.equ PORTG1 = 1 ;
		826	.equ PG1 = 1 ; For compatibility
		827	.equ PORTG2 = 2 ;
		828	.equ PG2 = 2 ; For compatibility
		829	.equ PORTG3 = 3 ;
		830	.equ PG3 = 3 ; For compatibility
		831	.equ PORTG4 = 4 ;
		832	.equ PG4 = 4 ; For compatibility
		833
		834	; DDRG - Data Direction Register, Port G
		835	.equ DDG0 = 0 ;
		836	.equ DDG1 = 1 ;
		837	.equ DDG2 = 2 ;
		838	.equ DDG3 = 3 ;
		839	.equ DDG4 = 4 ;
		840
		841	; PING - Input Pins, Port G
		842	.equ PING0 = 0 ;
		843	.equ PING1 = 1 ;
		844	.equ PING2 = 2 ;
		845	.equ PING3 = 3 ;
		846	.equ PING4 = 4 ;
		847
		848
		849	; *** TIMER_COUNTER_0 ************
		850	; TCCR0 - Timer/Counter Control Register
		851	.equ CS00 = 0 ; Clock Select 0
		852	.equ CS01 = 1 ; Clock Select 1
		853	.equ CS02 = 2 ; Clock Select 2
		854	.equ WGM01 = 3 ; Waveform Generation Mode 1
		855	.equ CTC0 = WGM01 ; For compatibility
		856	.equ COM00 = 4 ; Compare match Output Mode 0
		857	.equ COM01 = 5 ; Compare Match Output Mode 1
		858	.equ WGM00 = 6 ; Waveform Generation Mode 0
		859	.equ PWM0 = WGM00 ; For compatibility
		860	.equ FOC0 = 7 ; Force Output Compare
		861
		862	; TCNT0 - Timer/Counter Register
		863	.equ TCNT0_0 = 0 ;
		864	.equ TCNT0_1 = 1 ;
		865	.equ TCNT0_2 = 2 ;
		866	.equ TCNT0_3 = 3 ;
		867	.equ TCNT0_4 = 4 ;
		868	.equ TCNT0_5 = 5 ;
		869	.equ TCNT0_6 = 6 ;
		870	.equ TCNT0_7 = 7 ;
		871
		872	; OCR0 - Output Compare Register
		873	.equ OCR0_0 = 0 ;
		874	.equ OCR0_1 = 1 ;
		875	.equ OCR0_2 = 2 ;
		876	.equ OCR0_3 = 3 ;
		877	.equ OCR0_4 = 4 ;
		878	.equ OCR0_5 = 5 ;
		879	.equ OCR0_6 = 6 ;
		880	.equ OCR0_7 = 7 ;
		881
		882	; ASSR - Asynchronus Status Register
		883	.equ TCR0UB = 0 ; Timer/Counter Control Register 0 Update Busy
		884	.equ OCR0UB = 1 ; Output Compare register 0 Busy
		885	.equ TCN0UB = 2 ; Timer/Counter0 Update Busy
		886	.equ AS0 = 3 ; Asynchronus Timer/Counter 0
		887
		888	; TIMSK - Timer/Counter Interrupt Mask Register
		889	.equ TOIE0 = 0 ; Timer/Counter0 Overflow Interrupt Enable
		890	.equ OCIE0 = 1 ; Timer/Counter0 Output Compare Match Interrupt register
		891
		892	; TIFR - Timer/Counter Interrupt Flag register
		893	.equ TOV0 = 0 ; Timer/Counter0 Overflow Flag
		894	.equ OCF0 = 1 ; Output Compare Flag 0
		895
		896	; SFIOR - Special Function IO Register
		897	;.equ PSR0 = 1 ; Prescaler Reset Timer/Counter0
		898	;.equ TSM = 7 ; Timer/Counter Synchronization Mode
		899
		900
		901	; *** TIMER_COUNTER_1 ************
		902	; TIMSK - Timer/Counter Interrupt Mask Register
		903	.equ TOIE1 = 2 ; Timer/Counter1 Overflow Interrupt Enable
		904	.equ OCIE1B = 3 ; Timer/Counter1 Output CompareB Match Interrupt Enable
		905	.equ OCIE1A = 4 ; Timer/Counter1 Output CompareA Match Interrupt Enable
		906	.equ TICIE1 = 5 ; Timer/Counter1 Input Capture Interrupt Enable
		907
		908	; ETIMSK - Extended Timer/Counter Interrupt Mask Register
		909	.equ OCIE1C = 0 ; Timer/Counter 1, Output Compare Match C Interrupt Enable
		910
		911	; TIFR - Timer/Counter Interrupt Flag register
		912	.equ TOV1 = 2 ; Timer/Counter1 Overflow Flag
		913	.equ OCF1B = 3 ; Output Compare Flag 1B
		914	.equ OCF1A = 4 ; Output Compare Flag 1A
		915	.equ ICF1 = 5 ; Input Capture Flag 1
		916
		917	; ETIFR - Extended Timer/Counter Interrupt Flag register
		918	.equ OCF1C = 0 ; Timer/Counter 1, Output Compare C Match Flag
		919
		920	; SFIOR - Special Function IO Register
		921	;.equ PSR321 = 0 ; Prescaler Reset, T/C3, T/C2, T/C1
		922	;.equ TSM = 7 ; Timer/Counter Synchronization Mode
		923
		924	; TCCR1A - Timer/Counter1 Control Register A
		925	.equ WGM10 = 0 ; Waveform Generation Mode Bit 0
		926	.equ PWM10 = WGM10 ; For compatibility
		927	.equ WGM11 = 1 ; Waveform Generation Mode Bit 1
		928	.equ PWM11 = WGM11 ; For compatibility
		929	.equ COM1C0 = 2 ; Compare Output Mode 1C, bit 0
		930	.equ COM1C1 = 3 ; Compare Output Mode 1C, bit 1
		931	.equ COM1B0 = 4 ; Compare Output Mode 1B, bit 0
		932	.equ COM1B1 = 5 ; Compare Output Mode 1B, bit 1
		933	.equ COM1A0 = 6 ; Compare Ouput Mode 1A, bit 0
		934	.equ COM1A1 = 7 ; Compare Output Mode 1A, bit 1
		935
		936	; TCCR1B - Timer/Counter1 Control Register B
		937	.equ CS10 = 0 ; Clock Select bit 0
		938	.equ CS11 = 1 ; Clock Select 1 bit 1
		939	.equ CS12 = 2 ; Clock Select1 bit 2
		940	.equ WGM12 = 3 ; Waveform Generation Mode
		941	.equ CTC10 = WGM12 ; For compatibility
		942	.equ WGM13 = 4 ; Waveform Generation Mode
		943	.equ CTC11 = WGM13 ; For compatibility
		944	.equ ICES1 = 6 ; Input Capture 1 Edge Select
		945	.equ ICNC1 = 7 ; Input Capture 1 Noise Canceler
		946
		947	; TCCR1C - Timer/Counter1 Control Register C
		948	.equ FOC1C = 5 ; Force Output Compare for channel C
		949	.equ FOC1B = 6 ; Force Output Compare for channel B
		950	.equ FOC1A = 7 ; Force Output Compare for channel A
		951
		952
		953	; *** TIMER_COUNTER_2 ************
		954	; TCCR2 - Timer/Counter Control Register
		955	.equ CS20 = 0 ; Clock Select
		956	.equ CS21 = 1 ; Clock Select
		957	.equ CS22 = 2 ; Clock Select
		958	.equ WGM21 = 3 ; Waveform Generation Mode
		959	.equ CTC2 = WGM21 ; For compatibility
		960	.equ COM20 = 4 ; Compare Match Output Mode
		961	.equ COM21 = 5 ; Compare Match Output Mode
		962	.equ WGM20 = 6 ; Wafeform Generation Mode
		963	.equ PWM2 = WGM20 ; For compatibility
		964	.equ FOC2 = 7 ; Force Output Compare
		965
		966	; TCNT2 - Timer/Counter Register
		967	.equ TCNT2_0 = 0 ; Timer/Counter Register Bit 0
		968	.equ TCNT2_1 = 1 ; Timer/Counter Register Bit 1
		969	.equ TCNT2_2 = 2 ; Timer/Counter Register Bit 2
		970	.equ TCNT2_3 = 3 ; Timer/Counter Register Bit 3
		971	.equ TCNT2_4 = 4 ; Timer/Counter Register Bit 4
		972	.equ TCNT2_5 = 5 ; Timer/Counter Register Bit 5
		973	.equ TCNT2_6 = 6 ; Timer/Counter Register Bit 6
		974	.equ TCNT2_7 = 7 ; Timer/Counter Register Bit 7
		975
		976	; OCR2 - Output Compare Register
		977	.equ OCR2_0 = 0 ; Output Compare Register Bit 0
		978	.equ OCR2_1 = 1 ; Output Compare Register Bit 1
		979	.equ OCR2_2 = 2 ; Output Compare Register Bit 2
		980	.equ OCR2_3 = 3 ; Output Compare Register Bit 3
		981	.equ OCR2_4 = 4 ; Output Compare Register Bit 4
		982	.equ OCR2_5 = 5 ; Output Compare Register Bit 5
		983	.equ OCR2_6 = 6 ; Output Compare Register Bit 6
		984	.equ OCR2_7 = 7 ; Output Compare Register Bit 7
		985
		986	; TIMSK -
		987	.equ TOIE2 = 6 ;
		988	.equ OCIE2 = 7 ;
		989
		990	; TIFR - Timer/Counter Interrupt Flag Register
		991	.equ TOV2 = 6 ; Timer/Counter2 Overflow Flag
		992	.equ OCF2 = 7 ; Output Compare Flag 2
		993
		994
		995	; *** TIMER_COUNTER_3 ************
		996	; ETIMSK - Extended Timer/Counter Interrupt Mask Register
		997	.equ OCIE3C = 1 ; Timer/Counter3, Output Compare Match Interrupt Enable
		998	.equ TOIE3 = 2 ; Timer/Counter3 Overflow Interrupt Enable
		999	.equ OCIE3B = 3 ; Timer/Counter3 Output CompareB Match Interrupt Enable
		1000	.equ OCIE3A = 4 ; Timer/Counter3 Output CompareA Match Interrupt Enable
		1001	.equ TICIE3 = 5 ; Timer/Counter3 Input Capture Interrupt Enable
		1002
		1003	; ETIFR - Extended Timer/Counter Interrupt Flag register
		1004	.equ OCF3C = 1 ; Timer/Counter3 Output Compare C Match Flag
		1005	.equ TOV3 = 2 ; Timer/Counter3 Overflow Flag
		1006	.equ OCF3B = 3 ; Output Compare Flag 1B
		1007	.equ OCF3A = 4 ; Output Compare Flag 1A
		1008	.equ ICF3 = 5 ; Input Capture Flag 1
		1009
		1010	; SFIOR - Special Function IO Register
		1011	;.equ PSR321 = 0 ; Prescaler Reset, T/C3, T/C2, T/C1
		1012	;.equ PSR1 = PSR321 ; For compatibility
		1013	;.equ PSR2 = PSR321 ; For compatibility
		1014	;.equ TSM = 7 ; Timer/Counter Synchronization Mode
		1015
		1016	; TCCR3A - Timer/Counter3 Control Register A
		1017	.equ WGM30 = 0 ; Waveform Generation Mode Bit 0
		1018	.equ PWM30 = WGM30 ; For compatibility
		1019	.equ WGM31 = 1 ; Waveform Generation Mode Bit 1
		1020	.equ PWM31 = WGM31 ; For compatibility
		1021	.equ COM3C0 = 2 ; Compare Output Mode 3C, bit 0
		1022	.equ COM3C1 = 3 ; Compare Output Mode 3C, bit 1
		1023	.equ COM3B0 = 4 ; Compare Output Mode 3B, bit 0
		1024	.equ COM3B1 = 5 ; Compare Output Mode 3B, bit 1
		1025	.equ COM3A0 = 6 ; Comparet Ouput Mode 3A, bit 0
		1026	.equ COM3A1 = 7 ; Compare Output Mode 3A, bit 1
		1027
		1028	; TCCR3B - Timer/Counter3 Control Register B
		1029	.equ CS30 = 0 ; Clock Select 3 bit 0
		1030	.equ CS31 = 1 ; Clock Select 3 bit 1
		1031	.equ CS32 = 2 ; Clock Select3 bit 2
		1032	.equ WGM32 = 3 ; Waveform Generation Mode
		1033	.equ CTC30 = WGM32 ; For compatibility
		1034	.equ WGM33 = 4 ; Waveform Generation Mode
		1035	.equ CTC31 = WGM33 ; For compatibility
		1036	.equ ICES3 = 6 ; Input Capture 3 Edge Select
		1037	.equ ICNC3 = 7 ; Input Capture 3 Noise Canceler
		1038
		1039	; TCCR3C - Timer/Counter3 Control Register C
		1040	.equ FOC3C = 5 ; Force Output Compare for channel C
		1041	.equ FOC3B = 6 ; Force Output Compare for channel B
		1042	.equ FOC3A = 7 ; Force Output Compare for channel A
		1043
		1044
		1045	; *** WATCHDOG *******************
		1046	; WDTCR - Watchdog Timer Control Register
		1047	.equ WDTCSR = WDTCR ; For compatibility
		1048	.equ WDP0 = 0 ; Watch Dog Timer Prescaler bit 0
		1049	.equ WDP1 = 1 ; Watch Dog Timer Prescaler bit 1
		1050	.equ WDP2 = 2 ; Watch Dog Timer Prescaler bit 2
		1051	.equ WDE = 3 ; Watch Dog Enable
		1052	.equ WDCE = 4 ; Watchdog Change Enable
		1053	.equ WDTOE = WDCE ; For compatibility
		1054
		1055
		1056
		1057	; *** LOCKSBITS ******************************************************
		1058	.equ LB1 = 0 ; Lock bit
		1059	.equ LB2 = 1 ; Lock bit
		1060	.equ BLB01 = 2 ; Boot Lock bit
		1061	.equ BLB02 = 3 ; Boot Lock bit
		1062	.equ BLB11 = 4 ; Boot lock bit
		1063	.equ BLB12 = 5 ; Boot lock bit
		1064
		1065
		1066	; *** FUSES **********************************************************
		1067	; LOW fuse bits
		1068	.equ CKSEL0 = 0 ; Select Clock Source
		1069	.equ CKSEL1 = 1 ; Select Clock Source
		1070	.equ CKSEL2 = 2 ; Select Clock Source
		1071	.equ CKSEL3 = 3 ; Select Clock Source
		1072	.equ SUT0 = 4 ; Select start-up time
		1073	.equ SUT1 = 5 ; Select start-up time
		1074	.equ BODEN = 6 ; Brown out detector enable
		1075	.equ BODLEVEL = 7 ; Brown out detector trigger level
		1076
		1077	; HIGH fuse bits
		1078	.equ BOOTRST = 0 ; Select Reset Vector
		1079	.equ BOOTSZ0 = 1 ; Select Boot Size
		1080	.equ BOOTSZ1 = 2 ; Select Boot Size
		1081	.equ EESAVE = 3 ; EEPROM memory is preserved through chip erase
		1082	.equ CKOPT = 4 ; Oscillator Options
		1083	.equ SPIEN = 5 ; Enable Serial programming and Data Downloading
		1084	.equ JTAGEN = 6 ; Enable JTAG
		1085	.equ OCDEN = 7 ; Enable OCD
		1086
		1087	; EXTENDED fuse bits
		1088	.equ WDTON = 0 ; Watchdog timer always on
		1089	.equ M103C = 1 ; ATmega103 compatibility mode
		1090
		1091
		1092
		1093	; *** CPU REGISTER DEFINITIONS ***************************************
		1094	.def XH = r27
		1095	.def XL = r26
		1096	.def YH = r29
		1097	.def YL = r28
		1098	.def ZH = r31
		1099	.def ZL = r30
		1100
		1101
		1102
		1103	; *** DATA MEMORY DECLARATIONS ***************************************
		1104	.equ FLASHEND = 0xffff ; Note: Word address
		1105	.equ IOEND = 0x00ff
		1106	.equ SRAM_START = 0x0100
		1107	.equ SRAM_SIZE = 4096
		1108	.equ RAMEND = 0x10ff
		1109	.equ XRAMEND = 0xffff
		1110	.equ E2END = 0x0fff
		1111	.equ EEPROMEND = 0x0fff
		1112	.equ EEADRBITS = 12
		1113	#pragma AVRPART MEMORY PROG_FLASH 131072
		1114	#pragma AVRPART MEMORY EEPROM 4096
		1115	#pragma AVRPART MEMORY INT_SRAM SIZE 4096
		1116	#pragma AVRPART MEMORY INT_SRAM START_ADDR 0x100
		1117
		1118
		1119
		1120	; *** BOOTLOADER DECLARATIONS ****************************************
		1121	.equ NRWW_START_ADDR = 0xf000
		1122	.equ NRWW_STOP_ADDR = 0xffff
		1123	.equ RWW_START_ADDR = 0x0
		1124	.equ RWW_STOP_ADDR = 0xefff
		1125	.equ PAGESIZE = 128
		1126	.equ FIRSTBOOTSTART = 0xfe00
		1127	.equ SECONDBOOTSTART = 0xfc00
		1128	.equ THIRDBOOTSTART = 0xf800
		1129	.equ FOURTHBOOTSTART = 0xf000
		1130	.equ SMALLBOOTSTART = FIRSTBOOTSTART
		1131	.equ LARGEBOOTSTART = FOURTHBOOTSTART
		1132
		1133
		1134
		1135	; *** INTERRUPT VECTORS **********************************************
		1136	.equ INT0addr = 0x0002 ; External Interrupt Request 0
		1137	.equ INT1addr = 0x0004 ; External Interrupt Request 1
		1138	.equ INT2addr = 0x0006 ; External Interrupt Request 2
		1139	.equ INT3addr = 0x0008 ; External Interrupt Request 3
		1140	.equ INT4addr = 0x000a ; External Interrupt Request 4
		1141	.equ INT5addr = 0x000c ; External Interrupt Request 5
		1142	.equ INT6addr = 0x000e ; External Interrupt Request 6
		1143	.equ INT7addr = 0x0010 ; External Interrupt Request 7
		1144	.equ OC2addr = 0x0012 ; Timer/Counter2 Compare Match
		1145	.equ OVF2addr = 0x0014 ; Timer/Counter2 Overflow
		1146	.equ ICP1addr = 0x0016 ; Timer/Counter1 Capture Event
		1147	.equ OC1Aaddr = 0x0018 ; Timer/Counter1 Compare Match A
		1148	.equ OC1Baddr = 0x001a ; Timer/Counter Compare Match B
		1149	.equ OVF1addr = 0x001c ; Timer/Counter1 Overflow
		1150	.equ OC0addr = 0x001e ; Timer/Counter0 Compare Match
		1151	.equ OVF0addr = 0x0020 ; Timer/Counter0 Overflow
		1152	.equ SPIaddr = 0x0022 ; SPI Serial Transfer Complete
		1153	.equ URXC0addr = 0x0024 ; USART0, Rx Complete
		1154	.equ UDRE0addr = 0x0026 ; USART0 Data Register Empty
		1155	.equ UTXC0addr = 0x0028 ; USART0, Tx Complete
		1156	.equ ADCCaddr = 0x002a ; ADC Conversion Complete
		1157	.equ ERDYaddr = 0x002c ; EEPROM Ready
		1158	.equ ACIaddr = 0x002e ; Analog Comparator
		1159	.equ OC1Caddr = 0x0030 ; Timer/Counter1 Compare Match C
		1160	.equ ICP3addr = 0x0032 ; Timer/Counter3 Capture Event
		1161	.equ OC3Aaddr = 0x0034 ; Timer/Counter3 Compare Match A
		1162	.equ OC3Baddr = 0x0036 ; Timer/Counter3 Compare Match B
		1163	.equ OC3Caddr = 0x0038 ; Timer/Counter3 Compare Match C
		1164	.equ OVF3addr = 0x003a ; Timer/Counter3 Overflow
		1165	.equ URXC1addr = 0x003c ; USART1, Rx Complete
		1166	.equ UDRE1addr = 0x003e ; USART1, Data Register Empty
		1167	.equ UTXC1addr = 0x0040 ; USART1, Tx Complete
		1168	.equ TWIaddr = 0x0042 ; 2-wire Serial Interface
		1169	.equ SPMRaddr = 0x0044 ; Store Program Memory Read
		1170
		1171	.equ INT_VECTORS_SIZE = 70 ; size in words
		1172
		1173	#endif /* _M128DEF_INC_ */
		1174
		1175	; *** END OF FILE ****************************************************

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(root)/contrib/toolchain/avra/includes/m128def.inc – Rev 6400