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| Rev | Author | Line No. | Line |
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| 6146 | serge | 1 | /* |
| 2 | * Copyright 2000-2013 Intel Corporation All Rights Reserved |
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| 3 | * |
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| 4 | * Licensed under the Apache License, Version 2.0 (the "License"); |
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| 5 | * you may not use this file except in compliance with the License. |
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| 6 | * You may obtain a copy of the License at |
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| 7 | * |
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| 8 | * http://www.apache.org/licenses/LICENSE-2.0 |
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| 9 | * |
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| 10 | * Unless required by applicable law or agreed to in writing, software |
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| 11 | * distributed under the License is distributed on an "AS IS" BASIS, |
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| 12 | * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. |
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| 13 | * See the License for the specific language governing permissions and |
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| 14 | * limitations under the License. |
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| 15 | * |
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| 16 | * Authors: Zhao Yakui |
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| 17 | */ |
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| 18 | // 7 // Total instruction count |
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| 19 | // 1 // Total kernel count |
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| 20 | |||
| 21 | |||
| 22 | |||
| 23 | // Module name: common.inc |
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| 24 | // |
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| 25 | // Common header file for all Video-Processing kernels |
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| 26 | // |
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| 27 | |||
| 28 | .default_execution_size (16) |
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| 29 | .default_register_type :ub |
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| 30 | |||
| 31 | .reg_count_total 128 |
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| 32 | .reg_count_payload 7 |
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| 33 | |||
| 34 | //========== Common constants ========== |
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| 35 | |||
| 36 | |||
| 37 | //========== Macros ========== |
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| 38 | |||
| 39 | |||
| 40 | //Fast Jump, For more details see "Set_Layer_N.asm" |
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| 41 | |||
| 42 | |||
| 43 | //========== Defines ==================== |
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| 44 | |||
| 45 | //========== Static Parameters (Common To All) ========== |
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| 46 | //r1 |
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| 47 | |||
| 48 | |||
| 49 | //r2 |
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| 50 | |||
| 51 | // e.g. byte0 byte1 byte2 |
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| 52 | // YUYV 0 1 3 |
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| 53 | // YVYU 0 3 1 |
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| 54 | |||
| 55 | //Color Pipe (IECP) parameters |
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| 56 | |||
| 57 | |||
| 58 | //ByteCopy |
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| 59 | |||
| 60 | |||
| 61 | //r4 |
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| 62 | |||
| 63 | // e.g. byte0 byte1 byte2 |
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| 64 | // YUYV 0 1 3 |
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| 65 | // YVYU 0 3 1 |
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| 66 | |||
| 67 | |||
| 68 | //========== Inline parameters (Common To All) =========== |
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| 69 | |||
| 70 | |||
| 71 | //============== Binding Index Table=========== |
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| 72 | //Common between DNDI and DNUV |
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| 73 | |||
| 74 | |||
| 75 | //================= Common Message Descriptor ===== |
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| 76 | // Message descriptor for thread spawning |
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| 77 | // Message Descriptors |
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| 78 | // = 000 0001 (min message len 1 ) 0,0000 (resp len 0 -add later) |
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| 79 | // 0000,0000,0000 |
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| 80 | // 0001(Spawn a root thread),0001 (Root thread spawn thread) |
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| 81 | // = 0x02000011 |
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| 82 | // Thread Spawner Message Descriptor |
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| 83 | |||
| 84 | |||
| 85 | // Message descriptor for atomic operation add |
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| 86 | // Message Descriptors |
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| 87 | // = 000 0110 (min message len 6 ) 0,0000 (resp len 0 -add later) |
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| 88 | // 1(header present)001,10(typed atomic operation)0(return enabled)0(slot group, low 8 bits),0111 (AOP_Add) |
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| 89 | // 0000,0000 (Binding table index, added later) |
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| 90 | // = 0x02000011 |
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| 91 | |||
| 92 | // Atomic Operation Add Message Descriptor |
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| 93 | |||
| 94 | |||
| 95 | // Message descriptor for dataport media write |
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| 96 | // Message Descriptors |
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| 97 | // = 000 0001 (min message len 1 - add later) 00000 (resp len 0) |
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| 98 | // 1 (header present 1) 0 1010 (media block write) 000000 |
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| 99 | // 00000000 (binding table index - set later) |
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| 100 | // = 0x020A8000 |
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| 101 | |||
| 102 | |||
| 103 | // Message Length defines |
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| 104 | |||
| 105 | |||
| 106 | // Response Length defines |
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| 107 | |||
| 108 | |||
| 109 | // Block Width and Height Size defines |
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| 110 | |||
| 111 | |||
| 112 | // Extended Message Descriptors |
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| 113 | |||
| 114 | |||
| 115 | // Common message descriptors: |
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| 116 | |||
| 117 | |||
| 118 | //===================== Math Function Control =================================== |
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| 119 | |||
| 120 | |||
| 121 | //============ Message Registers =============== |
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| 122 | // buf4 starts from r28 |
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| 123 | |||
| 124 | |||
| 125 | //#define mMSGHDR_EOT r43 // Dummy Message Register for EOT |
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| 126 | |||
| 127 | |||
| 128 | .declare mubMSGPAYLOAD Base=r30 ElementSize=1 SrcRegion=<16;16,1> Type=ub |
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| 129 | .declare muwMSGPAYLOAD Base=r30 ElementSize=2 SrcRegion=<16;16,1> Type=uw |
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| 130 | .declare mudMSGPAYLOAD Base=r30 ElementSize=4 SrcRegion=<8;8,1> Type=ud |
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| 131 | .declare mfMSGPAYLOAD Base=r30 ElementSize=4 SrcRegion=<8;8,1> Type=f |
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| 132 | |||
| 133 | //=================== End of thread instruction =========================== |
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| 134 | |||
| 135 | |||
| 136 | //=====================Pointers Used===================================== |
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| 137 | |||
| 138 | |||
| 139 | //======================================================================= |
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| 140 | |||
| 141 | |||
| 142 | //r11-r17 |
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| 143 | // Define temp space for any usages |
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| 144 | |||
| 145 | |||
| 146 | // Common Buffers |
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| 147 | |||
| 148 | |||
| 149 | // temp space for rotation |
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| 150 | |||
| 151 | .declare fROBUF Base=r11.0 ElementSize=4 SrcRegion=<8;8,1> DstRegion=<1> Type=f |
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| 152 | |||
| 153 | .declare udROBUF Base=r11.0 ElementSize=4 SrcRegion=<8;8,1> DstRegion=<1> Type=ud |
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| 154 | |||
| 155 | .declare uwROBUF Base=r11.0 ElementSize=2 SrcRegion=<16;16,1> DstRegion=<1> Type=uw |
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| 156 | |||
| 157 | .declare ubROBUF Base=r11.0 ElementSize=1 SrcRegion=<16;16,1> DstRegion=<1> Type=ub |
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| 158 | |||
| 159 | .declare ub4ROBUF Base=r11.0 ElementSize=1 SrcRegion=<32;8,4> DstRegion=<4> Type=ub |
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| 160 | |||
| 161 | |||
| 162 | // End of common.inc |
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| 163 | |||
| 164 | |||
| 165 | //Module Name: Set_AVS_Buf_0123_BGRA.asm |
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| 166 | |||
| 167 | |||
| 168 | |||
| 169 | //Module Name: Set_Buf_0123_BGRA |
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| 170 | |||
| 171 | |||
| 172 | |||
| 173 | |||
| 174 | // Description: Includes all definitions explicit to Fast Composite. |
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| 175 | |||
| 176 | |||
| 177 | |||
| 178 | |||
| 179 | // End of common.inc |
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| 180 | |||
| 181 | |||
| 182 | //========== GRF partition ========== |
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| 183 | // r0 header : r0 (1 GRF) |
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| 184 | // Static parameters : r1 - r6 (6 GRFS) |
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| 185 | // Inline parameters : r7 - r8 (2 GRFs) |
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| 186 | // MSGSRC : r27 (1 GRF) |
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| 187 | //=================================== |
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| 188 | |||
| 189 | //Interface: |
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| 190 | //========== Static Parameters (Explicit To Fast Composite) ========== |
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| 191 | //r1 |
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| 192 | //CSC Set 0 |
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| 193 | |||
| 194 | |||
| 195 | .declare udCSC_CURBE Base=r1.0 ElementSize=4 Type=ud |
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| 196 | |||
| 197 | //Constant alpha |
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| 198 | |||
| 199 | |||
| 200 | //r2 |
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| 201 | |||
| 202 | |||
| 203 | // Gen7 AVS WA |
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| 204 | |||
| 205 | |||
| 206 | // WiDi Definitions |
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| 207 | |||
| 208 | |||
| 209 | //Colorfill |
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| 210 | |||
| 211 | |||
| 212 | // 0: 0-degree, 1: 90, 2: 180, 3: 270-degree, clockwise. |
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| 213 | |||
| 214 | .declare ubCOLOR_PIXEL_VAL Base=r2.20 ElementSize=1 SrcRegion=<0;1,0> DstRegion=<1> Type=ub |
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| 215 | |||
| 216 | //r3 |
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| 217 | //Normalised Ratio of Horizontal step size with main video for all layers |
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| 218 | |||
| 219 | |||
| 220 | //Normalised Ratio of Horizontal step size with main video for all layers becomes |
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| 221 | //Normalised Horizontal step size for all layers in VP_Setup.asm |
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| 222 | |||
| 223 | |||
| 224 | //r4 |
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| 225 | //Normalised Vertical step size for all layers |
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| 226 | |||
| 227 | |||
| 228 | //r5 |
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| 229 | //Normalised Vertical Frame Origin for all layers |
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| 230 | |||
| 231 | |||
| 232 | //r6 |
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| 233 | //Normalised Horizontal Frame Origin for all layers |
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| 234 | |||
| 235 | |||
| 236 | //========== Inline Parameters (Explicit To Fast Composite) ========== |
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| 237 | |||
| 238 | |||
| 239 | //Main video Step X |
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| 240 | |||
| 241 | |||
| 242 | //====================== Binding table (Explicit To Fast Composite)========================================= |
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| 243 | |||
| 244 | |||
| 245 | //Used by Interlaced Scaling Kernels |
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| 246 | |||
| 247 | |||
| 248 | //========== Sampler State Table Index (Explicit To Fast Composite)========== |
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| 249 | //Sampler Index for AVS/IEF messages |
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| 250 | |||
| 251 | |||
| 252 | //Sampler Index for SIMD16 sampler messages |
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| 253 | |||
| 254 | |||
| 255 | //============================================================================= |
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| 256 | |||
| 257 | .declare fBUFFER_0 Base=r64.0 ElementSize=4 SrcRegion=<8;8,1> DstRegion=<1> Type=f |
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| 258 | .declare fBUFFER_1 Base=r80.0 ElementSize=4 SrcRegion=<8;8,1> DstRegion=<1> Type=f |
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| 259 | .declare fBUFFER_2 Base=r96.0 ElementSize=4 SrcRegion=<8;8,1> DstRegion=<1> Type=f |
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| 260 | .declare fBUFFER_3 Base=r112.0 ElementSize=4 SrcRegion=<8;8,1> DstRegion=<1> Type=f |
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| 261 | .declare fBUFFER_4 Base=r28.0 ElementSize=4 SrcRegion=<8;8,1> DstRegion=<1> Type=f |
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| 262 | .declare fBUFFER_5 Base=r46.0 ElementSize=4 SrcRegion=<8;8,1> DstRegion=<1> Type=f |
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| 263 | |||
| 264 | .declare udBUFFER_0 Base=r64.0 ElementSize=4 SrcRegion=<8;8,1> DstRegion=<1> Type=ud |
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| 265 | .declare udBUFFER_1 Base=r80.0 ElementSize=4 SrcRegion=<8;8,1> DstRegion=<1> Type=ud |
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| 266 | .declare udBUFFER_2 Base=r96.0 ElementSize=4 SrcRegion=<8;8,1> DstRegion=<1> Type=ud |
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| 267 | .declare udBUFFER_3 Base=r112.0 ElementSize=4 SrcRegion=<8;8,1> DstRegion=<1> Type=ud |
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| 268 | .declare udBUFFER_4 Base=r28.0 ElementSize=4 SrcRegion=<8;8,1> DstRegion=<1> Type=ud |
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| 269 | .declare udBUFFER_5 Base=r46.0 ElementSize=4 SrcRegion=<8;8,1> DstRegion=<1> Type=ud |
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| 270 | |||
| 271 | .declare uwBUFFER_0 Base=r64.0 ElementSize=2 SrcRegion=<16;16,1> DstRegion=<1> Type=uw |
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| 272 | .declare uwBUFFER_1 Base=r80.0 ElementSize=2 SrcRegion=<16;16,1> DstRegion=<1> Type=uw |
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| 273 | .declare uwBUFFER_2 Base=r96.0 ElementSize=2 SrcRegion=<16;16,1> DstRegion=<1> Type=uw |
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| 274 | .declare uwBUFFER_3 Base=r112.0 ElementSize=2 SrcRegion=<16;16,1> DstRegion=<1> Type=uw |
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| 275 | .declare uwBUFFER_4 Base=r28.0 ElementSize=2 SrcRegion=<16;16,1> DstRegion=<1> Type=uw |
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| 276 | .declare uwBUFFER_5 Base=r46.0 ElementSize=2 SrcRegion=<16;16,1> DstRegion=<1> Type=uw |
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| 277 | |||
| 278 | .declare ubBUFFER_0 Base=r64.0 ElementSize=1 SrcRegion=<16;16,1> DstRegion=<1> Type=ub |
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| 279 | .declare ubBUFFER_1 Base=r80.0 ElementSize=1 SrcRegion=<16;16,1> DstRegion=<1> Type=ub |
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| 280 | .declare ubBUFFER_2 Base=r96.0 ElementSize=1 SrcRegion=<16;16,1> DstRegion=<1> Type=ub |
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| 281 | .declare ubBUFFER_3 Base=r112.0 ElementSize=1 SrcRegion=<16;16,1> DstRegion=<1> Type=ub |
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| 282 | .declare ubBUFFER_4 Base=r28.0 ElementSize=1 SrcRegion=<16;16,1> DstRegion=<1> Type=ub |
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| 283 | .declare ubBUFFER_5 Base=r46.0 ElementSize=1 SrcRegion=<16;16,1> DstRegion=<1> Type=ub |
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| 284 | |||
| 285 | .declare ub4BUFFER_0 Base=r64.0 ElementSize=1 SrcRegion=<32;8,4> DstRegion=<4> Type=ub |
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| 286 | .declare ub4BUFFER_1 Base=r80.0 ElementSize=1 SrcRegion=<32;8,4> DstRegion=<4> Type=ub |
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| 287 | .declare ub4BUFFER_2 Base=r96.0 ElementSize=1 SrcRegion=<32;8,4> DstRegion=<4> Type=ub |
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| 288 | .declare ub4BUFFER_3 Base=r112.0 ElementSize=1 SrcRegion=<32;8,4> DstRegion=<4> Type=ub |
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| 289 | .declare ub4BUFFER_4 Base=r28.0 ElementSize=1 SrcRegion=<32;8,4> DstRegion=<4> Type=ub |
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| 290 | .declare ub4BUFFER_5 Base=r46.0 ElementSize=1 SrcRegion=<32;8,4> DstRegion=<4> Type=ub |
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| 291 | |||
| 292 | //Pointer to mask reg |
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| 293 | |||
| 294 | |||
| 295 | //r18 |
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| 296 | |||
| 297 | |||
| 298 | //Always keep Cannel Pointers and Offsets in same GRF, so that we can use |
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| 299 | // NODDCLR, NODDCHK flags. -rT |
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| 300 | |||
| 301 | |||
| 302 | .declare udCSC_COEFF_0 Base=r18.0 ElementSize=4 Type=ud // 1 GRF |
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| 303 | |||
| 304 | //r19 |
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| 305 | |||
| 306 | |||
| 307 | .declare udCSC_COEFF_1 Base=r19.0 ElementSize=4 Type=ud // 1 GRF |
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| 308 | |||
| 309 | |||
| 310 | //r20 |
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| 311 | |||
| 312 | .declare uwALPHA_MASK_REG_TEMP Base=r20.0 ElementSize=2 SrcRegion=<16;16,1> Type=uw // 1 GRF |
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| 313 | |||
| 314 | //r21 |
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| 315 | |||
| 316 | .declare uwALPHA_MASK_REG Base=r21.0 ElementSize=2 SrcRegion=<16;16,1> Type=uw // 1 GRF |
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| 317 | |||
| 318 | //r22 |
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| 319 | |||
| 320 | |||
| 321 | //Always keep Cannel Pointers and Offsets in same GRF, so that we can use |
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| 322 | // NODDCLR, NODDCHK flags. -rT |
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| 323 | |||
| 324 | |||
| 325 | //Keep fORIGIN_X_NLAS, fY_OFFSET_2ND_BLOCK, fSTEP_X_NLAS, pMSGDSC_COPY, ubCONST_ALPHA_COPY as |
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| 326 | //sub registers of same GRF to enable using NODDCLR NODDCHK. -rT |
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| 327 | |||
| 328 | //r23 |
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| 329 | |||
| 330 | |||
| 331 | //Lumakey |
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| 332 | |||
| 333 | |||
| 334 | //r24 |
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| 335 | |||
| 336 | |||
| 337 | //r25 |
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| 338 | |||
| 339 | |||
| 340 | //r26 |
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| 341 | |||
| 342 | |||
| 343 | //defines to generate LABELS during compile time. |
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| 344 | |||
| 345 | |||
| 346 | //AVS LAYOUT:(UUYYVVAA) |
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| 347 | //AVS RGBX LAYOUT (RRGGBBAA) |
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| 348 | //Assign buffer channel order for Buffer 0123 in the order AUYV a0.3>A, a0.2>U, a0.1>Y, a0.0>V |
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| 349 | // V = 8, Y= 0, U = 4, A = 12. |
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| 350 | // And a0.x is used as indirect-register for RGBX. R=a0.1, G=a0.2, B=a0.0 |
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| 351 | // B = 8, R= 0, G = 4, A = 12 |
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| 352 | mov (4) acc0.0<1>:w 0x6EA2:v |
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| 353 | add (4) acc0.0<1>:w acc0<4;4,1>:w 70:uw |
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| 354 | shl (4) r22.0<1>:w acc0<4;4,1>:w 5:uw |
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| 355 | |||
| 356 | //OPT: wAVS_SU_SHUFFLE_PTR_0 and udAVS_SU_SHUFFLE_OFF_0 are sub-regs of same GRF. -rT |
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| 357 | |||
| 358 | //SU LAYOUT:(VYUAVYUA) |
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| 359 | //V = 4, Y = 2, U = 0, A = 6 |
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| 360 | //B = 4, G = 2, R = 0, A = 6 |
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| 361 | mov (4) acc0.0<1>:w 0x6204:v |
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| 362 | add (4) acc0.0<1>:w acc0<4;4,1>:w 64:uw |
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| 363 | shl (4) r18.0<1>:w acc0<4;4,1>:w 5:uw { NoDDClr } //Convert to BYTE address. |
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| 364 | |||
| 365 | //OFFSET: |
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| 366 | mov (1) r18.4<1>:ud 0x1000100:ud { NoDDChk } |
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| 367 |