Details | Last modification | View Log | RSS feed
| Rev | Author | Line No. | Line |
|---|---|---|---|
| 5361 | serge | 1 | /* |
| 2 | * Copyright © 2012 Intel Corporation |
||
| 3 | * |
||
| 4 | * Permission is hereby granted, free of charge, to any person obtaining a |
||
| 5 | * copy of this software and associated documentation files (the "Software"), |
||
| 6 | * to deal in the Software without restriction, including without limitation |
||
| 7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
||
| 8 | * and/or sell copies of the Software, and to permit persons to whom the |
||
| 9 | * Software is furnished to do so, subject to the following conditions: |
||
| 10 | * |
||
| 11 | * The above copyright notice and this permission notice (including the next |
||
| 12 | * paragraph) shall be included in all copies or substantial portions of the |
||
| 13 | * Software. |
||
| 14 | * |
||
| 15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
||
| 16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
||
| 17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
||
| 18 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER |
||
| 19 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING |
||
| 20 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS |
||
| 21 | * IN THE SOFTWARE. |
||
| 22 | * |
||
| 23 | * Authors: |
||
| 24 | * Xiang Haihao |
||
| 25 | */ |
||
| 26 | |||
| 27 | define(`BIND_IDX_VME_OUTPUT', `0') |
||
| 28 | define(`BIND_IDX_MFC_SLICE_HEADER', `1') |
||
| 29 | define(`BIND_IDX_MFC_BATCHBUFFER', `2') |
||
| 30 | |||
| 31 | define(`INTRAMBFLAG_MASK', `0x00002000') |
||
| 32 | |||
| 33 | #ifdef DEV_SNB |
||
| 34 | |||
| 35 | define(`OB_CACHE_TYPE', `5') |
||
| 36 | |||
| 37 | #else |
||
| 38 | |||
| 39 | define(`OB_CACHE_TYPE', `10') |
||
| 40 | |||
| 41 | #endif |
||
| 42 | |||
| 43 | define(`OB_READ', `0') |
||
| 44 | define(`OB_WRITE', `8') |
||
| 45 | |||
| 46 | define(`OB_CONTROL_0', `0') /* 1 OWord, low 128 bits */ |
||
| 47 | define(`OB_CONTROL_1', `1') /* 1 OWord, high 128 bits */ |
||
| 48 | define(`OB_CONTROL_2', `2') /* 2 OWords */ |
||
| 49 | define(`OB_CONTROL_3', `3') /* 4 OWords */ |
||
| 50 | define(`OB_CONTROL_4', `4') /* 8 OWords */ |
||
| 51 | |||
| 52 | #ifdef DEV_SNB |
||
| 53 | |||
| 54 | define(`OB_WRITE_COMMIT_CATEGORY', `1') /* write commit on Sandybrige */ |
||
| 55 | |||
| 56 | #else |
||
| 57 | |||
| 58 | define(`OB_WRITE_COMMIT_CATEGORY', `0') /* category on Ivybridge */ |
||
| 59 | |||
| 60 | #endif |
||
| 61 | |||
| 62 | define(`OB_HEADER_PRESENT', `1') |
||
| 63 | |||
| 64 | define(`INTER_VME_OUTPUT_IN_BYTES', `160') |
||
| 65 | define(`INTER_VME_OUTPUT_IN_OWS', `10') |
||
| 66 | define(`INTER_VME_OUTPUT_MV_IN_OWS', `8') |
||
| 67 | |||
| 68 | define(`MFC_AVC_PAK_OBJECT_INTRA_DW0', `0x71490009:UD') |
||
| 69 | define(`MFC_AVC_PAK_OBJECT_INTRA_DW3', `0x000e0000:UD') /* CbpDC (1 << 19 | 1 << 18 | 1 << 17) */ |
||
| 70 | define(`MFC_AVC_PAK_OBJECT_INTRA_DW4', `0xFFFF0000:UD') /* CBP for Y */ |
||
| 71 | define(`MFC_AVC_PAK_OBJECT_INTRA_DW5', `0x000F000F:UD') |
||
| 72 | define(`MFC_AVC_PAK_OBJECT_INTRA_DW6', `0x04000000:UD') /* the flag of the last macroblock */ |
||
| 73 | |||
| 74 | define(`MFC_AVC_PAK_OBJECT_INTER_DW0', `MFC_AVC_PAK_OBJECT_INTRA_DW0') |
||
| 75 | define(`MFC_AVC_PAK_OBJECT_INTER_DW1', `0x20:UD') /* 32 MVs */ |
||
| 76 | define(`MFC_AVC_PAK_OBJECT_INTER_DW2', `INTER_VME_OUTPUT_IN_BYTES:UD') /* offset, in bytes */ |
||
| 77 | define(`MFC_AVC_PAK_OBJECT_INTER_DW3', `0x014e0000:UD') /* |
||
| 78 | * (1 << 24) | PackedMvNum, Debug |
||
| 79 | * (4 << 20) | 8 MV, SNB don't use it |
||
| 80 | * (1 << 19) | CbpDcY |
||
| 81 | * (1 << 18) | CbpDcU |
||
| 82 | * (1 << 17) | CbpDcV |
||
| 83 | * (0 << 15) | Transform8x8Flag = 0 |
||
| 84 | * (0 << 14) | Frame based |
||
| 85 | * (0 << 13) | Inter MB |
||
| 86 | * (1 << 8) | MbType = P_L0_16x16 |
||
| 87 | * (0 << 7) | MBZ for frame |
||
| 88 | * (0 << 6) | MBZ |
||
| 89 | * (2 << 4) | MBZ for inter |
||
| 90 | * (0 << 3) | MBZ |
||
| 91 | * (0 << 2) | SkipMbFlag |
||
| 92 | * (0 << 0) InterMbMode |
||
| 93 | */ |
||
| 94 | define(`MFC_AVC_PAK_OBJECT_INTER_DW4', `MFC_AVC_PAK_OBJECT_INTRA_DW4') |
||
| 95 | define(`MFC_AVC_PAK_OBJECT_INTER_DW5', `MFC_AVC_PAK_OBJECT_INTRA_DW5') |
||
| 96 | define(`MFC_AVC_PAK_OBJECT_INTER_DW6', `MFC_AVC_PAK_OBJECT_INTRA_DW6') |
||
| 97 | |||
| 98 | define(`MI_BATCH_BUFFER_END', `0x05000000:UD') |
||
| 99 | |||
| 100 | /* GRF registers |
||
| 101 | * r0 header |
||
| 102 | * r1~r4 constant buffer (reserved) |
||
| 103 | * r5 inline data |
||
| 104 | * r6~r7 reserved |
||
| 105 | * r8~r15 temporary registers |
||
| 106 | * r16 write back of Oword Block Write |
||
| 107 | */ |
||
| 108 | /* |
||
| 109 | * GRF 0 -- header |
||
| 110 | */ |
||
| 111 | define(`thread_id_ub', `r0.20<0,1,0>:UB') /* thread id in payload */ |
||
| 112 | |||
| 113 | /* |
||
| 114 | * GRF 1~4 -- Constant Buffer (reserved) |
||
| 115 | */ |
||
| 116 | |||
| 117 | define(`FLAG_MASK_LAST_SLICE', `0x0001:uw') |
||
| 118 | define(`FLAG_MASK_LAST_OBJECT', `0x0002:uw') |
||
| 119 | define(`FLAG_MASK_FIRST_OBJECT', `0x0004:uw') |
||
| 120 | |||
| 121 | /* |
||
| 122 | * GRF 5 -- inline data |
||
| 123 | */ |
||
| 124 | define(`inline_reg0', `r5') |
||
| 125 | define(`head_offset', `inline_reg0.0') /* :ud, in units of Owords */ |
||
| 126 | define(`batchbuffer_offset', `inline_reg0.4') /* :ud, in units of Owords */ |
||
| 127 | define(`tail_size', `inline_reg0.8') /* :w, in units of Owords */ |
||
| 128 | define(`head_size', `inline_reg0.10') /* :w, in units of Owords */ |
||
| 129 | define(`flags', `inline_reg0.12') /* :uw, |
||
| 130 | * bit0 the flag of the last slice |
||
| 131 | * bit1 the flag of the last object in a slice |
||
| 132 | * bit2 the flag of the first object in a slice |
||
| 133 | */ |
||
| 134 | define(`total_mbs', `inline_reg0.14') /* :w, the number of macroblock commands |
||
| 135 | * being processed by the kernel |
||
| 136 | */ |
||
| 137 | define(`mb_x', `inline_reg0.16') /* :ub, */ |
||
| 138 | define(`mb_y', `inline_reg0.17') /* :ub, */ |
||
| 139 | define(`mb_xy', `inline_reg0.16') /* :uw, */ |
||
| 140 | define(`width_in_mb', `inline_reg0.20') /* :uw, the picture width in macroblocks */ |
||
| 141 | define(`qp', `inline_reg0.22') /* :ub, */ |
||
| 142 | define(`ref_idx0', `inline_reg0.24') /* :ud */ |
||
| 143 | define(`ref_idx1', `inline_reg0.28') /* :ud */ |
||
| 144 | |||
| 145 | /* |
||
| 146 | * GRF 8~15 -- temporary registers |
||
| 147 | */ |
||
| 148 | define(`tmp_reg0', `r8') |
||
| 149 | define(`tmp_reg1', `r9') |
||
| 150 | define(`tmp_reg2', `r10') |
||
| 151 | define(`tmp_reg3', `r11') |
||
| 152 | define(`tmp_reg4', `r12') |
||
| 153 | define(`tmp_reg5', `r13') |
||
| 154 | define(`tmp_reg6', `r14') |
||
| 155 | define(`tmp_reg7', `r15') |
||
| 156 | |||
| 157 | define(`tmp_vme_output', `tmp_reg0') |
||
| 158 | define(`tmp_slice_header', `tmp_reg1') |
||
| 159 | define(`tmp_mfc_batchbuffer', `tmp_reg2') |
||
| 160 | define(`tmp_offset', `tmp_reg7') |
||
| 161 | /* |
||
| 162 | * GRF 16~23 write back for Oword Block Read message |
||
| 163 | */ |
||
| 164 | define(`ob_read_wb', `r16<1>:uw') |
||
| 165 | define(`ob_read_wb0', `r16') |
||
| 166 | define(`ob_read_wb1', `r17') |
||
| 167 | define(`ob_read_wb2', `r18') |
||
| 168 | define(`ob_read_wb3', `r19') |
||
| 169 | define(`ob_read_wb4', `r20') |
||
| 170 | define(`ob_read_wb5', `r21') |
||
| 171 | define(`ob_read_wb6', `r22') |
||
| 172 | define(`ob_read_wb7', `r23') |
||
| 173 | |||
| 174 | define(`ob_read_wb_len_slice_header', `1') |
||
| 175 | define(`ob_read_wb_len_vme_intra', `1') |
||
| 176 | define(`ob_read_wb_len_vme_inter', `1') |
||
| 177 | |||
| 178 | #ifdef DEV_SNB |
||
| 179 | |||
| 180 | /* |
||
| 181 | * GRF 24~25 write back for Oword Block Write message |
||
| 182 | */ |
||
| 183 | |||
| 184 | define(`ob_write_wb', `r24') |
||
| 185 | define(`ob_write_wb_length', `1') |
||
| 186 | |||
| 187 | #else |
||
| 188 | |||
| 189 | /* |
||
| 190 | * GRF 24~25 -- reserved |
||
| 191 | */ |
||
| 192 | define(`ob_write_wb', `null<1>:W') |
||
| 193 | define(`ob_write_wb_length', `0') |
||
| 194 | |||
| 195 | #endif |
||
| 196 | |||
| 197 | /* |
||
| 198 | * GRF 26~27 |
||
| 199 | */ |
||
| 200 | define(`pak_object_ud', `r26.0') |
||
| 201 | define(`pak_object0_ud', `r26.0') |
||
| 202 | define(`pak_object1_ud', `r26.4') |
||
| 203 | define(`pak_object2_ud', `r26.8') |
||
| 204 | define(`pak_object3_ud', `r26.12') |
||
| 205 | define(`pak_object4_ud', `r26.16') |
||
| 206 | define(`pak_object5_ud', `r26.20') |
||
| 207 | define(`pak_object6_ud', `r26.24') |
||
| 208 | define(`pak_object7_ud', `r26.28') |
||
| 209 | define(`pak_object8_ud', `r27.0') |
||
| 210 | define(`pak_object9_ud', `r27.4') |
||
| 211 | define(`pak_object10_ud', `r27.8') |
||
| 212 | define(`pak_object11_ud', `r27.12') |
||
| 213 | |||
| 214 | #ifdef DEV_SNB |
||
| 215 | |||
| 216 | /* |
||
| 217 | * Message Payload registers |
||
| 218 | */ |
||
| 219 | define(`msg_ind', `0') |
||
| 220 | define(`msg_reg0', `m0') |
||
| 221 | define(`msg_reg1', `m1') |
||
| 222 | define(`msg_reg2', `m2') |
||
| 223 | define(`msg_reg3', `m3') |
||
| 224 | define(`msg_reg4', `m4') |
||
| 225 | define(`msg_reg5', `m5') |
||
| 226 | define(`msg_reg6', `m6') |
||
| 227 | define(`msg_reg7', `m7') |
||
| 228 | define(`msg_reg8', `m8') |
||
| 229 | |||
| 230 | #else |
||
| 231 | |||
| 232 | /* |
||
| 233 | * Message Payload registers |
||
| 234 | */ |
||
| 235 | define(`msg_ind', `64') |
||
| 236 | define(`msg_reg0', `g64') |
||
| 237 | define(`msg_reg1', `g65') |
||
| 238 | define(`msg_reg2', `g66') |
||
| 239 | define(`msg_reg3', `g67') |
||
| 240 | define(`msg_reg4', `g68') |
||
| 241 | define(`msg_reg5', `g69') |
||
| 242 | define(`msg_reg6', `g70') |
||
| 243 | define(`msg_reg7', `g71') |
||
| 244 | define(`msg_reg8', `g72') |
||
| 245 | |||
| 246 | #endif |