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| Rev | Author | Line No. | Line |
|---|---|---|---|
| 5361 | serge | 1 | /* |
| 2 | * Copyright © 2010 Intel Corporation |
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| 3 | * |
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| 4 | * Permission is hereby granted, free of charge, to any person obtaining a |
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| 5 | * copy of this software and associated documentation files (the "Software"), |
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| 6 | * to deal in the Software without restriction, including without limitation |
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| 7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
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| 8 | * and/or sell copies of the Software, and to permit persons to whom the |
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| 9 | * Software is furnished to do so, subject to the following conditions: |
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| 10 | * |
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| 11 | * The above copyright notice and this permission notice (including the next |
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| 12 | * paragraph) shall be included in all copies or substantial portions of the |
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| 13 | * Software. |
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| 14 | * |
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| 15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
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| 16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
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| 17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
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| 18 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER |
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| 19 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING |
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| 20 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS |
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| 21 | * IN THE SOFTWARE. |
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| 22 | * |
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| 23 | */ |
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| 24 | |||
| 25 | include(`exa_wm.g4i') |
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| 26 | |||
| 27 | /* |
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| 28 | * Prepare data in m2-m3 for Red channel, m4-m5 for Green channel, |
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| 29 | * m6-m7 for Blue and m8-m9 for Alpha channel |
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| 30 | */ |
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| 31 | define(`slot_r_00', `m2') |
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| 32 | define(`slot_r_01', `m3') |
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| 33 | define(`slot_g_00', `m4') |
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| 34 | define(`slot_g_01', `m5') |
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| 35 | define(`slot_b_00', `m6') |
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| 36 | define(`slot_b_01', `m7') |
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| 37 | define(`slot_a_00', `m8') |
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| 38 | define(`slot_a_01', `m9') |
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| 39 | define(`data_port_msg_2_ind', `2') |
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| 40 | |||
| 41 | mov (8) slot_r_00<1>F src_sample_r_01<8,8,1>F { align1 }; |
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| 42 | mov (8) slot_r_01<1>F src_sample_r_23<8,8,1>F { align1 }; |
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| 43 | |||
| 44 | mov (8) slot_g_00<1>F src_sample_g_01<8,8,1>F { align1 }; |
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| 45 | mov (8) slot_g_01<1>F src_sample_g_23<8,8,1>F { align1 }; |
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| 46 | |||
| 47 | mov (8) slot_b_00<1>F src_sample_b_01<8,8,1>F { align1 }; |
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| 48 | mov (8) slot_b_01<1>F src_sample_b_23<8,8,1>F { align1 }; |
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| 49 | |||
| 50 | mov (8) slot_a_00<1>F src_sample_a_01<8,8,1>F { align1 }; |
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| 51 | mov (8) slot_a_01<1>F src_sample_a_23<8,8,1>F { align1 }; |
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| 52 | |||
| 53 | /* write */ |
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| 54 | send (16) |
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| 55 | data_port_msg_2_ind |
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| 56 | acc0<1>UW |
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| 57 | null |
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| 58 | write ( |
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| 59 | 0, /* binding_table */ |
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| 60 | 16, /* pixel scordboard clear, msg type simd16 single source */ |
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| 61 | 12, /* render target write */ |
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| 62 | 0, /* no write commit message */ |
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| 63 | |||
| 64 | ) |
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| 65 | mlen 8 |
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| 66 | rlen 0 |
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| 67 | { align1 EOT }; |
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| 68 | |||
| 69 | nop; |
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| 70 | nop; |
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| 71 | nop; |
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| 72 | nop; |
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| 73 | nop; |
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| 74 | nop; |
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| 75 | nop; |
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| 76 | nop; |
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| 77 |