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| Rev | Author | Line No. | Line |
|---|---|---|---|
| 5361 | serge | 1 | /* |
| 2 | * Copyright 2000-2011 Intel Corporation All Rights Reserved |
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| 3 | * |
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| 4 | * Licensed under the Apache License, Version 2.0 (the "License"); |
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| 5 | * you may not use this file except in compliance with the License. |
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| 6 | * You may obtain a copy of the License at |
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| 7 | * |
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| 8 | * http://www.apache.org/licenses/LICENSE-2.0 |
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| 9 | * |
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| 10 | * Unless required by applicable law or agreed to in writing, software |
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| 11 | * distributed under the License is distributed on an "AS IS" BASIS, |
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| 12 | * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. |
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| 13 | * See the License for the specific language governing permissions and |
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| 14 | * limitations under the License. |
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| 15 | */ |
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| 16 | // 44 // Total instruction count |
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| 17 | // 1 // Total kernel count |
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| 18 | |||
| 19 | |||
| 20 | |||
| 21 | // Module name: common.inc |
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| 22 | // |
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| 23 | // Common header file for all Video-Processing kernels |
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| 24 | // |
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| 25 | |||
| 26 | .default_execution_size (16) |
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| 27 | .default_register_type :ub |
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| 28 | |||
| 29 | .reg_count_total 128 |
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| 30 | .reg_count_payload 7 |
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| 31 | |||
| 32 | //========== Common constants ========== |
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| 33 | |||
| 34 | |||
| 35 | //========== Macros ========== |
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| 36 | |||
| 37 | |||
| 38 | //Fast Jump, For more details see "Set_Layer_N.asm" |
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| 39 | |||
| 40 | |||
| 41 | //========== Defines ==================== |
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| 42 | |||
| 43 | //========== Static Parameters (Common To All) ========== |
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| 44 | //r1 |
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| 45 | |||
| 46 | |||
| 47 | //r2 |
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| 48 | |||
| 49 | // e.g. byte0 byte1 byte2 |
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| 50 | // YUYV 0 1 3 |
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| 51 | // YVYU 0 3 1 |
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| 52 | |||
| 53 | //Color Pipe (IECP) parameters |
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| 54 | |||
| 55 | |||
| 56 | //ByteCopy |
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| 57 | |||
| 58 | |||
| 59 | //r4 |
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| 60 | |||
| 61 | // e.g. byte0 byte1 byte2 |
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| 62 | // YUYV 0 1 3 |
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| 63 | // YVYU 0 3 1 |
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| 64 | |||
| 65 | |||
| 66 | //========== Inline parameters (Common To All) =========== |
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| 67 | |||
| 68 | |||
| 69 | //============== Binding Index Table=========== |
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| 70 | //Common between DNDI and DNUV |
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| 71 | |||
| 72 | |||
| 73 | //================= Common Message Descriptor ===== |
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| 74 | // Message descriptor for thread spawning |
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| 75 | // Message Descriptors |
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| 76 | // = 000 0001 (min message len 1 ) 0,0000 (resp len 0 -add later) |
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| 77 | // 0000,0000,0000 |
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| 78 | // 0001(Spawn a root thread),0001 (Root thread spawn thread) |
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| 79 | // = 0x02000011 |
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| 80 | // Thread Spawner Message Descriptor |
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| 81 | |||
| 82 | |||
| 83 | // Message descriptor for atomic operation add |
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| 84 | // Message Descriptors |
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| 85 | // = 000 0110 (min message len 6 ) 0,0000 (resp len 0 -add later) |
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| 86 | // 1(header present)001,10(typed atomic operation)0(return enabled)0(slot group, low 8 bits),0111 (AOP_Add) |
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| 87 | // 0000,0000 (Binding table index, added later) |
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| 88 | // = 0x02000011 |
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| 89 | |||
| 90 | // Atomic Operation Add Message Descriptor |
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| 91 | |||
| 92 | |||
| 93 | // Message descriptor for dataport media write |
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| 94 | // Message Descriptors |
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| 95 | // = 000 0001 (min message len 1 - add later) 00000 (resp len 0) |
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| 96 | // 1 (header present 1) 0 1010 (media block write) 000000 |
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| 97 | // 00000000 (binding table index - set later) |
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| 98 | // = 0x020A8000 |
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| 99 | |||
| 100 | |||
| 101 | // Message Length defines |
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| 102 | |||
| 103 | |||
| 104 | // Response Length defines |
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| 105 | |||
| 106 | |||
| 107 | // Block Width and Height Size defines |
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| 108 | |||
| 109 | |||
| 110 | // Extended Message Descriptors |
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| 111 | |||
| 112 | |||
| 113 | // Common message descriptors: |
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| 114 | |||
| 115 | |||
| 116 | //===================== Math Function Control =================================== |
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| 117 | |||
| 118 | |||
| 119 | //============ Message Registers =============== |
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| 120 | // buf4 starts from r28 |
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| 121 | |||
| 122 | |||
| 123 | //#define mMSGHDR_EOT r43 // Dummy Message Register for EOT |
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| 124 | |||
| 125 | |||
| 126 | .declare mubMSGPAYLOAD Base=r30 ElementSize=1 SrcRegion=<16;16,1> Type=ub |
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| 127 | .declare muwMSGPAYLOAD Base=r30 ElementSize=2 SrcRegion=<16;16,1> Type=uw |
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| 128 | .declare mudMSGPAYLOAD Base=r30 ElementSize=4 SrcRegion=<8;8,1> Type=ud |
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| 129 | .declare mfMSGPAYLOAD Base=r30 ElementSize=4 SrcRegion=<8;8,1> Type=f |
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| 130 | |||
| 131 | //=================== End of thread instruction =========================== |
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| 132 | |||
| 133 | |||
| 134 | //=====================Pointers Used===================================== |
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| 135 | |||
| 136 | |||
| 137 | //======================================================================= |
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| 138 | |||
| 139 | |||
| 140 | //r9-r17 |
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| 141 | // Define temp space for any usages |
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| 142 | |||
| 143 | |||
| 144 | // Common Buffers |
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| 145 | |||
| 146 | |||
| 147 | // temp space for rotation |
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| 148 | |||
| 149 | .declare fROBUF Base=r9.0 ElementSize=4 SrcRegion=<8;8,1> DstRegion=<1> Type=f |
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| 150 | |||
| 151 | .declare udROBUF Base=r9.0 ElementSize=4 SrcRegion=<8;8,1> DstRegion=<1> Type=ud |
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| 152 | |||
| 153 | .declare uwROBUF Base=r9.0 ElementSize=2 SrcRegion=<16;16,1> DstRegion=<1> Type=uw |
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| 154 | |||
| 155 | .declare ubROBUF Base=r9.0 ElementSize=1 SrcRegion=<16;16,1> DstRegion=<1> Type=ub |
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| 156 | |||
| 157 | .declare ub4ROBUF Base=r9.0 ElementSize=1 SrcRegion=<32;8,4> DstRegion=<4> Type=ub |
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| 158 | |||
| 159 | |||
| 160 | // End of common.inc |
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| 161 | |||
| 162 | |||
| 163 | // FileName: PL2_AVS_Buf_0.asm |
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| 164 | // Author: Tatiya, Rupesh |
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| 165 | // Description: Loads 8x8 AVS/IEF PL2 data into Buffer 0 |
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| 166 | |||
| 167 | |||
| 168 | |||
| 169 | // FileName : PL2_AVS_Buf.asm |
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| 170 | // Author : Tatiya, Rupesh |
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| 171 | // Description : Loads 8x8 AVS/IEF PL2 data into Buffer N |
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| 172 | |||
| 173 | |||
| 174 | |||
| 175 | // Module name: Scaling.inc |
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| 176 | |||
| 177 | |||
| 178 | |||
| 179 | |||
| 180 | // Description: Includes all definitions explicit to Fast Composite. |
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| 181 | |||
| 182 | |||
| 183 | |||
| 184 | |||
| 185 | // End of common.inc |
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| 186 | |||
| 187 | |||
| 188 | //========== GRF partition ========== |
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| 189 | // r0 header : r0 (1 GRF) |
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| 190 | // Static parameters : r1 - r6 (6 GRFS) |
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| 191 | // Inline parameters : r7 - r8 (2 GRFs) |
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| 192 | // MSGSRC : r27 (1 GRF) |
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| 193 | //=================================== |
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| 194 | |||
| 195 | //Interface: |
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| 196 | //========== Static Parameters (Explicit To Fast Composite) ========== |
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| 197 | //r1 |
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| 198 | //CSC Set 0 |
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| 199 | |||
| 200 | |||
| 201 | .declare udCSC_CURBE Base=r1.0 ElementSize=4 Type=ud |
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| 202 | |||
| 203 | //Constant alpha |
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| 204 | |||
| 205 | |||
| 206 | //r2 |
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| 207 | |||
| 208 | |||
| 209 | // Gen7 AVS WA |
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| 210 | |||
| 211 | |||
| 212 | // WiDi Definitions |
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| 213 | |||
| 214 | |||
| 215 | //Colorfill |
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| 216 | |||
| 217 | |||
| 218 | // 0: 0-degree, 1: 90, 2: 180, 3: 270-degree, clockwise. |
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| 219 | |||
| 220 | .declare ubCOLOR_PIXEL_VAL Base=r2.20 ElementSize=1 SrcRegion=<0;1,0> DstRegion=<1> Type=ub |
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| 221 | |||
| 222 | //r3 |
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| 223 | //Normalised Ratio of Horizontal step size with main video for all layers |
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| 224 | |||
| 225 | |||
| 226 | //Normalised Ratio of Horizontal step size with main video for all layers becomes |
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| 227 | //Normalised Horizontal step size for all layers in VP_Setup.asm |
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| 228 | |||
| 229 | |||
| 230 | //r4 |
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| 231 | //Normalised Vertical step size for all layers |
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| 232 | |||
| 233 | |||
| 234 | //r5 |
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| 235 | //Normalised Vertical Frame Origin for all layers |
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| 236 | |||
| 237 | |||
| 238 | //r6 |
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| 239 | //Normalised Horizontal Frame Origin for all layers |
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| 240 | |||
| 241 | |||
| 242 | //========== Inline Parameters (Explicit To Fast Composite) ========== |
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| 243 | |||
| 244 | |||
| 245 | //Main video Step X |
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| 246 | |||
| 247 | |||
| 248 | //====================== Binding table (Explicit To Fast Composite)========================================= |
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| 249 | |||
| 250 | |||
| 251 | //Used by Interlaced Scaling Kernels |
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| 252 | |||
| 253 | |||
| 254 | //========== Sampler State Table Index (Explicit To Fast Composite)========== |
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| 255 | //Sampler Index for AVS/IEF messages |
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| 256 | |||
| 257 | |||
| 258 | //Sampler Index for SIMD16 sampler messages |
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| 259 | |||
| 260 | |||
| 261 | //============================================================================= |
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| 262 | |||
| 263 | .declare fBUFFER_0 Base=r64.0 ElementSize=4 SrcRegion=<8;8,1> DstRegion=<1> Type=f |
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| 264 | .declare fBUFFER_1 Base=r80.0 ElementSize=4 SrcRegion=<8;8,1> DstRegion=<1> Type=f |
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| 265 | .declare fBUFFER_2 Base=r96.0 ElementSize=4 SrcRegion=<8;8,1> DstRegion=<1> Type=f |
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| 266 | .declare fBUFFER_3 Base=r112.0 ElementSize=4 SrcRegion=<8;8,1> DstRegion=<1> Type=f |
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| 267 | .declare fBUFFER_4 Base=r28.0 ElementSize=4 SrcRegion=<8;8,1> DstRegion=<1> Type=f |
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| 268 | .declare fBUFFER_5 Base=r46.0 ElementSize=4 SrcRegion=<8;8,1> DstRegion=<1> Type=f |
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| 269 | |||
| 270 | .declare udBUFFER_0 Base=r64.0 ElementSize=4 SrcRegion=<8;8,1> DstRegion=<1> Type=ud |
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| 271 | .declare udBUFFER_1 Base=r80.0 ElementSize=4 SrcRegion=<8;8,1> DstRegion=<1> Type=ud |
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| 272 | .declare udBUFFER_2 Base=r96.0 ElementSize=4 SrcRegion=<8;8,1> DstRegion=<1> Type=ud |
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| 273 | .declare udBUFFER_3 Base=r112.0 ElementSize=4 SrcRegion=<8;8,1> DstRegion=<1> Type=ud |
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| 274 | .declare udBUFFER_4 Base=r28.0 ElementSize=4 SrcRegion=<8;8,1> DstRegion=<1> Type=ud |
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| 275 | .declare udBUFFER_5 Base=r46.0 ElementSize=4 SrcRegion=<8;8,1> DstRegion=<1> Type=ud |
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| 276 | |||
| 277 | .declare uwBUFFER_0 Base=r64.0 ElementSize=2 SrcRegion=<16;16,1> DstRegion=<1> Type=uw |
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| 278 | .declare uwBUFFER_1 Base=r80.0 ElementSize=2 SrcRegion=<16;16,1> DstRegion=<1> Type=uw |
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| 279 | .declare uwBUFFER_2 Base=r96.0 ElementSize=2 SrcRegion=<16;16,1> DstRegion=<1> Type=uw |
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| 280 | .declare uwBUFFER_3 Base=r112.0 ElementSize=2 SrcRegion=<16;16,1> DstRegion=<1> Type=uw |
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| 281 | .declare uwBUFFER_4 Base=r28.0 ElementSize=2 SrcRegion=<16;16,1> DstRegion=<1> Type=uw |
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| 282 | .declare uwBUFFER_5 Base=r46.0 ElementSize=2 SrcRegion=<16;16,1> DstRegion=<1> Type=uw |
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| 283 | |||
| 284 | .declare ubBUFFER_0 Base=r64.0 ElementSize=1 SrcRegion=<16;16,1> DstRegion=<1> Type=ub |
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| 285 | .declare ubBUFFER_1 Base=r80.0 ElementSize=1 SrcRegion=<16;16,1> DstRegion=<1> Type=ub |
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| 286 | .declare ubBUFFER_2 Base=r96.0 ElementSize=1 SrcRegion=<16;16,1> DstRegion=<1> Type=ub |
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| 287 | .declare ubBUFFER_3 Base=r112.0 ElementSize=1 SrcRegion=<16;16,1> DstRegion=<1> Type=ub |
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| 288 | .declare ubBUFFER_4 Base=r28.0 ElementSize=1 SrcRegion=<16;16,1> DstRegion=<1> Type=ub |
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| 289 | .declare ubBUFFER_5 Base=r46.0 ElementSize=1 SrcRegion=<16;16,1> DstRegion=<1> Type=ub |
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| 290 | |||
| 291 | .declare ub4BUFFER_0 Base=r64.0 ElementSize=1 SrcRegion=<32;8,4> DstRegion=<4> Type=ub |
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| 292 | .declare ub4BUFFER_1 Base=r80.0 ElementSize=1 SrcRegion=<32;8,4> DstRegion=<4> Type=ub |
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| 293 | .declare ub4BUFFER_2 Base=r96.0 ElementSize=1 SrcRegion=<32;8,4> DstRegion=<4> Type=ub |
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| 294 | .declare ub4BUFFER_3 Base=r112.0 ElementSize=1 SrcRegion=<32;8,4> DstRegion=<4> Type=ub |
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| 295 | .declare ub4BUFFER_4 Base=r28.0 ElementSize=1 SrcRegion=<32;8,4> DstRegion=<4> Type=ub |
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| 296 | .declare ub4BUFFER_5 Base=r46.0 ElementSize=1 SrcRegion=<32;8,4> DstRegion=<4> Type=ub |
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| 297 | |||
| 298 | //Pointer to mask reg |
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| 299 | |||
| 300 | |||
| 301 | //r18 |
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| 302 | |||
| 303 | |||
| 304 | //Always keep Cannel Pointers and Offsets in same GRF, so that we can use |
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| 305 | // NODDCLR, NODDCHK flags. -rT |
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| 306 | |||
| 307 | |||
| 308 | .declare udCSC_COEFF_0 Base=r18.0 ElementSize=4 Type=ud // 1 GRF |
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| 309 | |||
| 310 | //r19 |
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| 311 | |||
| 312 | |||
| 313 | .declare udCSC_COEFF_1 Base=r19.0 ElementSize=4 Type=ud // 1 GRF |
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| 314 | |||
| 315 | |||
| 316 | //r20 |
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| 317 | |||
| 318 | .declare uwALPHA_MASK_REG_TEMP Base=r20.0 ElementSize=2 SrcRegion=<16;16,1> Type=uw // 1 GRF |
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| 319 | |||
| 320 | //r21 |
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| 321 | |||
| 322 | .declare uwALPHA_MASK_REG Base=r21.0 ElementSize=2 SrcRegion=<16;16,1> Type=uw // 1 GRF |
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| 323 | |||
| 324 | //r22 |
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| 325 | |||
| 326 | |||
| 327 | //Always keep Cannel Pointers and Offsets in same GRF, so that we can use |
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| 328 | // NODDCLR, NODDCHK flags. -rT |
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| 329 | |||
| 330 | |||
| 331 | //Keep fORIGIN_X_NLAS, fY_OFFSET_2ND_BLOCK, fSTEP_X_NLAS, pMSGDSC_COPY, ubCONST_ALPHA_COPY as |
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| 332 | //sub registers of same GRF to enable using NODDCLR NODDCHK. -rT |
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| 333 | |||
| 334 | //r23 |
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| 335 | |||
| 336 | |||
| 337 | //Lumakey |
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| 338 | |||
| 339 | |||
| 340 | //r24 |
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| 341 | |||
| 342 | |||
| 343 | //r25 |
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| 344 | |||
| 345 | |||
| 346 | //r26 |
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| 347 | |||
| 348 | |||
| 349 | //defines to generate LABELS during compile time. |
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| 350 | |||
| 351 | |||
| 352 | // Message Header |
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| 353 | // m0.7 31:0 Debug |
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| 354 | // m0.6 31:0 Debug |
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| 355 | // m0.5 31:0 Ignored |
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| 356 | // m0.4 31:0 Ignored |
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| 357 | // m0.3 31:0 Ignored |
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| 358 | // m0.2 31:16 Ignored |
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| 359 | // 15 Alpha Write Channel Mask enable=0, disable=1 |
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| 360 | // 14 Blue Write Channel Mask (U) |
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| 361 | // 13 Green Write Channel Mask (Y) |
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| 362 | // 12 Red Write Channel Mask (V) |
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| 363 | // 11:0 Ignored |
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| 364 | // m0.1 Ignored |
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| 365 | // m0.0 Ignored |
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| 366 | |||
| 367 | |||
| 368 | // AVS payload |
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| 369 | // m1.7 Group ID Number |
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| 370 | // m1.6 U 2nd Derivative ---> NLAS dx |
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| 371 | // m1.5 Delta V ---> Step Y |
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| 372 | // m1.4 Delta U ---> Step X |
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| 373 | // m1.3 Pixel 0 V Address ---> ORIY (Y0) |
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| 374 | // m1.2 Pixel 0 U Address ---> ORIX (X0) |
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| 375 | // m1.1 Vertical Block Number |
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| 376 | // m1.0 Reserved |
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| 377 | |||
| 378 | // Sampler Message Descriptor |
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| 379 | // 31:29 Reserved 000 |
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| 380 | // 28:25 Message length 0010 |
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| 381 | // 24:20 Response length xxxxx ---> 4GRFs for each enabled channel (AVS), 2GRFs for each enabled channel (sample unorm) |
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| 382 | // 19 Header Present 1 |
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| 383 | // 18:17 SIMD Mode 11 ---> SIMD32/64 |
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| 384 | // 16:12 Message Type xxxxx ---> 01011 sample_8x8, 01100 (sample_unorm), 01010 (sample_unorm+killpix) |
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| 385 | // 11:8 Sampler Index xxxx |
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| 386 | // 7:0 Binding Table Index xxxxxxxx |
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| 387 | |||
| 388 | |||
| 389 | // Msg Header M0.2 |
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| 390 | // 15:15 Alpha Write Channel Mask, 0: written back, 1: not written back |
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| 391 | // 14:14 Blue Write Channel Mask |
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| 392 | // 13:13 Green Write Channel Mask |
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| 393 | // 12:12 Red Write Channel Mask |
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| 394 | |||
| 395 | |||
| 396 | //By design, Buffer 0,1,2,3 always have Layer 0 and Buffer 4,5 always have L1-L7 |
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| 397 | |||
| 398 | |||
| 399 | //used to generate LABELS at compile time. |
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| 400 | |||
| 401 | |||
| 402 | // 18:17 SIMD Mode 10 ---> SIMD16 |
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| 403 | // 16:12 Message Type xxxxx ---> 00000 (SIMD16) |
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| 404 | |||
| 405 | |||
| 406 | //r10-17 - 8 GRFs to load SIMD16 data (upto 4 channels) |
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| 407 | //r18-19 - 2 GRFs to store sampler ramp. |
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| 408 | |||
| 409 | .declare mfSCALING_0X_34X_PAYLOAD Base=r14.0 ElementSize=4 SrcRegion=<8;8,1> DstRegion=<1> Type=f |
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| 410 | .declare muwSCALING_0X_34X_PAYLOAD Base=r14.0 ElementSize=2 SrcRegion=<16;16,1> DstRegion=<1> Type=uw |
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| 411 | .declare mudCALING_0X_34X_PAYLOAD Base=r14.0 ElementSize=4 SrcRegion=<8;8,1> DstRegion=<1> Type=ud |
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| 412 | .declare mubCALING_0X_34X_PAYLOAD Base=r14.0 ElementSize=1 SrcRegion=<32;32,1> DstRegion=<1> Type=ub |
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| 413 | |||
| 414 | |||
| 415 | .declare fSCALING_0X_34X_TEMP Base=r9.0 ElementSize=4 SrcRegion=<8;8,1> DstRegion=<1> Type=f |
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| 416 | .declare udSCALING_0X_34X_TEMP Base=r9.0 ElementSize=4 SrcRegion=<8;8,1> DstRegion=<1> Type=ud |
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| 417 | .declare ub4SCALING_0X_34X_TEMP Base=r9.0 ElementSize=1 SrcRegion=<32;8,4> DstRegion=<1> Type=ub |
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| 418 | .declare uwSCALING_0X_34X_TEMP Base=r9.0 ElementSize=2 SrcRegion=<16;16,1> DstRegion=<1> Type=uw |
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| 419 | |||
| 420 | // Sampler ramp is used for Scaling 0X_0.34X |
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| 421 | .declare fSAMPLER_RAMP Base=r9.0 ElementSize=4 SrcRegion=<8;8,1> Type=f // 1 GRFs, 8 elements |
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| 422 | |||
| 423 | |||
| 424 | //#define rMSGDSC_UV r23.0 |
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| 425 | |||
| 426 | |||
| 427 | //End of _SCALING_ |
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| 428 | |||
| 429 | |||
| 430 | //NOTE: We need offsets for second halfof LAYER 0 - even if we do not load it. |
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| 431 | //Update the channel offset in the buffers for the lower 8x4 data for BUFFER_0. |
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| 432 | mov (1) r22.4<1>:ud 0x400040:ud |
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| 433 | |||
| 434 | |||
| 435 | mov (1) r16.3<1>:ud r0.3<0;1,0>:ud |
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| 436 | |||
| 437 | |||
| 438 | //AVS_PAYLOAD already has all the data loaded at this point |
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| 439 | add (1) a0.0<1>:ud r23.5<0;1,0>:ud 0x44EB000:ud //msg desc |
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| 440 | |||
| 441 | mov (1) r16.2<1>:ud 0x0000D000:ud // Enable Red channel |
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| 442 | |||
| 443 | |||
| 444 | |||
| 445 | // set the vertical block number |
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| 446 | |||
| 447 | mov (1) r25.1<1>:ud 3:ud |
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| 448 | |||
| 449 | mov (8) r17.0<1>:ud r25.0<8;8,1>:ud // Copy msg payload mirrors to MRFs |
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| 450 | |||
| 451 | send (1) uwBUFFER_3(0)<1> r16 0x2 a0.0:ud |
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| 452 | // Returns Y data in 4 GRFs in scrambled order |
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| 453 | |||
| 454 | add (1) a0.0<1>:ud r23.5<0;1,0>:ud 0x44EB001:ud // msg desc; 1 is added to change BI to UV |
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| 455 | |||
| 456 | mov (1) r16.2<1>:ud 0x0000E000:ud // Enable Red channel |
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| 457 | |||
| 458 | send (1) uwBUFFER_3(4)<1> r16 0x2 a0.0:ud |
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| 459 | // Returns U data in 4 GRFs in scrambled order |
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| 460 | |||
| 461 | add (1) a0.0<1>:ud r23.5<0;1,0>:ud 0x44EB002:ud // msg desc; 1 is added to change BI to UV |
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| 462 | mov (1) r16.2<1>:ud 0x0000E000:ud // Enable Red channel |
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| 463 | |||
| 464 | send (1) uwBUFFER_3(8)<1> r16 0x2 a0.0:ud |
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| 465 | // Returns V data in 4 GRFs in scrambled order |
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| 466 | |||
| 467 | SKIP_AVS_LOAD_L0_0_: |
||
| 468 | nop |
||
| 469 |