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| Rev | Author | Line No. | Line |
|---|---|---|---|
| 5361 | serge | 1 | /* |
| 2 | * All Video Processing kernels |
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| 3 | * Copyright © <2010>, Intel Corporation. |
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| 4 | * |
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| 5 | * This program is licensed under the terms and conditions of the |
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| 6 | * Eclipse Public License (EPL), version 1.0. The full text of the EPL is at |
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| 7 | * http://www.opensource.org/licenses/eclipse-1.0.php. |
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| 8 | * |
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| 9 | */ |
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| 10 | |||
| 11 | //---------- PL3_Scaling.asm ---------- |
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| 12 | #include "Scaling.inc" |
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| 13 | |||
| 14 | // Build 16 elements ramp in float32 and normalized it |
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| 15 | // mov (8) SAMPLER_RAMP(0)<1> 0x76543210:v |
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| 16 | // add (8) SAMPLER_RAMP(1)<1> SAMPLER_RAMP(0) 8.0:f |
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| 17 | mov (4) SAMPLER_RAMP(0)<1> 0x48403000:vf { NoDDClr }//3, 2, 1, 0 in float vector |
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| 18 | mov (4) SAMPLER_RAMP(0,4)<1> 0x5C585450:vf { NoDDChk }//7, 6, 5, 4 in float vector |
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| 19 | add (8) SAMPLER_RAMP(1)<1> SAMPLER_RAMP(0) 8.0:f |
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| 20 | |||
| 21 | |||
| 22 | //Module: PrepareScaleCoord.asm |
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| 23 | |||
| 24 | // Setup for sampler msg hdr |
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| 25 | mov (2) rMSGSRC.0<1>:ud 0:ud { NoDDClr } // Unused fields |
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| 26 | mov (1) rMSGSRC.2<1>:ud 0:ud { NoDDChk } // Write and offset |
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| 27 | |||
| 28 | // Calculate 16 v based on the step Y and vertical origin |
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| 29 | mov (16) mfMSGPAYLOAD(2)<1> fSRC_VID_V_ORI<0;1,0>:f |
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| 30 | mov (16) SCALE_COORD_Y<1>:f fSRC_VID_V_ORI<0;1,0>:f |
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| 31 | |||
| 32 | // Calculate 16 u based on the step X and hori origin |
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| 33 | // line (16) mfMSGPAYLOAD(0)<1> SCALE_STEP_X<0;1,0>:f SAMPLER_RAMP(0) // Assign to mrf directly |
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| 34 | mov (16) acc0:f fSRC_VID_H_ORI<0;1,0>:f { Compr } |
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| 35 | mac (16) mfMSGPAYLOAD(0)<1> fVIDEO_STEP_X<0;1,0>:f SAMPLER_RAMP(0) { Compr } |
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| 36 | |||
| 37 | //Setup the constants for line instruction |
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| 38 | mov (1) SCALE_LINE_P255<1>:f 255.0:f { NoDDClr } //{ NoDDClr, NoDDChk } |
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| 39 | mov (1) SCALE_LINE_P0_5<1>:f 0.5:f { NoDDChk } |
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| 40 | |||
| 41 | //------------------------------------------------------------------------------ |
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| 42 | |||
| 43 | $for (0; |
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| 44 | // Read 16 sampled pixels and store them in float32 in 8 GRFs in the order of BGRA (VYUA). |
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| 45 | mov (8) MSGHDR_SCALE<1>:ud rMSGSRC<8;8,1>:ud // Copy msg header and payload mirrors to MRFs |
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| 46 | send (16) SCALE_RESPONSE_VW(0)<1> MSGHDR_SCALE udDUMMY_NULL nSMPL_ENGINE SMPLR_MSG_DSC+nSI_SRC_SIMD16_V+nBI_CURRENT_SRC_V |
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| 47 | send (16) SCALE_RESPONSE_YW(0)<1> MSGHDR_SCALE udDUMMY_NULL nSMPL_ENGINE SMPLR_MSG_DSC+nSI_SRC_SIMD16_Y+nBI_CURRENT_SRC_Y |
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| 48 | send (16) SCALE_RESPONSE_UW(0)<1> MSGHDR_SCALE udDUMMY_NULL nSMPL_ENGINE SMPLR_MSG_DSC+nSI_SRC_SIMD16_U+nBI_CURRENT_SRC_U |
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| 49 | |||
| 50 | // Calculate 16 v for next line |
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| 51 | add (16) mfMSGPAYLOAD(2)<1> SCALE_COORD_Y<8;8,1>:f fVIDEO_STEP_Y<0;1,0>:f // Assign to mrf directly |
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| 52 | add (16) SCALE_COORD_Y<1>:f SCALE_COORD_Y<8;8,1>:f fVIDEO_STEP_Y<0;1,0>:f // Assign to mrf directly |
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| 53 | |||
| 54 | // Scale back to [0, 255], convert f to ud |
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| 55 | line (16) acc0:f SCALE_LINE_P255<0;1,0>:f SCALE_RESPONSE_VF(0) { Compr } // Process B, V |
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| 56 | mov (16) SCALE_RESPONSE_VD(0)<1> acc0:f { Compr } |
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| 57 | |||
| 58 | line (16) acc0:f SCALE_LINE_P255<0;1,0>:f SCALE_RESPONSE_YF(0) { Compr } // Process B, V |
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| 59 | mov (16) SCALE_RESPONSE_YD(0)<1> acc0:f { Compr } |
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| 60 | |||
| 61 | line (16) acc0:f SCALE_LINE_P255<0;1,0>:f SCALE_RESPONSE_UF(0) { Compr } // Process B, V |
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| 62 | mov (16) SCALE_RESPONSE_UD(0)<1> acc0:f { Compr } |
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| 63 | |||
| 64 | mov (16) DEST_V(%1)<1> SCALE_RESPONSE_VB(0) //possible error due to truncation - vK |
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| 65 | mov (16) DEST_Y(%1)<1> SCALE_RESPONSE_YB(0) //possible error due to truncation - vK |
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| 66 | mov (16) DEST_U(%1)<1> SCALE_RESPONSE_UB(0) //possible error due to truncation - vK |
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| 67 | |||
| 68 | } |
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| 69 | |||
| 70 | #define nSRC_REGION nREGION_1 |
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| 71 | |||
| 72 | //------------------------------------------------------------------------------ |