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| Rev | Author | Line No. | Line |
|---|---|---|---|
| 5361 | serge | 1 | #ifndef _INTEL_DRIVER_H_ |
| 2 | #define _INTEL_DRIVER_H_ |
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| 3 | |||
| 4 | #include |
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| 5 | //#include |
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| 6 | //#include |
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| 7 | #include |
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| 8 | |||
| 9 | #include |
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| 10 | #include |
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| 11 | #include |
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| 12 | |||
| 13 | #include |
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| 14 | #include "va_backend_compat.h" |
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| 15 | |||
| 16 | #include "intel_compiler.h" |
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| 17 | |||
| 18 | #define BATCH_SIZE 0x80000 |
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| 19 | #define BATCH_RESERVED 0x10 |
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| 20 | |||
| 21 | #define CMD_MI (0x0 << 29) |
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| 22 | #define CMD_2D (0x2 << 29) |
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| 23 | #define CMD_3D (0x3 << 29) |
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| 24 | |||
| 25 | #define MI_NOOP (CMD_MI | 0) |
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| 26 | |||
| 27 | #define MI_BATCH_BUFFER_END (CMD_MI | (0xA << 23)) |
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| 28 | #define MI_BATCH_BUFFER_START (CMD_MI | (0x31 << 23)) |
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| 29 | |||
| 30 | #define MI_FLUSH (CMD_MI | (0x4 << 23)) |
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| 31 | #define MI_FLUSH_STATE_INSTRUCTION_CACHE_INVALIDATE (0x1 << 0) |
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| 32 | |||
| 33 | #define MI_FLUSH_DW (CMD_MI | (0x26 << 23) | 0x2) |
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| 34 | #define MI_FLUSH_DW_VIDEO_PIPELINE_CACHE_INVALIDATE (0x1 << 7) |
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| 35 | |||
| 36 | #define XY_COLOR_BLT_CMD (CMD_2D | (0x50 << 22) | 0x04) |
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| 37 | #define XY_COLOR_BLT_WRITE_ALPHA (1 << 21) |
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| 38 | #define XY_COLOR_BLT_WRITE_RGB (1 << 20) |
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| 39 | #define XY_COLOR_BLT_DST_TILED (1 << 11) |
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| 40 | |||
| 41 | #define GEN8_XY_COLOR_BLT_CMD (CMD_2D | (0x50 << 22) | 0x05) |
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| 42 | |||
| 43 | /* BR13 */ |
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| 44 | #define BR13_8 (0x0 << 24) |
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| 45 | #define BR13_565 (0x1 << 24) |
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| 46 | #define BR13_1555 (0x2 << 24) |
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| 47 | #define BR13_8888 (0x3 << 24) |
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| 48 | |||
| 49 | #define CMD_PIPE_CONTROL (CMD_3D | (3 << 27) | (2 << 24) | (0 << 16)) |
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| 50 | #define CMD_PIPE_CONTROL_CS_STALL (1 << 20) |
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| 51 | #define CMD_PIPE_CONTROL_NOWRITE (0 << 14) |
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| 52 | #define CMD_PIPE_CONTROL_WRITE_QWORD (1 << 14) |
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| 53 | #define CMD_PIPE_CONTROL_WRITE_DEPTH (2 << 14) |
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| 54 | #define CMD_PIPE_CONTROL_WRITE_TIME (3 << 14) |
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| 55 | #define CMD_PIPE_CONTROL_DEPTH_STALL (1 << 13) |
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| 56 | #define CMD_PIPE_CONTROL_WC_FLUSH (1 << 12) |
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| 57 | #define CMD_PIPE_CONTROL_IS_FLUSH (1 << 11) |
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| 58 | #define CMD_PIPE_CONTROL_TC_FLUSH (1 << 10) |
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| 59 | #define CMD_PIPE_CONTROL_NOTIFY_ENABLE (1 << 8) |
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| 60 | #define CMD_PIPE_CONTROL_DC_FLUSH (1 << 5) |
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| 61 | #define CMD_PIPE_CONTROL_GLOBAL_GTT (1 << 2) |
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| 62 | #define CMD_PIPE_CONTROL_LOCAL_PGTT (0 << 2) |
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| 63 | #define CMD_PIPE_CONTROL_STALL_AT_SCOREBOARD (1 << 1) |
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| 64 | #define CMD_PIPE_CONTROL_DEPTH_CACHE_FLUSH (1 << 0) |
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| 65 | |||
| 66 | |||
| 67 | struct intel_batchbuffer; |
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| 68 | |||
| 69 | #define ALIGN(i, n) (((i) + (n) - 1) & ~((n) - 1)) |
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| 70 | #define IS_ALIGNED(i, n) (((i) & ((n)-1)) == 0) |
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| 71 | #define MIN(a, b) ((a) < (b) ? (a) : (b)) |
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| 72 | #define MAX(a, b) ((a) > (b) ? (a) : (b)) |
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| 73 | #define ARRAY_ELEMS(a) (sizeof(a) / sizeof((a)[0])) |
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| 74 | |||
| 75 | #define Bool int |
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| 76 | #define True 1 |
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| 77 | #define False 0 |
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| 78 | |||
| 79 | extern uint32_t g_intel_debug_option_flags; |
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| 80 | #define VA_INTEL_DEBUG_OPTION_ASSERT (1 << 0) |
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| 81 | #define VA_INTEL_DEBUG_OPTION_BENCH (1 << 1) |
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| 82 | |||
| 83 | #define ASSERT_RET(value, fail_ret) do { \ |
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| 84 | if (!(value)) { \ |
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| 85 | if (g_intel_debug_option_flags & VA_INTEL_DEBUG_OPTION_ASSERT) \ |
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| 86 | assert(value); \ |
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| 87 | return fail_ret; \ |
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| 88 | } \ |
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| 89 | } while (0) |
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| 90 | |||
| 91 | #define SET_BLOCKED_SIGSET() do { \ |
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| 92 | sigset_t bl_mask; \ |
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| 93 | sigfillset(&bl_mask); \ |
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| 94 | sigdelset(&bl_mask, SIGFPE); \ |
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| 95 | sigdelset(&bl_mask, SIGILL); \ |
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| 96 | sigdelset(&bl_mask, SIGSEGV); \ |
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| 97 | sigdelset(&bl_mask, SIGBUS); \ |
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| 98 | sigdelset(&bl_mask, SIGKILL); \ |
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| 99 | pthread_sigmask(SIG_SETMASK, &bl_mask, &intel->sa_mask); \ |
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| 100 | } while (0) |
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| 101 | |||
| 102 | #define RESTORE_BLOCKED_SIGSET() do { \ |
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| 103 | pthread_sigmask(SIG_SETMASK, &intel->sa_mask, NULL); \ |
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| 104 | } while (0) |
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| 105 | |||
| 106 | #define PPTHREAD_MUTEX_LOCK() do { \ |
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| 107 | SET_BLOCKED_SIGSET(); \ |
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| 108 | pthread_mutex_lock(&intel->ctxmutex); \ |
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| 109 | } while (0) |
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| 110 | |||
| 111 | #define PPTHREAD_MUTEX_UNLOCK() do { \ |
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| 112 | pthread_mutex_unlock(&intel->ctxmutex); \ |
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| 113 | RESTORE_BLOCKED_SIGSET(); \ |
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| 114 | } while (0) |
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| 115 | |||
| 116 | #define WARN_ONCE(...) do { \ |
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| 117 | static int g_once = 1; \ |
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| 118 | if (g_once) { \ |
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| 119 | g_once = 0; \ |
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| 120 | printf("WARNING: " __VA_ARGS__); \ |
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| 121 | } \ |
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| 122 | } while (0) |
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| 123 | |||
| 124 | struct intel_device_info |
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| 125 | { |
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| 126 | int gen; |
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| 127 | int gt; |
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| 128 | |||
| 129 | unsigned int urb_size; |
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| 130 | unsigned int max_wm_threads; |
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| 131 | |||
| 132 | unsigned int is_g4x : 1; /* gen4 */ |
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| 133 | unsigned int is_ivybridge : 1; /* gen7 */ |
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| 134 | unsigned int is_baytrail : 1; /* gen7 */ |
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| 135 | unsigned int is_haswell : 1; /* gen7 */ |
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| 136 | unsigned int is_cherryview : 1; /* gen8 */ |
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| 137 | }; |
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| 138 | |||
| 139 | struct intel_driver_data |
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| 140 | { |
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| 141 | int fd; |
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| 142 | int device_id; |
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| 143 | int revision; |
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| 144 | |||
| 145 | int dri2Enabled; |
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| 146 | |||
| 147 | // sigset_t sa_mask; |
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| 148 | // pthread_mutex_t ctxmutex; |
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| 149 | int locked; |
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| 150 | |||
| 151 | dri_bufmgr *bufmgr; |
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| 152 | |||
| 153 | unsigned int has_exec2 : 1; /* Flag: has execbuffer2? */ |
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| 154 | unsigned int has_bsd : 1; /* Flag: has bitstream decoder for H.264? */ |
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| 155 | unsigned int has_blt : 1; /* Flag: has BLT unit? */ |
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| 156 | unsigned int has_vebox : 1; /* Flag: has VEBOX unit */ |
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| 157 | |||
| 158 | const struct intel_device_info *device_info; |
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| 159 | }; |
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| 160 | |||
| 161 | bool intel_driver_init(VADriverContextP ctx); |
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| 162 | void intel_driver_terminate(VADriverContextP ctx); |
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| 163 | |||
| 164 | static INLINE struct intel_driver_data * |
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| 165 | intel_driver_data(VADriverContextP ctx) |
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| 166 | { |
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| 167 | return (struct intel_driver_data *)ctx->pDriverData; |
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| 168 | } |
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| 169 | |||
| 170 | struct intel_region |
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| 171 | { |
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| 172 | int x; |
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| 173 | int y; |
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| 174 | unsigned int width; |
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| 175 | unsigned int height; |
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| 176 | unsigned int cpp; |
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| 177 | unsigned int pitch; |
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| 178 | unsigned int tiling; |
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| 179 | unsigned int swizzle; |
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| 180 | dri_bo *bo; |
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| 181 | }; |
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| 182 | |||
| 183 | #define IS_G4X(device_info) (device_info->is_g4x) |
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| 184 | |||
| 185 | #define IS_IRONLAKE(device_info) (device_info->gen == 5) |
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| 186 | |||
| 187 | #define IS_GEN6(device_info) (device_info->gen == 6) |
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| 188 | |||
| 189 | #define IS_HASWELL(device_info) (device_info->is_haswell) |
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| 190 | #define IS_GEN7(device_info) (device_info->gen == 7) |
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| 191 | |||
| 192 | #define IS_CHERRYVIEW(device_info) (device_info->is_cherryview) |
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| 193 | #define IS_GEN8(device_info) (device_info->gen == 8) |
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| 194 | |||
| 195 | #endif /* _INTEL_DRIVER_H_ */ |