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5361 | serge | 1 | /* |
2 | * Copyright © 2012 Intel Corporation |
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3 | * |
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4 | * Permission is hereby granted, free of charge, to any person obtaining a |
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5 | * copy of this software and associated documentation files (the "Software"), |
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6 | * to deal in the Software without restriction, including without limitation |
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7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
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8 | * and/or sell copies of the Software, and to permit persons to whom the |
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9 | * Software is furnished to do so, subject to the following conditions: |
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10 | * |
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11 | * The above copyright notice and this permission notice (including the next |
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12 | * paragraph) shall be included in all copies or substantial portions of the |
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13 | * Software. |
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14 | * |
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15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
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16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
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17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
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18 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER |
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19 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING |
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20 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS |
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21 | * IN THE SOFTWARE. |
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22 | * |
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23 | * Authors: |
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24 | * Xiang Haihao |
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25 | */ |
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26 | |||
27 | #ifndef _I965_GPE_UTILS_H_ |
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28 | #define _I965_GPE_UTILS_H_ |
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29 | |||
30 | #include |
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31 | #include |
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32 | |||
33 | #include "i965_defines.h" |
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34 | #include "i965_drv_video.h" |
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35 | #include "i965_structs.h" |
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36 | |||
37 | #define MAX_GPE_KERNELS 32 |
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38 | |||
39 | struct i965_buffer_surface |
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40 | { |
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41 | dri_bo *bo; |
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42 | unsigned int num_blocks; |
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43 | unsigned int size_block; |
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44 | unsigned int pitch; |
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45 | }; |
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46 | |||
47 | struct i965_gpe_context |
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48 | { |
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49 | struct { |
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50 | dri_bo *bo; |
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51 | unsigned int length; /* in bytes */ |
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52 | } surface_state_binding_table; |
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53 | |||
54 | struct { |
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55 | dri_bo *bo; |
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56 | unsigned int max_entries; |
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57 | unsigned int entry_size; /* in bytes */ |
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58 | } idrt; |
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59 | |||
60 | struct { |
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61 | dri_bo *bo; |
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62 | unsigned int length; /* in bytes */ |
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63 | } curbe; |
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64 | |||
65 | struct { |
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66 | unsigned int gpgpu_mode : 1; |
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67 | unsigned int pad0 : 7; |
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68 | unsigned int max_num_threads : 16; |
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69 | unsigned int num_urb_entries : 8; |
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70 | unsigned int urb_entry_size : 16; |
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71 | unsigned int curbe_allocation_size : 16; |
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72 | } vfe_state; |
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73 | |||
74 | /* vfe_desc5/6/7 is used to determine whether the HW scoreboard is used. |
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75 | * If scoreboard is not used, don't touch them |
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76 | */ |
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77 | union { |
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78 | unsigned int dword; |
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79 | struct { |
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80 | unsigned int mask:8; |
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81 | unsigned int pad:22; |
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82 | unsigned int type:1; |
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83 | unsigned int enable:1; |
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84 | } scoreboard0; |
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85 | }vfe_desc5; |
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86 | |||
87 | union { |
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88 | unsigned int dword; |
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89 | struct { |
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90 | int delta_x0:4; |
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91 | int delta_y0:4; |
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92 | int delta_x1:4; |
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93 | int delta_y1:4; |
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94 | int delta_x2:4; |
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95 | int delta_y2:4; |
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96 | int delta_x3:4; |
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97 | int delta_y3:4; |
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98 | } scoreboard1; |
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99 | } vfe_desc6; |
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100 | |||
101 | union { |
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102 | unsigned int dword; |
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103 | struct { |
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104 | int delta_x4:4; |
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105 | int delta_y4:4; |
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106 | int delta_x5:4; |
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107 | int delta_y5:4; |
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108 | int delta_x6:4; |
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109 | int delta_y6:4; |
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110 | int delta_x7:4; |
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111 | int delta_y7:4; |
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112 | } scoreboard2; |
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113 | } vfe_desc7; |
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114 | |||
115 | unsigned int num_kernels; |
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116 | struct i965_kernel kernels[MAX_GPE_KERNELS]; |
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117 | |||
118 | struct { |
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119 | dri_bo *bo; |
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120 | int bo_size; |
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121 | unsigned int end_offset; |
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122 | } instruction_state; |
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123 | |||
124 | struct { |
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125 | dri_bo *bo; |
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126 | } indirect_state; |
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127 | |||
128 | struct { |
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129 | dri_bo *bo; |
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130 | int bo_size; |
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131 | unsigned int end_offset; |
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132 | } dynamic_state; |
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133 | |||
134 | unsigned int sampler_offset; |
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135 | int sampler_size; |
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136 | unsigned int idrt_offset; |
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137 | int idrt_size; |
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138 | unsigned int curbe_offset; |
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139 | int curbe_size; |
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140 | }; |
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141 | |||
142 | void i965_gpe_context_destroy(struct i965_gpe_context *gpe_context); |
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143 | void i965_gpe_context_init(VADriverContextP ctx, |
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144 | struct i965_gpe_context *gpe_context); |
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145 | void i965_gpe_load_kernels(VADriverContextP ctx, |
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146 | struct i965_gpe_context *gpe_context, |
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147 | struct i965_kernel *kernel_list, |
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148 | unsigned int num_kernels); |
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149 | void gen6_gpe_pipeline_setup(VADriverContextP ctx, |
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150 | struct i965_gpe_context *gpe_context, |
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151 | struct intel_batchbuffer *batch); |
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152 | void i965_gpe_surface2_setup(VADriverContextP ctx, |
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153 | struct i965_gpe_context *gpe_context, |
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154 | struct object_surface *obj_surface, |
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155 | unsigned long binding_table_offset, |
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156 | unsigned long surface_state_offset); |
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157 | void i965_gpe_media_rw_surface_setup(VADriverContextP ctx, |
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158 | struct i965_gpe_context *gpe_context, |
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159 | struct object_surface *obj_surface, |
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160 | unsigned long binding_table_offset, |
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161 | unsigned long surface_state_offset); |
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162 | void i965_gpe_buffer_suface_setup(VADriverContextP ctx, |
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163 | struct i965_gpe_context *gpe_context, |
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164 | struct i965_buffer_surface *buffer_surface, |
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165 | unsigned long binding_table_offset, |
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166 | unsigned long surface_state_offset); |
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167 | void gen7_gpe_surface2_setup(VADriverContextP ctx, |
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168 | struct i965_gpe_context *gpe_context, |
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169 | struct object_surface *obj_surface, |
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170 | unsigned long binding_table_offset, |
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171 | unsigned long surface_state_offset); |
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172 | void gen7_gpe_media_rw_surface_setup(VADriverContextP ctx, |
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173 | struct i965_gpe_context *gpe_context, |
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174 | struct object_surface *obj_surface, |
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175 | unsigned long binding_table_offset, |
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176 | unsigned long surface_state_offset); |
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177 | void gen7_gpe_buffer_suface_setup(VADriverContextP ctx, |
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178 | struct i965_gpe_context *gpe_context, |
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179 | struct i965_buffer_surface *buffer_surface, |
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180 | unsigned long binding_table_offset, |
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181 | unsigned long surface_state_offset); |
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182 | void gen75_gpe_media_chroma_surface_setup(VADriverContextP ctx, |
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183 | struct i965_gpe_context *gpe_context, |
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184 | struct object_surface *obj_surface, |
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185 | unsigned long binding_table_offset, |
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186 | unsigned long surface_state_offset); |
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187 | |||
188 | extern void gen8_gpe_surface2_setup(VADriverContextP ctx, |
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189 | struct i965_gpe_context *gpe_context, |
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190 | struct object_surface *obj_surface, |
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191 | unsigned long binding_table_offset, |
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192 | unsigned long surface_state_offset); |
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193 | extern void gen8_gpe_media_rw_surface_setup(VADriverContextP ctx, |
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194 | struct i965_gpe_context *gpe_context, |
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195 | struct object_surface *obj_surface, |
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196 | unsigned long binding_table_offset, |
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197 | unsigned long surface_state_offset); |
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198 | extern void gen8_gpe_buffer_suface_setup(VADriverContextP ctx, |
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199 | struct i965_gpe_context *gpe_context, |
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200 | struct i965_buffer_surface *buffer_surface, |
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201 | unsigned long binding_table_offset, |
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202 | unsigned long surface_state_offset); |
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203 | extern void gen8_gpe_media_chroma_surface_setup(VADriverContextP ctx, |
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204 | struct i965_gpe_context *gpe_context, |
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205 | struct object_surface *obj_surface, |
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206 | unsigned long binding_table_offset, |
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207 | unsigned long surface_state_offset); |
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208 | |||
209 | void gen8_gpe_pipeline_setup(VADriverContextP ctx, |
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210 | struct i965_gpe_context *gpe_context, |
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211 | struct intel_batchbuffer *batch); |
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212 | |||
213 | |||
214 | void gen8_gpe_context_destroy(struct i965_gpe_context *gpe_context); |
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215 | void gen8_gpe_context_init(VADriverContextP ctx, |
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216 | struct i965_gpe_context *gpe_context); |
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217 | |||
218 | void gen8_gpe_load_kernels(VADriverContextP ctx, |
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219 | struct i965_gpe_context *gpe_context, |
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220 | struct i965_kernel *kernel_list, |
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221 | unsigned int num_kernels); |
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222 | #endif /* _I965_GPE_UTILS_H_ */ |