Rev 4363 | Go to most recent revision | Details | Compare with Previous | Last modification | View Log | RSS feed
Rev | Author | Line No. | Line |
---|---|---|---|
4363 | Serge | 1 | /* |
2 | * Copyright © 2008 Intel Corporation |
||
3 | * |
||
4 | * Permission is hereby granted, free of charge, to any person obtaining a |
||
5 | * copy of this software and associated documentation files (the "Software"), |
||
6 | * to deal in the Software without restriction, including without limitation |
||
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
||
8 | * and/or sell copies of the Software, and to permit persons to whom the |
||
9 | * Software is furnished to do so, subject to the following conditions: |
||
10 | * |
||
11 | * The above copyright notice and this permission notice (including the next |
||
12 | * paragraph) shall be included in all copies or substantial portions of the |
||
13 | * Software. |
||
14 | * |
||
15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
||
16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
||
17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
||
18 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER |
||
19 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING |
||
20 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS |
||
21 | * IN THE SOFTWARE. |
||
22 | * |
||
23 | * Authors: |
||
24 | * Eric Anholt |
||
25 | * |
||
26 | */ |
||
27 | |||
28 | /** |
||
29 | * @file intel_bufmgr_priv.h |
||
30 | * |
||
31 | * Private definitions of Intel-specific bufmgr functions and structures. |
||
32 | */ |
||
33 | |||
34 | #ifndef INTEL_BUFMGR_PRIV_H |
||
35 | #define INTEL_BUFMGR_PRIV_H |
||
36 | |||
37 | /** |
||
38 | * Context for a buffer manager instance. |
||
39 | * |
||
40 | * Contains public methods followed by private storage for the buffer manager. |
||
41 | */ |
||
42 | struct _drm_intel_bufmgr { |
||
43 | /** |
||
44 | * Allocate a buffer object. |
||
45 | * |
||
46 | * Buffer objects are not necessarily initially mapped into CPU virtual |
||
47 | * address space or graphics device aperture. They must be mapped |
||
48 | * using bo_map() or drm_intel_gem_bo_map_gtt() to be used by the CPU. |
||
49 | */ |
||
50 | drm_intel_bo *(*bo_alloc) (drm_intel_bufmgr *bufmgr, const char *name, |
||
51 | unsigned long size, unsigned int alignment); |
||
52 | |||
53 | /** |
||
54 | * Allocate a buffer object, hinting that it will be used as a |
||
55 | * render target. |
||
56 | * |
||
57 | * This is otherwise the same as bo_alloc. |
||
58 | */ |
||
5068 | serge | 59 | drm_intel_bo *(*bo_alloc_for_render) (drm_intel_bufmgr *bufmgr, |
60 | const char *name, |
||
61 | unsigned long size, |
||
62 | unsigned int alignment); |
||
4363 | Serge | 63 | |
64 | /** |
||
65 | * Allocate a tiled buffer object. |
||
66 | * |
||
67 | * Alignment for tiled objects is set automatically; the 'flags' |
||
68 | * argument provides a hint about how the object will be used initially. |
||
69 | * |
||
70 | * Valid tiling formats are: |
||
71 | * I915_TILING_NONE |
||
72 | * I915_TILING_X |
||
73 | * I915_TILING_Y |
||
74 | * |
||
75 | * Note the tiling format may be rejected; callers should check the |
||
76 | * 'tiling_mode' field on return, as well as the pitch value, which |
||
77 | * may have been rounded up to accommodate for tiling restrictions. |
||
78 | */ |
||
79 | drm_intel_bo *(*bo_alloc_tiled) (drm_intel_bufmgr *bufmgr, |
||
80 | const char *name, |
||
81 | int x, int y, int cpp, |
||
82 | uint32_t *tiling_mode, |
||
83 | unsigned long *pitch, |
||
84 | unsigned long flags); |
||
85 | |||
86 | /** Takes a reference on a buffer object */ |
||
87 | void (*bo_reference) (drm_intel_bo *bo); |
||
88 | |||
89 | /** |
||
90 | * Releases a reference on a buffer object, freeing the data if |
||
91 | * no references remain. |
||
92 | */ |
||
93 | void (*bo_unreference) (drm_intel_bo *bo); |
||
94 | |||
95 | /** |
||
96 | * Maps the buffer into userspace. |
||
97 | * |
||
98 | * This function will block waiting for any existing execution on the |
||
99 | * buffer to complete, first. The resulting mapping is available at |
||
100 | * buf->virtual. |
||
101 | */ |
||
102 | int (*bo_map) (drm_intel_bo *bo, int write_enable); |
||
103 | |||
104 | /** |
||
105 | * Reduces the refcount on the userspace mapping of the buffer |
||
106 | * object. |
||
107 | */ |
||
108 | int (*bo_unmap) (drm_intel_bo *bo); |
||
109 | |||
110 | /** |
||
111 | * Write data into an object. |
||
112 | * |
||
113 | * This is an optional function, if missing, |
||
114 | * drm_intel_bo will map/memcpy/unmap. |
||
115 | */ |
||
116 | int (*bo_subdata) (drm_intel_bo *bo, unsigned long offset, |
||
117 | unsigned long size, const void *data); |
||
118 | |||
119 | /** |
||
120 | * Read data from an object |
||
121 | * |
||
122 | * This is an optional function, if missing, |
||
123 | * drm_intel_bo will map/memcpy/unmap. |
||
124 | */ |
||
125 | // int (*bo_get_subdata) (drm_intel_bo *bo, unsigned long offset, |
||
126 | // unsigned long size, void *data); |
||
127 | |||
128 | /** |
||
129 | * Waits for rendering to an object by the GPU to have completed. |
||
130 | * |
||
131 | * This is not required for any access to the BO by bo_map, |
||
132 | * bo_subdata, etc. It is merely a way for the driver to implement |
||
133 | * glFinish. |
||
134 | */ |
||
135 | void (*bo_wait_rendering) (drm_intel_bo *bo); |
||
136 | |||
137 | /** |
||
138 | * Tears down the buffer manager instance. |
||
139 | */ |
||
140 | void (*destroy) (drm_intel_bufmgr *bufmgr); |
||
141 | |||
142 | /** |
||
143 | * Add relocation entry in reloc_buf, which will be updated with the |
||
144 | * target buffer's real offset on on command submission. |
||
145 | * |
||
146 | * Relocations remain in place for the lifetime of the buffer object. |
||
147 | * |
||
148 | * \param bo Buffer to write the relocation into. |
||
149 | * \param offset Byte offset within reloc_bo of the pointer to |
||
150 | * target_bo. |
||
151 | * \param target_bo Buffer whose offset should be written into the |
||
152 | * relocation entry. |
||
153 | * \param target_offset Constant value to be added to target_bo's |
||
154 | * offset in relocation entry. |
||
155 | * \param read_domains GEM read domains which the buffer will be |
||
156 | * read into by the command that this relocation |
||
157 | * is part of. |
||
158 | * \param write_domains GEM read domains which the buffer will be |
||
159 | * dirtied in by the command that this |
||
160 | * relocation is part of. |
||
161 | */ |
||
162 | int (*bo_emit_reloc) (drm_intel_bo *bo, uint32_t offset, |
||
163 | drm_intel_bo *target_bo, uint32_t target_offset, |
||
164 | uint32_t read_domains, uint32_t write_domain); |
||
165 | int (*bo_emit_reloc_fence)(drm_intel_bo *bo, uint32_t offset, |
||
166 | drm_intel_bo *target_bo, |
||
167 | uint32_t target_offset, |
||
168 | uint32_t read_domains, |
||
169 | uint32_t write_domain); |
||
170 | |||
171 | /** Executes the command buffer pointed to by bo. */ |
||
172 | int (*bo_exec) (drm_intel_bo *bo, int used, |
||
173 | drm_clip_rect_t *cliprects, int num_cliprects, |
||
174 | int DR4); |
||
175 | |||
176 | /** Executes the command buffer pointed to by bo on the selected |
||
177 | * ring buffer |
||
178 | */ |
||
179 | int (*bo_mrb_exec) (drm_intel_bo *bo, int used, |
||
180 | drm_clip_rect_t *cliprects, int num_cliprects, |
||
181 | int DR4, unsigned flags); |
||
182 | |||
183 | /** |
||
184 | * Pin a buffer to the aperture and fix the offset until unpinned |
||
185 | * |
||
186 | * \param buf Buffer to pin |
||
187 | * \param alignment Required alignment for aperture, in bytes |
||
188 | */ |
||
189 | int (*bo_pin) (drm_intel_bo *bo, uint32_t alignment); |
||
190 | |||
191 | /** |
||
192 | * Unpin a buffer from the aperture, allowing it to be removed |
||
193 | * |
||
194 | * \param buf Buffer to unpin |
||
195 | */ |
||
196 | int (*bo_unpin) (drm_intel_bo *bo); |
||
197 | |||
198 | /** |
||
199 | * Ask that the buffer be placed in tiling mode |
||
200 | * |
||
201 | * \param buf Buffer to set tiling mode for |
||
202 | * \param tiling_mode desired, and returned tiling mode |
||
203 | */ |
||
204 | int (*bo_set_tiling) (drm_intel_bo *bo, uint32_t * tiling_mode, |
||
205 | uint32_t stride); |
||
206 | |||
207 | /** |
||
208 | * Get the current tiling (and resulting swizzling) mode for the bo. |
||
209 | * |
||
210 | * \param buf Buffer to get tiling mode for |
||
211 | * \param tiling_mode returned tiling mode |
||
212 | * \param swizzle_mode returned swizzling mode |
||
213 | */ |
||
214 | int (*bo_get_tiling) (drm_intel_bo *bo, uint32_t * tiling_mode, |
||
215 | uint32_t * swizzle_mode); |
||
216 | |||
217 | /** |
||
218 | * Create a visible name for a buffer which can be used by other apps |
||
219 | * |
||
220 | * \param buf Buffer to create a name for |
||
221 | * \param name Returned name |
||
222 | */ |
||
223 | int (*bo_flink) (drm_intel_bo *bo, uint32_t * name); |
||
224 | |||
225 | /** |
||
226 | * Returns 1 if mapping the buffer for write could cause the process |
||
227 | * to block, due to the object being active in the GPU. |
||
228 | */ |
||
229 | int (*bo_busy) (drm_intel_bo *bo); |
||
230 | |||
231 | /** |
||
232 | * Specify the volatility of the buffer. |
||
233 | * \param bo Buffer to create a name for |
||
234 | * \param madv The purgeable status |
||
235 | * |
||
236 | * Use I915_MADV_DONTNEED to mark the buffer as purgeable, and it will be |
||
237 | * reclaimed under memory pressure. If you subsequently require the buffer, |
||
238 | * then you must pass I915_MADV_WILLNEED to mark the buffer as required. |
||
239 | * |
||
240 | * Returns 1 if the buffer was retained, or 0 if it was discarded whilst |
||
241 | * marked as I915_MADV_DONTNEED. |
||
242 | */ |
||
243 | int (*bo_madvise) (drm_intel_bo *bo, int madv); |
||
244 | |||
245 | int (*check_aperture_space) (drm_intel_bo ** bo_array, int count); |
||
246 | |||
247 | /** |
||
248 | * Disable buffer reuse for buffers which will be shared in some way, |
||
249 | * as with scanout buffers. When the buffer reference count goes to |
||
250 | * zero, it will be freed and not placed in the reuse list. |
||
251 | * |
||
252 | * \param bo Buffer to disable reuse for |
||
253 | */ |
||
254 | int (*bo_disable_reuse) (drm_intel_bo *bo); |
||
255 | |||
256 | /** |
||
257 | * Query whether a buffer is reusable. |
||
258 | * |
||
259 | * \param bo Buffer to query |
||
260 | */ |
||
261 | int (*bo_is_reusable) (drm_intel_bo *bo); |
||
262 | |||
263 | /** |
||
264 | * |
||
265 | * Return the pipe associated with a crtc_id so that vblank |
||
266 | * synchronization can use the correct data in the request. |
||
267 | * This is only supported for KMS and gem at this point, when |
||
268 | * unsupported, this function returns -1 and leaves the decision |
||
269 | * of what to do in that case to the caller |
||
270 | * |
||
271 | * \param bufmgr the associated buffer manager |
||
272 | * \param crtc_id the crtc identifier |
||
273 | */ |
||
274 | // int (*get_pipe_from_crtc_id) (drm_intel_bufmgr *bufmgr, int crtc_id); |
||
275 | |||
276 | /** Returns true if target_bo is in the relocation tree rooted at bo. */ |
||
277 | int (*bo_references) (drm_intel_bo *bo, drm_intel_bo *target_bo); |
||
278 | |||
279 | /**< Enables verbose debugging printouts */ |
||
280 | int debug; |
||
281 | }; |
||
282 | |||
283 | struct _drm_intel_context { |
||
284 | unsigned int ctx_id; |
||
285 | struct _drm_intel_bufmgr *bufmgr; |
||
286 | }; |
||
287 | |||
288 | #define ALIGN(value, alignment) ((value + alignment - 1) & ~(alignment - 1)) |
||
289 | #define ROUND_UP_TO(x, y) (((x) + (y) - 1) / (y) * (y)) |
||
290 | #define ROUND_UP_TO_MB(x) ROUND_UP_TO((x), 1024*1024) |
||
291 | |||
292 | #endif /* INTEL_BUFMGR_PRIV_H */> |