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4363 Serge 1
/*
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 * Copyright © 2008-2012 Intel Corporation
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 *
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 * Permission is hereby granted, free of charge, to any person obtaining a
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 * copy of this software and associated documentation files (the "Software"),
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 * to deal in the Software without restriction, including without limitation
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 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
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 * and/or sell copies of the Software, and to permit persons to whom the
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 * Software is furnished to do so, subject to the following conditions:
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 *
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 * The above copyright notice and this permission notice (including the next
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 * paragraph) shall be included in all copies or substantial portions of the
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 * Software.
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 *
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 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
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 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
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 * IN THE SOFTWARE.
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 *
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 * Authors:
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 *    Eric Anholt 
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 *
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 */
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/**
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 * @file intel_bufmgr.h
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 *
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 * Public definitions of Intel-specific bufmgr functions.
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 */
33
 
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#ifndef INTEL_BUFMGR_H
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#define INTEL_BUFMGR_H
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#include 
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#include 
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#include 
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struct drm_clip_rect;
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typedef struct _drm_intel_bufmgr drm_intel_bufmgr;
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typedef struct _drm_intel_context drm_intel_context;
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typedef struct _drm_intel_bo drm_intel_bo;
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struct _drm_intel_bo {
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	/**
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	 * Size in bytes of the buffer object.
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	 *
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	 * The size may be larger than the size originally requested for the
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	 * allocation, such as being aligned to page size.
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	 */
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	unsigned long size;
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	/**
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	 * Alignment requirement for object
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	 *
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	 * Used for GTT mapping & pinning the object.
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	 */
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	unsigned long align;
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	/**
5068 serge 64
	 * Deprecated field containing (possibly the low 32-bits of) the last
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	 * seen virtual card address.  Use offset64 instead.
4363 Serge 66
	 */
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	unsigned long offset;
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	/**
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	 * Virtual address for accessing the buffer data.  Only valid while
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	 * mapped.
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	 */
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#ifdef __cplusplus
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	void *virt;
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#else
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	void *virtual;
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#endif
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	/** Buffer manager context associated with this buffer object */
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	drm_intel_bufmgr *bufmgr;
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	/**
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	 * MM-specific handle for accessing object
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	 */
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	int handle;
5068 serge 86
 
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	/**
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	 * Last seen card virtual address (offset from the beginning of the
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	 * aperture) for the object.  This should be used to fill relocation
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	 * entries when calling drm_intel_bo_emit_reloc()
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	 */
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	uint64_t offset64;
4363 Serge 93
};
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enum aub_dump_bmp_format {
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	AUB_DUMP_BMP_FORMAT_8BIT = 1,
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	AUB_DUMP_BMP_FORMAT_ARGB_4444 = 4,
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	AUB_DUMP_BMP_FORMAT_ARGB_0888 = 6,
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	AUB_DUMP_BMP_FORMAT_ARGB_8888 = 7,
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};
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typedef struct _drm_intel_aub_annotation {
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	uint32_t type;
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	uint32_t subtype;
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	uint32_t ending_offset;
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} drm_intel_aub_annotation;
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#define BO_ALLOC_FOR_RENDER (1<<0)
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drm_intel_bo *drm_intel_bo_alloc(drm_intel_bufmgr *bufmgr, const char *name,
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				 unsigned long size, unsigned int alignment);
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drm_intel_bo *drm_intel_bo_alloc_for_render(drm_intel_bufmgr *bufmgr,
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					    const char *name,
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					    unsigned long size,
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					    unsigned int alignment);
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drm_intel_bo *drm_intel_bo_alloc_tiled(drm_intel_bufmgr *bufmgr,
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				       const char *name,
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				       int x, int y, int cpp,
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				       uint32_t *tiling_mode,
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				       unsigned long *pitch,
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				       unsigned long flags);
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void drm_intel_bo_reference(drm_intel_bo *bo);
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void drm_intel_bo_unreference(drm_intel_bo *bo);
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int drm_intel_bo_map(drm_intel_bo *bo, int write_enable);
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int drm_intel_bo_unmap(drm_intel_bo *bo);
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int drm_intel_bo_subdata(drm_intel_bo *bo, unsigned long offset,
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			 unsigned long size, const void *data);
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int drm_intel_bo_get_subdata(drm_intel_bo *bo, unsigned long offset,
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			     unsigned long size, void *data);
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void drm_intel_bo_wait_rendering(drm_intel_bo *bo);
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void drm_intel_bufmgr_set_debug(drm_intel_bufmgr *bufmgr, int enable_debug);
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void drm_intel_bufmgr_destroy(drm_intel_bufmgr *bufmgr);
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int drm_intel_bo_exec(drm_intel_bo *bo, int used,
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		      struct drm_clip_rect *cliprects, int num_cliprects, int DR4);
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int drm_intel_bo_mrb_exec(drm_intel_bo *bo, int used,
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			struct drm_clip_rect *cliprects, int num_cliprects, int DR4,
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			unsigned int flags);
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int drm_intel_bufmgr_check_aperture_space(drm_intel_bo ** bo_array, int count);
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int drm_intel_bo_emit_reloc(drm_intel_bo *bo, uint32_t offset,
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			    drm_intel_bo *target_bo, uint32_t target_offset,
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			    uint32_t read_domains, uint32_t write_domain);
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int drm_intel_bo_emit_reloc_fence(drm_intel_bo *bo, uint32_t offset,
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				  drm_intel_bo *target_bo,
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				  uint32_t target_offset,
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				  uint32_t read_domains, uint32_t write_domain);
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int drm_intel_bo_pin(drm_intel_bo *bo, uint32_t alignment);
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int drm_intel_bo_unpin(drm_intel_bo *bo);
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int drm_intel_bo_set_tiling(drm_intel_bo *bo, uint32_t * tiling_mode,
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			    uint32_t stride);
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int drm_intel_bo_get_tiling(drm_intel_bo *bo, uint32_t * tiling_mode,
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			    uint32_t * swizzle_mode);
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int drm_intel_bo_flink(drm_intel_bo *bo, uint32_t * name);
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int drm_intel_bo_busy(drm_intel_bo *bo);
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int drm_intel_bo_madvise(drm_intel_bo *bo, int madv);
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int drm_intel_bo_disable_reuse(drm_intel_bo *bo);
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int drm_intel_bo_is_reusable(drm_intel_bo *bo);
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int drm_intel_bo_references(drm_intel_bo *bo, drm_intel_bo *target_bo);
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163
/* drm_intel_bufmgr_gem.c */
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drm_intel_bufmgr *drm_intel_bufmgr_gem_init(int fd, int batch_size);
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drm_intel_bo *drm_intel_bo_gem_create_from_name(drm_intel_bufmgr *bufmgr,
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						const char *name,
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						unsigned int handle);
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drm_intel_bo *
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bo_create_from_gem_handle(drm_intel_bufmgr *bufmgr,
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                          unsigned int size, unsigned int handle);
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void drm_intel_bufmgr_gem_enable_reuse(drm_intel_bufmgr *bufmgr);
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void drm_intel_bufmgr_gem_enable_fenced_relocs(drm_intel_bufmgr *bufmgr);
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void drm_intel_bufmgr_gem_set_vma_cache_size(drm_intel_bufmgr *bufmgr,
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					     int limit);
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int drm_intel_gem_bo_map_unsynchronized(drm_intel_bo *bo);
177
int drm_intel_gem_bo_map_gtt(drm_intel_bo *bo);
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int drm_intel_gem_bo_unmap_gtt(drm_intel_bo *bo);
179
 
180
int drm_intel_gem_bo_get_reloc_count(drm_intel_bo *bo);
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void drm_intel_gem_bo_clear_relocs(drm_intel_bo *bo, int start);
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void drm_intel_gem_bo_start_gtt_access(drm_intel_bo *bo, int write_enable);
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184
void
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drm_intel_bufmgr_gem_set_aub_filename(drm_intel_bufmgr *bufmgr,
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				      const char *filename);
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void drm_intel_bufmgr_gem_set_aub_dump(drm_intel_bufmgr *bufmgr, int enable);
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void drm_intel_gem_bo_aub_dump_bmp(drm_intel_bo *bo,
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				   int x1, int y1, int width, int height,
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				   enum aub_dump_bmp_format format,
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				   int pitch, int offset);
192
void
193
drm_intel_bufmgr_gem_set_aub_annotations(drm_intel_bo *bo,
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					 drm_intel_aub_annotation *annotations,
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					 unsigned count);
196
 
197
int drm_intel_get_pipe_from_crtc_id(drm_intel_bufmgr *bufmgr, int crtc_id);
198
 
199
int drm_intel_get_aperture_sizes(int fd, size_t *mappable, size_t *total);
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int drm_intel_bufmgr_gem_get_devid(drm_intel_bufmgr *bufmgr);
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int drm_intel_gem_bo_wait(drm_intel_bo *bo, int64_t timeout_ns);
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203
drm_intel_context *drm_intel_gem_context_create(drm_intel_bufmgr *bufmgr);
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void drm_intel_gem_context_destroy(drm_intel_context *ctx);
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int drm_intel_gem_bo_context_exec(drm_intel_bo *bo, drm_intel_context *ctx,
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				  int used, unsigned int flags);
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208
int drm_intel_bo_gem_export_to_prime(drm_intel_bo *bo, int *prime_fd);
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drm_intel_bo *drm_intel_bo_gem_create_from_prime(drm_intel_bufmgr *bufmgr,
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						int prime_fd, int size);
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212
/* drm_intel_bufmgr_fake.c */
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drm_intel_bufmgr *drm_intel_bufmgr_fake_init(int fd,
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					     unsigned long low_offset,
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					     void *low_virtual,
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					     unsigned long size,
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					     volatile unsigned int
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					     *last_dispatch);
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void drm_intel_bufmgr_fake_set_last_dispatch(drm_intel_bufmgr *bufmgr,
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					     volatile unsigned int
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					     *last_dispatch);
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void drm_intel_bufmgr_fake_set_exec_callback(drm_intel_bufmgr *bufmgr,
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					     int (*exec) (drm_intel_bo *bo,
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							  unsigned int used,
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							  void *priv),
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					     void *priv);
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void drm_intel_bufmgr_fake_set_fence_callback(drm_intel_bufmgr *bufmgr,
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					      unsigned int (*emit) (void *priv),
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					      void (*wait) (unsigned int fence,
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							    void *priv),
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					      void *priv);
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drm_intel_bo *drm_intel_bo_fake_alloc_static(drm_intel_bufmgr *bufmgr,
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					     const char *name,
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					     unsigned long offset,
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					     unsigned long size, void *virt);
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void drm_intel_bo_fake_disable_backing_store(drm_intel_bo *bo,
237
					     void (*invalidate_cb) (drm_intel_bo
238
								    * bo,
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								    void *ptr),
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					     void *ptr);
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242
void drm_intel_bufmgr_fake_contended_lock_take(drm_intel_bufmgr *bufmgr);
243
void drm_intel_bufmgr_fake_evict_all(drm_intel_bufmgr *bufmgr);
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245
struct drm_intel_decode *drm_intel_decode_context_alloc(uint32_t devid);
246
void drm_intel_decode_context_free(struct drm_intel_decode *ctx);
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void drm_intel_decode_set_batch_pointer(struct drm_intel_decode *ctx,
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					void *data, uint32_t hw_offset,
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					int count);
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void drm_intel_decode_set_dump_past_end(struct drm_intel_decode *ctx,
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					int dump_past_end);
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void drm_intel_decode_set_head_tail(struct drm_intel_decode *ctx,
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				    uint32_t head, uint32_t tail);
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void drm_intel_decode_set_output_file(struct drm_intel_decode *ctx, FILE *out);
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void drm_intel_decode(struct drm_intel_decode *ctx);
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257
int drm_intel_reg_read(drm_intel_bufmgr *bufmgr,
258
		       uint32_t offset,
259
		       uint64_t *result);
260
 
261
int drm_intel_get_reset_stats(drm_intel_context *ctx,
262
			      uint32_t *reset_count,
263
			      uint32_t *active,
264
			      uint32_t *pending);
265
 
266
/** @{ Compatibility defines to keep old code building despite the symbol rename
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 * from dri_* to drm_intel_*
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 */
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#define dri_bo drm_intel_bo
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#define dri_bufmgr drm_intel_bufmgr
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#define dri_bo_alloc drm_intel_bo_alloc
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#define dri_bo_reference drm_intel_bo_reference
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#define dri_bo_unreference drm_intel_bo_unreference
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#define dri_bo_map drm_intel_bo_map
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#define dri_bo_unmap drm_intel_bo_unmap
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#define dri_bo_subdata drm_intel_bo_subdata
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#define dri_bo_get_subdata drm_intel_bo_get_subdata
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#define dri_bo_wait_rendering drm_intel_bo_wait_rendering
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#define dri_bufmgr_set_debug drm_intel_bufmgr_set_debug
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#define dri_bufmgr_destroy drm_intel_bufmgr_destroy
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#define dri_bo_exec drm_intel_bo_exec
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#define dri_bufmgr_check_aperture_space drm_intel_bufmgr_check_aperture_space
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#define dri_bo_emit_reloc(reloc_bo, read, write, target_offset,		\
284
			  reloc_offset, target_bo)			\
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	drm_intel_bo_emit_reloc(reloc_bo, reloc_offset,			\
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				target_bo, target_offset,		\
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				read, write);
288
#define dri_bo_pin drm_intel_bo_pin
289
#define dri_bo_unpin drm_intel_bo_unpin
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#define dri_bo_get_tiling drm_intel_bo_get_tiling
291
#define dri_bo_set_tiling(bo, mode) drm_intel_bo_set_tiling(bo, mode, 0)
292
#define dri_bo_flink drm_intel_bo_flink
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#define intel_bufmgr_gem_init drm_intel_bufmgr_gem_init
294
#define intel_bo_gem_create_from_name drm_intel_bo_gem_create_from_name
295
#define intel_bufmgr_gem_enable_reuse drm_intel_bufmgr_gem_enable_reuse
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#define intel_bufmgr_fake_init drm_intel_bufmgr_fake_init
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#define intel_bufmgr_fake_set_last_dispatch drm_intel_bufmgr_fake_set_last_dispatch
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#define intel_bufmgr_fake_set_exec_callback drm_intel_bufmgr_fake_set_exec_callback
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#define intel_bufmgr_fake_set_fence_callback drm_intel_bufmgr_fake_set_fence_callback
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#define intel_bo_fake_alloc_static drm_intel_bo_fake_alloc_static
301
#define intel_bo_fake_disable_backing_store drm_intel_bo_fake_disable_backing_store
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#define intel_bufmgr_fake_contended_lock_take drm_intel_bufmgr_fake_contended_lock_take
303
#define intel_bufmgr_fake_evict_all drm_intel_bufmgr_fake_evict_all
304
 
305
/** @{ */
306
 
307
#endif /* INTEL_BUFMGR_H */