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4363 | Serge | 1 | /* |
2 | * Copyright © 2007 Intel Corporation |
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3 | * |
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4 | * Permission is hereby granted, free of charge, to any person obtaining a |
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5 | * copy of this software and associated documentation files (the "Software"), |
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6 | * to deal in the Software without restriction, including without limitation |
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7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
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8 | * and/or sell copies of the Software, and to permit persons to whom the |
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9 | * Software is furnished to do so, subject to the following conditions: |
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10 | * |
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11 | * The above copyright notice and this permission notice (including the next |
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12 | * paragraph) shall be included in all copies or substantial portions of the |
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13 | * Software. |
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14 | * |
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15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
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16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
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17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
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18 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER |
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19 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING |
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20 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS |
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21 | * IN THE SOFTWARE. |
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22 | * |
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23 | * Authors: |
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24 | * Eric Anholt |
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25 | * |
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26 | */ |
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27 | |||
28 | #ifdef HAVE_CONFIG_H |
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29 | #include "config.h" |
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30 | #endif |
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31 | |||
32 | #include |
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33 | #include |
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34 | #include |
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35 | #include |
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36 | #include |
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37 | #include |
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38 | #include |
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39 | //#include |
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40 | #include "intel_bufmgr.h" |
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41 | #include "intel_bufmgr_priv.h" |
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42 | #include "xf86drm.h" |
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43 | |||
44 | /** @file intel_bufmgr.c |
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45 | * |
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46 | * Convenience functions for buffer management methods. |
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47 | */ |
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48 | |||
49 | drm_intel_bo *drm_intel_bo_alloc(drm_intel_bufmgr *bufmgr, const char *name, |
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50 | unsigned long size, unsigned int alignment) |
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51 | { |
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52 | return bufmgr->bo_alloc(bufmgr, name, size, alignment); |
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53 | } |
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54 | |||
55 | #if 0 |
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56 | drm_intel_bo *drm_intel_bo_alloc_for_render(drm_intel_bufmgr *bufmgr, |
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57 | const char *name, |
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58 | unsigned long size, |
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59 | unsigned int alignment) |
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60 | { |
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61 | return bufmgr->bo_alloc_for_render(bufmgr, name, size, alignment); |
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62 | } |
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63 | #endif |
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64 | |||
65 | drm_intel_bo * |
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66 | drm_intel_bo_alloc_tiled(drm_intel_bufmgr *bufmgr, const char *name, |
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67 | int x, int y, int cpp, uint32_t *tiling_mode, |
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68 | unsigned long *pitch, unsigned long flags) |
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69 | { |
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70 | return bufmgr->bo_alloc_tiled(bufmgr, name, x, y, cpp, |
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71 | tiling_mode, pitch, flags); |
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72 | } |
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73 | |||
74 | void drm_intel_bo_reference(drm_intel_bo *bo) |
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75 | { |
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76 | bo->bufmgr->bo_reference(bo); |
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77 | } |
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78 | |||
79 | void drm_intel_bo_unreference(drm_intel_bo *bo) |
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80 | { |
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81 | if (bo == NULL) |
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82 | return; |
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83 | |||
84 | bo->bufmgr->bo_unreference(bo); |
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85 | } |
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86 | |||
87 | int drm_intel_bo_map(drm_intel_bo *buf, int write_enable) |
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88 | { |
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89 | return buf->bufmgr->bo_map(buf, write_enable); |
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90 | } |
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91 | |||
92 | int drm_intel_bo_unmap(drm_intel_bo *buf) |
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93 | { |
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94 | return buf->bufmgr->bo_unmap(buf); |
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95 | } |
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96 | |||
97 | int |
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98 | drm_intel_bo_subdata(drm_intel_bo *bo, unsigned long offset, |
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99 | unsigned long size, const void *data) |
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100 | { |
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101 | return bo->bufmgr->bo_subdata(bo, offset, size, data); |
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102 | } |
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103 | |||
104 | int |
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105 | drm_intel_bo_get_subdata(drm_intel_bo *bo, unsigned long offset, |
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106 | unsigned long size, void *data) |
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107 | { |
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108 | int ret; |
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109 | // if (bo->bufmgr->bo_get_subdata) |
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110 | // return bo->bufmgr->bo_get_subdata(bo, offset, size, data); |
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111 | |||
112 | if (size == 0 || data == NULL) |
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113 | return 0; |
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114 | |||
115 | ret = drm_intel_bo_map(bo, 0); |
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116 | if (ret) |
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117 | return ret; |
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118 | memcpy(data, (unsigned char *)bo->virtual + offset, size); |
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119 | drm_intel_bo_unmap(bo); |
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120 | return 0; |
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121 | } |
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122 | |||
123 | void drm_intel_bo_wait_rendering(drm_intel_bo *bo) |
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124 | { |
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125 | bo->bufmgr->bo_wait_rendering(bo); |
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126 | } |
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127 | |||
128 | void drm_intel_bufmgr_destroy(drm_intel_bufmgr *bufmgr) |
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129 | { |
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130 | bufmgr->destroy(bufmgr); |
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131 | } |
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132 | |||
133 | int |
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134 | drm_intel_bo_exec(drm_intel_bo *bo, int used, |
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135 | drm_clip_rect_t * cliprects, int num_cliprects, int DR4) |
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136 | { |
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137 | return bo->bufmgr->bo_exec(bo, used, cliprects, num_cliprects, DR4); |
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138 | } |
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139 | |||
140 | int |
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141 | drm_intel_bo_mrb_exec(drm_intel_bo *bo, int used, |
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142 | drm_clip_rect_t *cliprects, int num_cliprects, int DR4, |
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143 | unsigned int rings) |
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144 | { |
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145 | if (bo->bufmgr->bo_mrb_exec) |
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146 | return bo->bufmgr->bo_mrb_exec(bo, used, |
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147 | cliprects, num_cliprects, DR4, |
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148 | rings); |
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149 | |||
150 | switch (rings) { |
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151 | case I915_EXEC_DEFAULT: |
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152 | case I915_EXEC_RENDER: |
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153 | return bo->bufmgr->bo_exec(bo, used, |
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154 | cliprects, num_cliprects, DR4); |
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155 | default: |
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156 | return -ENODEV; |
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157 | } |
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158 | } |
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159 | |||
160 | void drm_intel_bufmgr_set_debug(drm_intel_bufmgr *bufmgr, int enable_debug) |
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161 | { |
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162 | bufmgr->debug = enable_debug; |
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163 | } |
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164 | |||
165 | int drm_intel_bufmgr_check_aperture_space(drm_intel_bo ** bo_array, int count) |
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166 | { |
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167 | return bo_array[0]->bufmgr->check_aperture_space(bo_array, count); |
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168 | } |
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169 | |||
170 | int drm_intel_bo_flink(drm_intel_bo *bo, uint32_t * name) |
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171 | { |
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172 | if (bo->bufmgr->bo_flink) |
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173 | return bo->bufmgr->bo_flink(bo, name); |
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174 | |||
175 | return -ENODEV; |
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176 | } |
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177 | |||
178 | int |
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179 | drm_intel_bo_emit_reloc(drm_intel_bo *bo, uint32_t offset, |
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180 | drm_intel_bo *target_bo, uint32_t target_offset, |
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181 | uint32_t read_domains, uint32_t write_domain) |
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182 | { |
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183 | return bo->bufmgr->bo_emit_reloc(bo, offset, |
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184 | target_bo, target_offset, |
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185 | read_domains, write_domain); |
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186 | } |
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187 | |||
188 | /* For fence registers, not GL fences */ |
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189 | int |
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190 | drm_intel_bo_emit_reloc_fence(drm_intel_bo *bo, uint32_t offset, |
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191 | drm_intel_bo *target_bo, uint32_t target_offset, |
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192 | uint32_t read_domains, uint32_t write_domain) |
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193 | { |
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194 | return bo->bufmgr->bo_emit_reloc_fence(bo, offset, |
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195 | target_bo, target_offset, |
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196 | read_domains, write_domain); |
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197 | } |
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198 | |||
199 | |||
200 | int drm_intel_bo_pin(drm_intel_bo *bo, uint32_t alignment) |
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201 | { |
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202 | if (bo->bufmgr->bo_pin) |
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203 | return bo->bufmgr->bo_pin(bo, alignment); |
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204 | |||
205 | return -ENODEV; |
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206 | } |
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207 | |||
208 | int drm_intel_bo_unpin(drm_intel_bo *bo) |
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209 | { |
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210 | if (bo->bufmgr->bo_unpin) |
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211 | return bo->bufmgr->bo_unpin(bo); |
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212 | |||
213 | return -ENODEV; |
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214 | } |
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215 | |||
216 | int drm_intel_bo_set_tiling(drm_intel_bo *bo, uint32_t * tiling_mode, |
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217 | uint32_t stride) |
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218 | { |
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219 | if (bo->bufmgr->bo_set_tiling) |
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220 | return bo->bufmgr->bo_set_tiling(bo, tiling_mode, stride); |
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221 | |||
222 | *tiling_mode = I915_TILING_NONE; |
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223 | return 0; |
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224 | } |
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225 | |||
226 | int drm_intel_bo_get_tiling(drm_intel_bo *bo, uint32_t * tiling_mode, |
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227 | uint32_t * swizzle_mode) |
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228 | { |
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229 | if (bo->bufmgr->bo_get_tiling) |
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230 | return bo->bufmgr->bo_get_tiling(bo, tiling_mode, swizzle_mode); |
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231 | |||
232 | *tiling_mode = I915_TILING_NONE; |
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233 | *swizzle_mode = I915_BIT_6_SWIZZLE_NONE; |
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234 | return 0; |
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235 | } |
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236 | |||
237 | int drm_intel_bo_disable_reuse(drm_intel_bo *bo) |
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238 | { |
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239 | if (bo->bufmgr->bo_disable_reuse) |
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240 | return bo->bufmgr->bo_disable_reuse(bo); |
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241 | return 0; |
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242 | } |
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243 | |||
244 | int drm_intel_bo_is_reusable(drm_intel_bo *bo) |
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245 | { |
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246 | if (bo->bufmgr->bo_is_reusable) |
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247 | return bo->bufmgr->bo_is_reusable(bo); |
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248 | return 0; |
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249 | } |
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250 | |||
251 | int drm_intel_bo_busy(drm_intel_bo *bo) |
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252 | { |
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253 | if (bo->bufmgr->bo_busy) |
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254 | return bo->bufmgr->bo_busy(bo); |
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255 | return 0; |
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256 | } |
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257 | |||
258 | int drm_intel_bo_madvise(drm_intel_bo *bo, int madv) |
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259 | { |
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260 | if (bo->bufmgr->bo_madvise) |
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261 | return bo->bufmgr->bo_madvise(bo, madv); |
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262 | return -1; |
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263 | } |
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264 | |||
265 | int drm_intel_bo_references(drm_intel_bo *bo, drm_intel_bo *target_bo) |
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266 | { |
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267 | return bo->bufmgr->bo_references(bo, target_bo); |
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268 | } |
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269 | |||
270 | |||
271 | |||
272 | #if 0 |
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273 | static size_t |
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274 | drm_intel_probe_agp_aperture_size(int fd) |
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275 | { |
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276 | struct pci_device *pci_dev; |
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277 | size_t size = 0; |
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278 | int ret; |
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279 | |||
280 | ret = pci_system_init(); |
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281 | if (ret) |
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282 | goto err; |
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283 | |||
284 | /* XXX handle multiple adaptors? */ |
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285 | pci_dev = pci_device_find_by_slot(0, 0, 2, 0); |
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286 | if (pci_dev == NULL) |
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287 | goto err; |
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288 | |||
289 | ret = pci_device_probe(pci_dev); |
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290 | if (ret) |
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291 | goto err; |
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292 | |||
293 | size = pci_dev->regions[2].size; |
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294 | err: |
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295 | pci_system_cleanup (); |
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296 | return size; |
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297 | } |
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298 | #endif |
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299 | |||
300 | int drm_intel_get_aperture_sizes(int fd, |
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301 | size_t *mappable, |
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302 | size_t *total) |
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303 | { |
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304 | |||
305 | struct drm_i915_gem_get_aperture aperture; |
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306 | int ret; |
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307 | |||
308 | ret = drmIoctl(fd, DRM_IOCTL_I915_GEM_GET_APERTURE, &aperture); |
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309 | if (ret) |
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310 | return ret; |
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311 | |||
312 | /* XXX add a query for the kernel value? */ |
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313 | *mappable = 512 * 1024 * 1024; /* minimum possible value */ |
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314 | *total = aperture.aper_size; |
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315 | return 0; |
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316 | } |