Rev 5368 | Rev 6110 | Go to most recent revision | Details | Compare with Previous | Last modification | View Log | RSS feed
Rev | Author | Line No. | Line |
---|---|---|---|
4363 | Serge | 1 | /* |
2 | * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas. |
||
3 | * All Rights Reserved. |
||
4 | * |
||
5 | * Permission is hereby granted, free of charge, to any person obtaining a |
||
6 | * copy of this software and associated documentation files (the |
||
7 | * "Software"), to deal in the Software without restriction, including |
||
8 | * without limitation the rights to use, copy, modify, merge, publish, |
||
9 | * distribute, sub license, and/or sell copies of the Software, and to |
||
10 | * permit persons to whom the Software is furnished to do so, subject to |
||
11 | * the following conditions: |
||
12 | * |
||
13 | * The above copyright notice and this permission notice (including the |
||
14 | * next paragraph) shall be included in all copies or substantial portions |
||
15 | * of the Software. |
||
16 | * |
||
17 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS |
||
18 | * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF |
||
19 | * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. |
||
20 | * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR |
||
21 | * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, |
||
22 | * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE |
||
23 | * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. |
||
24 | * |
||
25 | */ |
||
26 | |||
27 | #ifndef _I915_DRM_H_ |
||
28 | #define _I915_DRM_H_ |
||
29 | |||
30 | #include "drm.h" |
||
31 | |||
32 | /* Please note that modifications to all structs defined here are |
||
33 | * subject to backwards-compatibility constraints. |
||
34 | */ |
||
35 | |||
5022 | Serge | 36 | /** |
37 | * DOC: uevents generated by i915 on it's device node |
||
38 | * |
||
39 | * I915_L3_PARITY_UEVENT - Generated when the driver receives a parity mismatch |
||
40 | * event from the gpu l3 cache. Additional information supplied is ROW, |
||
41 | * BANK, SUBBANK, SLICE of the affected cacheline. Userspace should keep |
||
42 | * track of these events and if a specific cache-line seems to have a |
||
43 | * persistent error remap it with the l3 remapping tool supplied in |
||
44 | * intel-gpu-tools. The value supplied with the event is always 1. |
||
45 | * |
||
46 | * I915_ERROR_UEVENT - Generated upon error detection, currently only via |
||
47 | * hangcheck. The error detection event is a good indicator of when things |
||
48 | * began to go badly. The value supplied with the event is a 1 upon error |
||
49 | * detection, and a 0 upon reset completion, signifying no more error |
||
50 | * exists. NOTE: Disabling hangcheck or reset via module parameter will |
||
51 | * cause the related events to not be seen. |
||
52 | * |
||
53 | * I915_RESET_UEVENT - Event is generated just before an attempt to reset the |
||
54 | * the GPU. The value supplied with the event is always 1. NOTE: Disable |
||
55 | * reset via module parameter will cause this event to not be seen. |
||
56 | */ |
||
57 | #define I915_L3_PARITY_UEVENT "L3_PARITY_ERROR" |
||
58 | #define I915_ERROR_UEVENT "ERROR" |
||
59 | #define I915_RESET_UEVENT "RESET" |
||
4363 | Serge | 60 | |
61 | /* Each region is a minimum of 16k, and there are at most 255 of them. |
||
62 | */ |
||
63 | #define I915_NR_TEX_REGIONS 255 /* table size 2k - maximum due to use |
||
64 | * of chars for next/prev indices */ |
||
65 | #define I915_LOG_MIN_TEX_REGION_SIZE 14 |
||
66 | |||
67 | typedef struct _drm_i915_init { |
||
68 | enum { |
||
69 | I915_INIT_DMA = 0x01, |
||
70 | I915_CLEANUP_DMA = 0x02, |
||
71 | I915_RESUME_DMA = 0x03 |
||
72 | } func; |
||
73 | unsigned int mmio_offset; |
||
74 | int sarea_priv_offset; |
||
75 | unsigned int ring_start; |
||
76 | unsigned int ring_end; |
||
77 | unsigned int ring_size; |
||
78 | unsigned int front_offset; |
||
79 | unsigned int back_offset; |
||
80 | unsigned int depth_offset; |
||
81 | unsigned int w; |
||
82 | unsigned int h; |
||
83 | unsigned int pitch; |
||
84 | unsigned int pitch_bits; |
||
85 | unsigned int back_pitch; |
||
86 | unsigned int depth_pitch; |
||
87 | unsigned int cpp; |
||
88 | unsigned int chipset; |
||
89 | } drm_i915_init_t; |
||
90 | |||
91 | typedef struct _drm_i915_sarea { |
||
92 | struct drm_tex_region texList[I915_NR_TEX_REGIONS + 1]; |
||
93 | int last_upload; /* last time texture was uploaded */ |
||
94 | int last_enqueue; /* last time a buffer was enqueued */ |
||
95 | int last_dispatch; /* age of the most recently dispatched buffer */ |
||
96 | int ctxOwner; /* last context to upload state */ |
||
97 | int texAge; |
||
98 | int pf_enabled; /* is pageflipping allowed? */ |
||
99 | int pf_active; |
||
100 | int pf_current_page; /* which buffer is being displayed? */ |
||
101 | int perf_boxes; /* performance boxes to be displayed */ |
||
102 | int width, height; /* screen size in pixels */ |
||
103 | |||
104 | drm_handle_t front_handle; |
||
105 | int front_offset; |
||
106 | int front_size; |
||
107 | |||
108 | drm_handle_t back_handle; |
||
109 | int back_offset; |
||
110 | int back_size; |
||
111 | |||
112 | drm_handle_t depth_handle; |
||
113 | int depth_offset; |
||
114 | int depth_size; |
||
115 | |||
116 | drm_handle_t tex_handle; |
||
117 | int tex_offset; |
||
118 | int tex_size; |
||
119 | int log_tex_granularity; |
||
120 | int pitch; |
||
121 | int rotation; /* 0, 90, 180 or 270 */ |
||
122 | int rotated_offset; |
||
123 | int rotated_size; |
||
124 | int rotated_pitch; |
||
125 | int virtualX, virtualY; |
||
126 | |||
127 | unsigned int front_tiled; |
||
128 | unsigned int back_tiled; |
||
129 | unsigned int depth_tiled; |
||
130 | unsigned int rotated_tiled; |
||
131 | unsigned int rotated2_tiled; |
||
132 | |||
133 | int pipeA_x; |
||
134 | int pipeA_y; |
||
135 | int pipeA_w; |
||
136 | int pipeA_h; |
||
137 | int pipeB_x; |
||
138 | int pipeB_y; |
||
139 | int pipeB_w; |
||
140 | int pipeB_h; |
||
141 | |||
142 | /* fill out some space for old userspace triple buffer */ |
||
143 | drm_handle_t unused_handle; |
||
144 | __u32 unused1, unused2, unused3; |
||
145 | |||
146 | /* buffer object handles for static buffers. May change |
||
147 | * over the lifetime of the client. |
||
148 | */ |
||
149 | __u32 front_bo_handle; |
||
150 | __u32 back_bo_handle; |
||
151 | __u32 unused_bo_handle; |
||
152 | __u32 depth_bo_handle; |
||
153 | |||
154 | } drm_i915_sarea_t; |
||
155 | |||
156 | /* due to userspace building against these headers we need some compat here */ |
||
157 | #define planeA_x pipeA_x |
||
158 | #define planeA_y pipeA_y |
||
159 | #define planeA_w pipeA_w |
||
160 | #define planeA_h pipeA_h |
||
161 | #define planeB_x pipeB_x |
||
162 | #define planeB_y pipeB_y |
||
163 | #define planeB_w pipeB_w |
||
164 | #define planeB_h pipeB_h |
||
165 | |||
166 | /* Flags for perf_boxes |
||
167 | */ |
||
4502 | Serge | 168 | #define I915_BOX_RING_EMPTY 0x1 |
169 | #define I915_BOX_FLIP 0x2 |
||
170 | #define I915_BOX_WAIT 0x4 |
||
171 | #define I915_BOX_TEXTURE_LOAD 0x8 |
||
172 | #define I915_BOX_LOST_CONTEXT 0x10 |
||
4363 | Serge | 173 | |
174 | /* I915 specific ioctls |
||
175 | * The device specific ioctl range is 0x40 to 0x79. |
||
176 | */ |
||
4502 | Serge | 177 | #define DRM_I915_INIT 0x00 |
178 | #define DRM_I915_FLUSH 0x01 |
||
179 | #define DRM_I915_FLIP 0x02 |
||
180 | #define DRM_I915_BATCHBUFFER 0x03 |
||
181 | #define DRM_I915_IRQ_EMIT 0x04 |
||
182 | #define DRM_I915_IRQ_WAIT 0x05 |
||
183 | #define DRM_I915_GETPARAM 0x06 |
||
184 | #define DRM_I915_SETPARAM 0x07 |
||
185 | #define DRM_I915_ALLOC 0x08 |
||
186 | #define DRM_I915_FREE 0x09 |
||
187 | #define DRM_I915_INIT_HEAP 0x0a |
||
188 | #define DRM_I915_CMDBUFFER 0x0b |
||
189 | #define DRM_I915_DESTROY_HEAP 0x0c |
||
4363 | Serge | 190 | #define DRM_I915_SET_VBLANK_PIPE 0x0d |
191 | #define DRM_I915_GET_VBLANK_PIPE 0x0e |
||
4502 | Serge | 192 | #define DRM_I915_VBLANK_SWAP 0x0f |
193 | #define DRM_I915_HWS_ADDR 0x11 |
||
194 | #define DRM_I915_GEM_INIT 0x13 |
||
195 | #define DRM_I915_GEM_EXECBUFFER 0x14 |
||
196 | #define DRM_I915_GEM_PIN 0x15 |
||
197 | #define DRM_I915_GEM_UNPIN 0x16 |
||
198 | #define DRM_I915_GEM_BUSY 0x17 |
||
199 | #define DRM_I915_GEM_THROTTLE 0x18 |
||
200 | #define DRM_I915_GEM_ENTERVT 0x19 |
||
201 | #define DRM_I915_GEM_LEAVEVT 0x1a |
||
202 | #define DRM_I915_GEM_CREATE 0x1b |
||
203 | #define DRM_I915_GEM_PREAD 0x1c |
||
204 | #define DRM_I915_GEM_PWRITE 0x1d |
||
205 | #define DRM_I915_GEM_MMAP 0x1e |
||
206 | #define DRM_I915_GEM_SET_DOMAIN 0x1f |
||
207 | #define DRM_I915_GEM_SW_FINISH 0x20 |
||
208 | #define DRM_I915_GEM_SET_TILING 0x21 |
||
209 | #define DRM_I915_GEM_GET_TILING 0x22 |
||
210 | #define DRM_I915_GEM_GET_APERTURE 0x23 |
||
211 | #define DRM_I915_GEM_MMAP_GTT 0x24 |
||
4363 | Serge | 212 | #define DRM_I915_GET_PIPE_FROM_CRTC_ID 0x25 |
4502 | Serge | 213 | #define DRM_I915_GEM_MADVISE 0x26 |
4363 | Serge | 214 | #define DRM_I915_OVERLAY_PUT_IMAGE 0x27 |
4502 | Serge | 215 | #define DRM_I915_OVERLAY_ATTRS 0x28 |
4363 | Serge | 216 | #define DRM_I915_GEM_EXECBUFFER2 0x29 |
217 | #define DRM_I915_GET_SPRITE_COLORKEY 0x2a |
||
218 | #define DRM_I915_SET_SPRITE_COLORKEY 0x2b |
||
4502 | Serge | 219 | #define DRM_I915_GEM_WAIT 0x2c |
4363 | Serge | 220 | #define DRM_I915_GEM_CONTEXT_CREATE 0x2d |
221 | #define DRM_I915_GEM_CONTEXT_DESTROY 0x2e |
||
5022 | Serge | 222 | #define DRM_I915_GEM_SET_CACHING 0x2f |
223 | #define DRM_I915_GEM_GET_CACHING 0x30 |
||
4363 | Serge | 224 | #define DRM_I915_REG_READ 0x31 |
225 | #define DRM_I915_GET_RESET_STATS 0x32 |
||
5068 | serge | 226 | #define DRM_I915_GEM_USERPTR 0x33 |
4363 | Serge | 227 | |
228 | #define DRM_IOCTL_I915_INIT |
||
229 | #define DRM_IOCTL_I915_FLUSH |
||
230 | #define DRM_IOCTL_I915_FLIP |
||
231 | #define DRM_IOCTL_I915_BATCHBUFFER |
||
232 | #define DRM_IOCTL_I915_IRQ_EMIT |
||
233 | #define DRM_IOCTL_I915_IRQ_WAIT |
||
234 | #define DRM_IOCTL_I915_GETPARAM SRV_I915_GET_PARAM |
||
235 | #define DRM_IOCTL_I915_SETPARAM |
||
236 | #define DRM_IOCTL_I915_ALLOC |
||
237 | #define DRM_IOCTL_I915_FREE |
||
238 | #define DRM_IOCTL_I915_INIT_HEAP |
||
239 | #define DRM_IOCTL_I915_CMDBUFFER |
||
240 | #define DRM_IOCTL_I915_DESTROY_HEAP |
||
241 | #define DRM_IOCTL_I915_SET_VBLANK_PIPE |
||
242 | #define DRM_IOCTL_I915_GET_VBLANK_PIPE |
||
243 | #define DRM_IOCTL_I915_VBLANK_SWAP |
||
244 | #define DRM_IOCTL_I915_HWS_ADDR |
||
245 | #define DRM_IOCTL_I915_GEM_INIT |
||
246 | #define DRM_IOCTL_I915_GEM_EXECBUFFER |
||
247 | #define DRM_IOCTL_I915_GEM_EXECBUFFER2 SRV_I915_GEM_EXECBUFFER2 |
||
248 | #define DRM_IOCTL_I915_GEM_PIN SRV_I915_GEM_PIN |
||
249 | #define DRM_IOCTL_I915_GEM_UNPIN SRV_I915_GEM_UNPIN |
||
250 | #define DRM_IOCTL_I915_GEM_BUSY SRV_I915_GEM_BUSY |
||
251 | #define DRM_IOCTL_I915_GEM_SET_CACHEING SRV_I915_GEM_SET_CACHING |
||
5368 | serge | 252 | #define DRM_IOCTL_I915_GEM_GET_CACHEING SRV_I915_GEM_GET_CACHING |
4363 | Serge | 253 | #define DRM_IOCTL_I915_GEM_THROTTLE SRV_I915_GEM_THROTTLE |
254 | #define DRM_IOCTL_I915_GEM_ENTERVT |
||
255 | #define DRM_IOCTL_I915_GEM_LEAVEVT |
||
256 | #define DRM_IOCTL_I915_GEM_CREATE SRV_I915_GEM_CREATE |
||
257 | #define DRM_IOCTL_I915_GEM_PREAD |
||
258 | #define DRM_IOCTL_I915_GEM_PWRITE SRV_I915_GEM_PWRITE |
||
259 | #define DRM_IOCTL_I915_GEM_MMAP SRV_I915_GEM_MMAP |
||
260 | #define DRM_IOCTL_I915_GEM_MMAP_GTT SRV_I915_GEM_MMAP_GTT |
||
261 | #define DRM_IOCTL_I915_GEM_SET_DOMAIN SRV_I915_GEM_SET_DOMAIN |
||
262 | #define DRM_IOCTL_I915_GEM_SW_FINISH |
||
263 | #define DRM_IOCTL_I915_GEM_SET_TILING SRV_I915_GEM_SET_TILING |
||
264 | #define DRM_IOCTL_I915_GEM_GET_TILING SRV_I915_GEM_GET_TILING |
||
265 | #define DRM_IOCTL_I915_GEM_GET_APERTURE SRV_I915_GEM_GET_APERTURE |
||
266 | #define DRM_IOCTL_I915_GET_PIPE_FROM_CRTC_ID |
||
267 | #define DRM_IOCTL_I915_GEM_MADVISE |
||
268 | #define DRM_IOCTL_I915_OVERLAY_PUT_IMAGE |
||
269 | #define DRM_IOCTL_I915_OVERLAY_ATTRS |
||
270 | #define DRM_IOCTL_I915_SET_SPRITE_COLORKEY |
||
271 | #define DRM_IOCTL_I915_GET_SPRITE_COLORKEY |
||
272 | #define DRM_IOCTL_I915_GEM_WAIT SRV_I915_GEM_WAIT |
||
273 | #define DRM_IOCTL_I915_GEM_CONTEXT_CREATE SRV_I915_GEM_CONTEXT_CREATE |
||
274 | #define DRM_IOCTL_I915_GEM_CONTEXT_DESTROY SRV_I915_GEM_CONTEXT_DESTROY |
||
275 | #define DRM_IOCTL_I915_REG_READ SRV_I915_REG_READ |
||
276 | |||
277 | |||
278 | /* Allow drivers to submit batchbuffers directly to hardware, relying |
||
279 | * on the security mechanisms provided by hardware. |
||
280 | */ |
||
281 | typedef struct drm_i915_batchbuffer { |
||
282 | int start; /* agp offset */ |
||
283 | int used; /* nr bytes in use */ |
||
284 | int DR1; /* hw flags for GFX_OP_DRAWRECT_INFO */ |
||
285 | int DR4; /* window origin for GFX_OP_DRAWRECT_INFO */ |
||
286 | int num_cliprects; /* mulitpass with multiple cliprects? */ |
||
287 | struct drm_clip_rect *cliprects; /* pointer to userspace cliprects */ |
||
288 | } drm_i915_batchbuffer_t; |
||
289 | |||
290 | /* As above, but pass a pointer to userspace buffer which can be |
||
291 | * validated by the kernel prior to sending to hardware. |
||
292 | */ |
||
293 | typedef struct _drm_i915_cmdbuffer { |
||
294 | char *buf; /* pointer to userspace command buffer */ |
||
295 | int sz; /* nr bytes in buf */ |
||
296 | int DR1; /* hw flags for GFX_OP_DRAWRECT_INFO */ |
||
297 | int DR4; /* window origin for GFX_OP_DRAWRECT_INFO */ |
||
298 | int num_cliprects; /* mulitpass with multiple cliprects? */ |
||
299 | struct drm_clip_rect *cliprects; /* pointer to userspace cliprects */ |
||
300 | } drm_i915_cmdbuffer_t; |
||
301 | |||
302 | /* Userspace can request & wait on irq's: |
||
303 | */ |
||
304 | typedef struct drm_i915_irq_emit { |
||
305 | int *irq_seq; |
||
306 | } drm_i915_irq_emit_t; |
||
307 | |||
308 | typedef struct drm_i915_irq_wait { |
||
309 | int irq_seq; |
||
310 | } drm_i915_irq_wait_t; |
||
311 | |||
312 | /* Ioctl to query kernel params: |
||
313 | */ |
||
314 | #define I915_PARAM_IRQ_ACTIVE 1 |
||
315 | #define I915_PARAM_ALLOW_BATCHBUFFER 2 |
||
316 | #define I915_PARAM_LAST_DISPATCH 3 |
||
317 | #define I915_PARAM_CHIPSET_ID 4 |
||
318 | #define I915_PARAM_HAS_GEM 5 |
||
319 | #define I915_PARAM_NUM_FENCES_AVAIL 6 |
||
320 | #define I915_PARAM_HAS_OVERLAY 7 |
||
321 | #define I915_PARAM_HAS_PAGEFLIPPING 8 |
||
322 | #define I915_PARAM_HAS_EXECBUF2 9 |
||
323 | #define I915_PARAM_HAS_BSD 10 |
||
324 | #define I915_PARAM_HAS_BLT 11 |
||
325 | #define I915_PARAM_HAS_RELAXED_FENCING 12 |
||
326 | #define I915_PARAM_HAS_COHERENT_RINGS 13 |
||
327 | #define I915_PARAM_HAS_EXEC_CONSTANTS 14 |
||
328 | #define I915_PARAM_HAS_RELAXED_DELTA 15 |
||
329 | #define I915_PARAM_HAS_GEN7_SOL_RESET 16 |
||
330 | #define I915_PARAM_HAS_LLC 17 |
||
331 | #define I915_PARAM_HAS_ALIASING_PPGTT 18 |
||
332 | #define I915_PARAM_HAS_WAIT_TIMEOUT 19 |
||
5022 | Serge | 333 | #define I915_PARAM_HAS_SEMAPHORES 20 |
334 | #define I915_PARAM_HAS_PRIME_VMAP_FLUSH 21 |
||
4363 | Serge | 335 | #define I915_PARAM_HAS_VEBOX 22 |
5022 | Serge | 336 | #define I915_PARAM_HAS_SECURE_BATCHES 23 |
337 | #define I915_PARAM_HAS_PINNED_BATCHES 24 |
||
338 | #define I915_PARAM_HAS_EXEC_NO_RELOC 25 |
||
339 | #define I915_PARAM_HAS_EXEC_HANDLE_LUT 26 |
||
340 | #define I915_PARAM_HAS_WT 27 |
||
341 | #define I915_PARAM_CMD_PARSER_VERSION 28 |
||
5368 | serge | 342 | #define I915_PARAM_HAS_COHERENT_PHYS_GTT 29 |
4363 | Serge | 343 | |
344 | typedef struct drm_i915_getparam { |
||
345 | int param; |
||
346 | int *value; |
||
347 | } drm_i915_getparam_t; |
||
348 | |||
349 | /* Ioctl to set kernel params: |
||
350 | */ |
||
351 | #define I915_SETPARAM_USE_MI_BATCHBUFFER_START 1 |
||
352 | #define I915_SETPARAM_TEX_LRU_LOG_GRANULARITY 2 |
||
353 | #define I915_SETPARAM_ALLOW_BATCHBUFFER 3 |
||
354 | #define I915_SETPARAM_NUM_USED_FENCES 4 |
||
355 | |||
356 | typedef struct drm_i915_setparam { |
||
357 | int param; |
||
358 | int value; |
||
359 | } drm_i915_setparam_t; |
||
360 | |||
361 | /* A memory manager for regions of shared memory: |
||
362 | */ |
||
363 | #define I915_MEM_REGION_AGP 1 |
||
364 | |||
365 | typedef struct drm_i915_mem_alloc { |
||
366 | int region; |
||
367 | int alignment; |
||
368 | int size; |
||
369 | int *region_offset; /* offset from start of fb or agp */ |
||
370 | } drm_i915_mem_alloc_t; |
||
371 | |||
372 | typedef struct drm_i915_mem_free { |
||
373 | int region; |
||
374 | int region_offset; |
||
375 | } drm_i915_mem_free_t; |
||
376 | |||
377 | typedef struct drm_i915_mem_init_heap { |
||
378 | int region; |
||
379 | int size; |
||
380 | int start; |
||
381 | } drm_i915_mem_init_heap_t; |
||
382 | |||
383 | /* Allow memory manager to be torn down and re-initialized (eg on |
||
384 | * rotate): |
||
385 | */ |
||
386 | typedef struct drm_i915_mem_destroy_heap { |
||
387 | int region; |
||
388 | } drm_i915_mem_destroy_heap_t; |
||
389 | |||
390 | /* Allow X server to configure which pipes to monitor for vblank signals |
||
391 | */ |
||
392 | #define DRM_I915_VBLANK_PIPE_A 1 |
||
393 | #define DRM_I915_VBLANK_PIPE_B 2 |
||
394 | |||
395 | typedef struct drm_i915_vblank_pipe { |
||
396 | int pipe; |
||
397 | } drm_i915_vblank_pipe_t; |
||
398 | |||
399 | /* Schedule buffer swap at given vertical blank: |
||
400 | */ |
||
401 | typedef struct drm_i915_vblank_swap { |
||
402 | drm_drawable_t drawable; |
||
403 | enum drm_vblank_seq_type seqtype; |
||
404 | unsigned int sequence; |
||
405 | } drm_i915_vblank_swap_t; |
||
406 | |||
407 | typedef struct drm_i915_hws_addr { |
||
408 | __u64 addr; |
||
409 | } drm_i915_hws_addr_t; |
||
410 | |||
411 | struct drm_i915_gem_init { |
||
412 | /** |
||
413 | * Beginning offset in the GTT to be managed by the DRM memory |
||
414 | * manager. |
||
415 | */ |
||
416 | __u64 gtt_start; |
||
417 | /** |
||
418 | * Ending offset in the GTT to be managed by the DRM memory |
||
419 | * manager. |
||
420 | */ |
||
421 | __u64 gtt_end; |
||
422 | }; |
||
423 | |||
424 | struct drm_i915_gem_create { |
||
425 | /** |
||
426 | * Requested size for the object. |
||
427 | * |
||
428 | * The (page-aligned) allocated size for the object will be returned. |
||
429 | */ |
||
430 | __u64 size; |
||
431 | /** |
||
432 | * Returned handle for the object. |
||
433 | * |
||
434 | * Object handles are nonzero. |
||
435 | */ |
||
436 | __u32 handle; |
||
437 | __u32 pad; |
||
438 | }; |
||
439 | |||
440 | struct drm_i915_gem_pread { |
||
441 | /** Handle for the object being read. */ |
||
442 | __u32 handle; |
||
443 | __u32 pad; |
||
444 | /** Offset into the object to read from */ |
||
445 | __u64 offset; |
||
446 | /** Length of data to read */ |
||
447 | __u64 size; |
||
448 | /** |
||
449 | * Pointer to write the data into. |
||
450 | * |
||
451 | * This is a fixed-size type for 32/64 compatibility. |
||
452 | */ |
||
453 | __u64 data_ptr; |
||
454 | }; |
||
455 | |||
456 | struct drm_i915_gem_pwrite { |
||
457 | /** Handle for the object being written to. */ |
||
458 | __u32 handle; |
||
459 | __u32 pad; |
||
460 | /** Offset into the object to write to */ |
||
461 | __u64 offset; |
||
462 | /** Length of data to write */ |
||
463 | __u64 size; |
||
464 | /** |
||
465 | * Pointer to read the data from. |
||
466 | * |
||
467 | * This is a fixed-size type for 32/64 compatibility. |
||
468 | */ |
||
469 | __u64 data_ptr; |
||
470 | }; |
||
471 | |||
472 | struct drm_i915_gem_mmap { |
||
473 | /** Handle for the object being mapped. */ |
||
474 | __u32 handle; |
||
475 | __u32 pad; |
||
476 | /** Offset in the object to map. */ |
||
477 | __u64 offset; |
||
478 | /** |
||
479 | * Length of data to map. |
||
480 | * |
||
481 | * The value will be page-aligned. |
||
482 | */ |
||
483 | __u64 size; |
||
484 | /** |
||
485 | * Returned pointer the data was mapped at. |
||
486 | * |
||
487 | * This is a fixed-size type for 32/64 compatibility. |
||
488 | */ |
||
489 | __u64 addr_ptr; |
||
490 | }; |
||
491 | |||
492 | struct drm_i915_gem_mmap_gtt { |
||
493 | /** Handle for the object being mapped. */ |
||
494 | __u32 handle; |
||
495 | __u32 pad; |
||
496 | /** |
||
497 | * Fake offset to use for subsequent mmap call |
||
498 | * |
||
499 | * This is a fixed-size type for 32/64 compatibility. |
||
500 | */ |
||
501 | __u64 offset; |
||
502 | }; |
||
503 | |||
504 | struct drm_i915_gem_set_domain { |
||
505 | /** Handle for the object */ |
||
506 | __u32 handle; |
||
507 | |||
508 | /** New read domains */ |
||
509 | __u32 read_domains; |
||
510 | |||
511 | /** New write domain */ |
||
512 | __u32 write_domain; |
||
513 | }; |
||
514 | |||
515 | struct drm_i915_gem_sw_finish { |
||
516 | /** Handle for the object */ |
||
517 | __u32 handle; |
||
518 | }; |
||
519 | |||
520 | struct drm_i915_gem_relocation_entry { |
||
521 | /** |
||
522 | * Handle of the buffer being pointed to by this relocation entry. |
||
523 | * |
||
524 | * It's appealing to make this be an index into the mm_validate_entry |
||
525 | * list to refer to the buffer, but this allows the driver to create |
||
526 | * a relocation list for state buffers and not re-write it per |
||
527 | * exec using the buffer. |
||
528 | */ |
||
529 | __u32 target_handle; |
||
530 | |||
531 | /** |
||
532 | * Value to be added to the offset of the target buffer to make up |
||
533 | * the relocation entry. |
||
534 | */ |
||
535 | __u32 delta; |
||
536 | |||
537 | /** Offset in the buffer the relocation entry will be written into */ |
||
538 | __u64 offset; |
||
539 | |||
540 | /** |
||
541 | * Offset value of the target buffer that the relocation entry was last |
||
542 | * written as. |
||
543 | * |
||
544 | * If the buffer has the same offset as last time, we can skip syncing |
||
545 | * and writing the relocation. This value is written back out by |
||
546 | * the execbuffer ioctl when the relocation is written. |
||
547 | */ |
||
548 | __u64 presumed_offset; |
||
549 | |||
550 | /** |
||
551 | * Target memory domains read by this operation. |
||
552 | */ |
||
553 | __u32 read_domains; |
||
554 | |||
555 | /** |
||
556 | * Target memory domains written by this operation. |
||
557 | * |
||
558 | * Note that only one domain may be written by the whole |
||
559 | * execbuffer operation, so that where there are conflicts, |
||
560 | * the application will get -EINVAL back. |
||
561 | */ |
||
562 | __u32 write_domain; |
||
563 | }; |
||
564 | |||
565 | /** @{ |
||
566 | * Intel memory domains |
||
567 | * |
||
568 | * Most of these just align with the various caches in |
||
569 | * the system and are used to flush and invalidate as |
||
570 | * objects end up cached in different domains. |
||
571 | */ |
||
572 | /** CPU cache */ |
||
573 | #define I915_GEM_DOMAIN_CPU 0x00000001 |
||
574 | /** Render cache, used by 2D and 3D drawing */ |
||
575 | #define I915_GEM_DOMAIN_RENDER 0x00000002 |
||
576 | /** Sampler cache, used by texture engine */ |
||
577 | #define I915_GEM_DOMAIN_SAMPLER 0x00000004 |
||
578 | /** Command queue, used to load batch buffers */ |
||
579 | #define I915_GEM_DOMAIN_COMMAND 0x00000008 |
||
580 | /** Instruction cache, used by shader programs */ |
||
581 | #define I915_GEM_DOMAIN_INSTRUCTION 0x00000010 |
||
582 | /** Vertex address cache */ |
||
583 | #define I915_GEM_DOMAIN_VERTEX 0x00000020 |
||
584 | /** GTT domain - aperture and scanout */ |
||
585 | #define I915_GEM_DOMAIN_GTT 0x00000040 |
||
586 | /** @} */ |
||
587 | |||
588 | struct drm_i915_gem_exec_object { |
||
589 | /** |
||
590 | * User's handle for a buffer to be bound into the GTT for this |
||
591 | * operation. |
||
592 | */ |
||
593 | __u32 handle; |
||
594 | |||
595 | /** Number of relocations to be performed on this buffer */ |
||
596 | __u32 relocation_count; |
||
597 | /** |
||
598 | * Pointer to array of struct drm_i915_gem_relocation_entry containing |
||
599 | * the relocations to be performed in this buffer. |
||
600 | */ |
||
601 | __u64 relocs_ptr; |
||
602 | |||
603 | /** Required alignment in graphics aperture */ |
||
604 | __u64 alignment; |
||
605 | |||
606 | /** |
||
607 | * Returned value of the updated offset of the object, for future |
||
608 | * presumed_offset writes. |
||
609 | */ |
||
610 | __u64 offset; |
||
611 | }; |
||
612 | |||
613 | struct drm_i915_gem_execbuffer { |
||
614 | /** |
||
615 | * List of buffers to be validated with their relocations to be |
||
616 | * performend on them. |
||
617 | * |
||
618 | * This is a pointer to an array of struct drm_i915_gem_validate_entry. |
||
619 | * |
||
620 | * These buffers must be listed in an order such that all relocations |
||
621 | * a buffer is performing refer to buffers that have already appeared |
||
622 | * in the validate list. |
||
623 | */ |
||
624 | __u64 buffers_ptr; |
||
625 | __u32 buffer_count; |
||
626 | |||
627 | /** Offset in the batchbuffer to start execution from. */ |
||
628 | __u32 batch_start_offset; |
||
629 | /** Bytes used in batchbuffer from batch_start_offset */ |
||
630 | __u32 batch_len; |
||
631 | __u32 DR1; |
||
632 | __u32 DR4; |
||
633 | __u32 num_cliprects; |
||
634 | /** This is a struct drm_clip_rect *cliprects */ |
||
635 | __u64 cliprects_ptr; |
||
636 | }; |
||
637 | |||
638 | struct drm_i915_gem_exec_object2 { |
||
639 | /** |
||
640 | * User's handle for a buffer to be bound into the GTT for this |
||
641 | * operation. |
||
642 | */ |
||
643 | __u32 handle; |
||
644 | |||
645 | /** Number of relocations to be performed on this buffer */ |
||
646 | __u32 relocation_count; |
||
647 | /** |
||
648 | * Pointer to array of struct drm_i915_gem_relocation_entry containing |
||
649 | * the relocations to be performed in this buffer. |
||
650 | */ |
||
651 | __u64 relocs_ptr; |
||
652 | |||
653 | /** Required alignment in graphics aperture */ |
||
654 | __u64 alignment; |
||
655 | |||
656 | /** |
||
657 | * Returned value of the updated offset of the object, for future |
||
658 | * presumed_offset writes. |
||
659 | */ |
||
660 | __u64 offset; |
||
661 | |||
662 | #define EXEC_OBJECT_NEEDS_FENCE (1<<0) |
||
5022 | Serge | 663 | #define EXEC_OBJECT_NEEDS_GTT (1<<1) |
664 | #define EXEC_OBJECT_WRITE (1<<2) |
||
665 | #define __EXEC_OBJECT_UNKNOWN_FLAGS -(EXEC_OBJECT_WRITE<<1) |
||
4363 | Serge | 666 | __u64 flags; |
5022 | Serge | 667 | |
4363 | Serge | 668 | __u64 rsvd1; |
669 | __u64 rsvd2; |
||
670 | }; |
||
671 | |||
672 | struct drm_i915_gem_execbuffer2 { |
||
673 | /** |
||
674 | * List of gem_exec_object2 structs |
||
675 | */ |
||
676 | __u64 buffers_ptr; |
||
677 | __u32 buffer_count; |
||
678 | |||
679 | /** Offset in the batchbuffer to start execution from. */ |
||
680 | __u32 batch_start_offset; |
||
681 | /** Bytes used in batchbuffer from batch_start_offset */ |
||
682 | __u32 batch_len; |
||
683 | __u32 DR1; |
||
684 | __u32 DR4; |
||
685 | __u32 num_cliprects; |
||
686 | /** This is a struct drm_clip_rect *cliprects */ |
||
687 | __u64 cliprects_ptr; |
||
688 | #define I915_EXEC_RING_MASK (7<<0) |
||
689 | #define I915_EXEC_DEFAULT (0<<0) |
||
690 | #define I915_EXEC_RENDER (1<<0) |
||
691 | #define I915_EXEC_BSD (2<<0) |
||
692 | #define I915_EXEC_BLT (3<<0) |
||
693 | #define I915_EXEC_VEBOX (4<<0) |
||
694 | |||
695 | /* Used for switching the constants addressing mode on gen4+ RENDER ring. |
||
696 | * Gen6+ only supports relative addressing to dynamic state (default) and |
||
697 | * absolute addressing. |
||
698 | * |
||
699 | * These flags are ignored for the BSD and BLT rings. |
||
700 | */ |
||
701 | #define I915_EXEC_CONSTANTS_MASK (3<<6) |
||
702 | #define I915_EXEC_CONSTANTS_REL_GENERAL (0<<6) /* default */ |
||
703 | #define I915_EXEC_CONSTANTS_ABSOLUTE (1<<6) |
||
704 | #define I915_EXEC_CONSTANTS_REL_SURFACE (2<<6) /* gen4/5 only */ |
||
705 | __u64 flags; |
||
706 | __u64 rsvd1; /* now used for context info */ |
||
707 | __u64 rsvd2; |
||
708 | }; |
||
709 | |||
710 | /** Resets the SO write offset registers for transform feedback on gen7. */ |
||
711 | #define I915_EXEC_GEN7_SOL_RESET (1<<8) |
||
712 | |||
5022 | Serge | 713 | /** Request a privileged ("secure") batch buffer. Note only available for |
714 | * DRM_ROOT_ONLY | DRM_MASTER processes. |
||
715 | */ |
||
716 | #define I915_EXEC_SECURE (1<<9) |
||
717 | |||
718 | /** Inform the kernel that the batch is and will always be pinned. This |
||
719 | * negates the requirement for a workaround to be performed to avoid |
||
720 | * an incoherent CS (such as can be found on 830/845). If this flag is |
||
721 | * not passed, the kernel will endeavour to make sure the batch is |
||
722 | * coherent with the CS before execution. If this flag is passed, |
||
723 | * userspace assumes the responsibility for ensuring the same. |
||
724 | */ |
||
725 | #define I915_EXEC_IS_PINNED (1<<10) |
||
726 | |||
727 | /** Provide a hint to the kernel that the command stream and auxiliary |
||
728 | * state buffers already holds the correct presumed addresses and so the |
||
729 | * relocation process may be skipped if no buffers need to be moved in |
||
730 | * preparation for the execbuffer. |
||
731 | */ |
||
732 | #define I915_EXEC_NO_RELOC (1<<11) |
||
733 | |||
734 | /** Use the reloc.handle as an index into the exec object array rather |
||
735 | * than as the per-file handle. |
||
736 | */ |
||
737 | #define I915_EXEC_HANDLE_LUT (1<<12) |
||
738 | |||
739 | #define __I915_EXEC_UNKNOWN_FLAGS -(I915_EXEC_HANDLE_LUT<<1) |
||
740 | |||
4363 | Serge | 741 | #define I915_EXEC_CONTEXT_ID_MASK (0xffffffff) |
742 | #define i915_execbuffer2_set_context_id(eb2, context) \ |
||
743 | (eb2).rsvd1 = context & I915_EXEC_CONTEXT_ID_MASK |
||
744 | #define i915_execbuffer2_get_context_id(eb2) \ |
||
745 | ((eb2).rsvd1 & I915_EXEC_CONTEXT_ID_MASK) |
||
746 | |||
747 | struct drm_i915_gem_pin { |
||
748 | /** Handle of the buffer to be pinned. */ |
||
749 | __u32 handle; |
||
750 | __u32 pad; |
||
751 | |||
752 | /** alignment required within the aperture */ |
||
753 | __u64 alignment; |
||
754 | |||
755 | /** Returned GTT offset of the buffer. */ |
||
756 | __u64 offset; |
||
757 | }; |
||
758 | |||
759 | struct drm_i915_gem_unpin { |
||
760 | /** Handle of the buffer to be unpinned. */ |
||
761 | __u32 handle; |
||
762 | __u32 pad; |
||
763 | }; |
||
764 | |||
765 | struct drm_i915_gem_busy { |
||
766 | /** Handle of the buffer to check for busy */ |
||
767 | __u32 handle; |
||
768 | |||
769 | /** Return busy status (1 if busy, 0 if idle). |
||
770 | * The high word is used to indicate on which rings the object |
||
771 | * currently resides: |
||
772 | * 16:31 - busy (r or r/w) rings (16 render, 17 bsd, 18 blt, etc) |
||
773 | */ |
||
774 | __u32 busy; |
||
775 | }; |
||
776 | |||
5022 | Serge | 777 | /** |
778 | * I915_CACHING_NONE |
||
779 | * |
||
780 | * GPU access is not coherent with cpu caches. Default for machines without an |
||
781 | * LLC. |
||
782 | */ |
||
783 | #define I915_CACHING_NONE 0 |
||
784 | /** |
||
785 | * I915_CACHING_CACHED |
||
786 | * |
||
787 | * GPU access is coherent with cpu caches and furthermore the data is cached in |
||
788 | * last-level caches shared between cpu cores and the gpu GT. Default on |
||
789 | * machines with HAS_LLC. |
||
790 | */ |
||
791 | #define I915_CACHING_CACHED 1 |
||
792 | /** |
||
793 | * I915_CACHING_DISPLAY |
||
794 | * |
||
795 | * Special GPU caching mode which is coherent with the scanout engines. |
||
796 | * Transparently falls back to I915_CACHING_NONE on platforms where no special |
||
797 | * cache mode (like write-through or gfdt flushing) is available. The kernel |
||
798 | * automatically sets this mode when using a buffer as a scanout target. |
||
799 | * Userspace can manually set this mode to avoid a costly stall and clflush in |
||
800 | * the hotpath of drawing the first frame. |
||
801 | */ |
||
802 | #define I915_CACHING_DISPLAY 2 |
||
4363 | Serge | 803 | |
5022 | Serge | 804 | struct drm_i915_gem_caching { |
4363 | Serge | 805 | /** |
5022 | Serge | 806 | * Handle of the buffer to set/get the caching level of. */ |
4363 | Serge | 807 | __u32 handle; |
808 | |||
809 | /** |
||
810 | * Cacheing level to apply or return value |
||
811 | * |
||
5022 | Serge | 812 | * bits0-15 are for generic caching control (i.e. the above defined |
4363 | Serge | 813 | * values). bits16-31 are reserved for platform-specific variations |
814 | * (e.g. l3$ caching on gen7). */ |
||
5022 | Serge | 815 | __u32 caching; |
4363 | Serge | 816 | }; |
817 | |||
818 | #define I915_TILING_NONE 0 |
||
819 | #define I915_TILING_X 1 |
||
820 | #define I915_TILING_Y 2 |
||
821 | |||
822 | #define I915_BIT_6_SWIZZLE_NONE 0 |
||
823 | #define I915_BIT_6_SWIZZLE_9 1 |
||
824 | #define I915_BIT_6_SWIZZLE_9_10 2 |
||
825 | #define I915_BIT_6_SWIZZLE_9_11 3 |
||
826 | #define I915_BIT_6_SWIZZLE_9_10_11 4 |
||
827 | /* Not seen by userland */ |
||
828 | #define I915_BIT_6_SWIZZLE_UNKNOWN 5 |
||
829 | /* Seen by userland. */ |
||
830 | #define I915_BIT_6_SWIZZLE_9_17 6 |
||
831 | #define I915_BIT_6_SWIZZLE_9_10_17 7 |
||
832 | |||
833 | struct drm_i915_gem_set_tiling { |
||
834 | /** Handle of the buffer to have its tiling state updated */ |
||
835 | __u32 handle; |
||
836 | |||
837 | /** |
||
838 | * Tiling mode for the object (I915_TILING_NONE, I915_TILING_X, |
||
839 | * I915_TILING_Y). |
||
840 | * |
||
841 | * This value is to be set on request, and will be updated by the |
||
842 | * kernel on successful return with the actual chosen tiling layout. |
||
843 | * |
||
844 | * The tiling mode may be demoted to I915_TILING_NONE when the system |
||
845 | * has bit 6 swizzling that can't be managed correctly by GEM. |
||
846 | * |
||
847 | * Buffer contents become undefined when changing tiling_mode. |
||
848 | */ |
||
849 | __u32 tiling_mode; |
||
850 | |||
851 | /** |
||
852 | * Stride in bytes for the object when in I915_TILING_X or |
||
853 | * I915_TILING_Y. |
||
854 | */ |
||
855 | __u32 stride; |
||
856 | |||
857 | /** |
||
858 | * Returned address bit 6 swizzling required for CPU access through |
||
859 | * mmap mapping. |
||
860 | */ |
||
861 | __u32 swizzle_mode; |
||
862 | }; |
||
863 | |||
864 | struct drm_i915_gem_get_tiling { |
||
865 | /** Handle of the buffer to get tiling state for. */ |
||
866 | __u32 handle; |
||
867 | |||
868 | /** |
||
869 | * Current tiling mode for the object (I915_TILING_NONE, I915_TILING_X, |
||
870 | * I915_TILING_Y). |
||
871 | */ |
||
872 | __u32 tiling_mode; |
||
873 | |||
874 | /** |
||
875 | * Returned address bit 6 swizzling required for CPU access through |
||
876 | * mmap mapping. |
||
877 | */ |
||
878 | __u32 swizzle_mode; |
||
5368 | serge | 879 | |
880 | /** |
||
881 | * Returned address bit 6 swizzling required for CPU access through |
||
882 | * mmap mapping whilst bound. |
||
883 | */ |
||
884 | __u32 phys_swizzle_mode; |
||
4363 | Serge | 885 | }; |
886 | |||
887 | struct drm_i915_gem_get_aperture { |
||
888 | /** Total size of the aperture used by i915_gem_execbuffer, in bytes */ |
||
889 | __u64 aper_size; |
||
890 | |||
891 | /** |
||
892 | * Available space in the aperture used by i915_gem_execbuffer, in |
||
893 | * bytes |
||
894 | */ |
||
895 | __u64 aper_available_size; |
||
896 | }; |
||
897 | |||
898 | struct drm_i915_get_pipe_from_crtc_id { |
||
899 | /** ID of CRTC being requested **/ |
||
900 | __u32 crtc_id; |
||
901 | |||
902 | /** pipe of requested CRTC **/ |
||
903 | __u32 pipe; |
||
904 | }; |
||
905 | |||
906 | #define I915_MADV_WILLNEED 0 |
||
907 | #define I915_MADV_DONTNEED 1 |
||
908 | #define __I915_MADV_PURGED 2 /* internal state */ |
||
909 | |||
910 | struct drm_i915_gem_madvise { |
||
911 | /** Handle of the buffer to change the backing store advice */ |
||
912 | __u32 handle; |
||
913 | |||
914 | /* Advice: either the buffer will be needed again in the near future, |
||
915 | * or wont be and could be discarded under memory pressure. |
||
916 | */ |
||
917 | __u32 madv; |
||
918 | |||
919 | /** Whether the backing store still exists. */ |
||
920 | __u32 retained; |
||
921 | }; |
||
922 | |||
923 | /* flags */ |
||
924 | #define I915_OVERLAY_TYPE_MASK 0xff |
||
925 | #define I915_OVERLAY_YUV_PLANAR 0x01 |
||
926 | #define I915_OVERLAY_YUV_PACKED 0x02 |
||
927 | #define I915_OVERLAY_RGB 0x03 |
||
928 | |||
929 | #define I915_OVERLAY_DEPTH_MASK 0xff00 |
||
930 | #define I915_OVERLAY_RGB24 0x1000 |
||
931 | #define I915_OVERLAY_RGB16 0x2000 |
||
932 | #define I915_OVERLAY_RGB15 0x3000 |
||
933 | #define I915_OVERLAY_YUV422 0x0100 |
||
934 | #define I915_OVERLAY_YUV411 0x0200 |
||
935 | #define I915_OVERLAY_YUV420 0x0300 |
||
936 | #define I915_OVERLAY_YUV410 0x0400 |
||
937 | |||
938 | #define I915_OVERLAY_SWAP_MASK 0xff0000 |
||
939 | #define I915_OVERLAY_NO_SWAP 0x000000 |
||
940 | #define I915_OVERLAY_UV_SWAP 0x010000 |
||
941 | #define I915_OVERLAY_Y_SWAP 0x020000 |
||
942 | #define I915_OVERLAY_Y_AND_UV_SWAP 0x030000 |
||
943 | |||
944 | #define I915_OVERLAY_FLAGS_MASK 0xff000000 |
||
945 | #define I915_OVERLAY_ENABLE 0x01000000 |
||
946 | |||
947 | struct drm_intel_overlay_put_image { |
||
948 | /* various flags and src format description */ |
||
949 | __u32 flags; |
||
950 | /* source picture description */ |
||
951 | __u32 bo_handle; |
||
952 | /* stride values and offsets are in bytes, buffer relative */ |
||
953 | __u16 stride_Y; /* stride for packed formats */ |
||
954 | __u16 stride_UV; |
||
955 | __u32 offset_Y; /* offset for packet formats */ |
||
956 | __u32 offset_U; |
||
957 | __u32 offset_V; |
||
958 | /* in pixels */ |
||
959 | __u16 src_width; |
||
960 | __u16 src_height; |
||
961 | /* to compensate the scaling factors for partially covered surfaces */ |
||
962 | __u16 src_scan_width; |
||
963 | __u16 src_scan_height; |
||
964 | /* output crtc description */ |
||
965 | __u32 crtc_id; |
||
966 | __u16 dst_x; |
||
967 | __u16 dst_y; |
||
968 | __u16 dst_width; |
||
969 | __u16 dst_height; |
||
970 | }; |
||
971 | |||
972 | /* flags */ |
||
973 | #define I915_OVERLAY_UPDATE_ATTRS (1<<0) |
||
974 | #define I915_OVERLAY_UPDATE_GAMMA (1<<1) |
||
975 | struct drm_intel_overlay_attrs { |
||
976 | __u32 flags; |
||
977 | __u32 color_key; |
||
978 | __s32 brightness; |
||
979 | __u32 contrast; |
||
980 | __u32 saturation; |
||
981 | __u32 gamma0; |
||
982 | __u32 gamma1; |
||
983 | __u32 gamma2; |
||
984 | __u32 gamma3; |
||
985 | __u32 gamma4; |
||
986 | __u32 gamma5; |
||
987 | }; |
||
988 | |||
989 | /* |
||
990 | * Intel sprite handling |
||
991 | * |
||
992 | * Color keying works with a min/mask/max tuple. Both source and destination |
||
993 | * color keying is allowed. |
||
994 | * |
||
995 | * Source keying: |
||
996 | * Sprite pixels within the min & max values, masked against the color channels |
||
997 | * specified in the mask field, will be transparent. All other pixels will |
||
998 | * be displayed on top of the primary plane. For RGB surfaces, only the min |
||
999 | * and mask fields will be used; ranged compares are not allowed. |
||
1000 | * |
||
1001 | * Destination keying: |
||
1002 | * Primary plane pixels that match the min value, masked against the color |
||
1003 | * channels specified in the mask field, will be replaced by corresponding |
||
1004 | * pixels from the sprite plane. |
||
1005 | * |
||
1006 | * Note that source & destination keying are exclusive; only one can be |
||
1007 | * active on a given plane. |
||
1008 | */ |
||
1009 | |||
1010 | #define I915_SET_COLORKEY_NONE (1<<0) /* disable color key matching */ |
||
1011 | #define I915_SET_COLORKEY_DESTINATION (1<<1) |
||
1012 | #define I915_SET_COLORKEY_SOURCE (1<<2) |
||
1013 | struct drm_intel_sprite_colorkey { |
||
1014 | __u32 plane_id; |
||
1015 | __u32 min_value; |
||
1016 | __u32 channel_mask; |
||
1017 | __u32 max_value; |
||
1018 | __u32 flags; |
||
1019 | }; |
||
1020 | |||
1021 | struct drm_i915_gem_wait { |
||
1022 | /** Handle of BO we shall wait on */ |
||
1023 | __u32 bo_handle; |
||
1024 | __u32 flags; |
||
1025 | /** Number of nanoseconds to wait, Returns time remaining. */ |
||
1026 | __s64 timeout_ns; |
||
1027 | }; |
||
1028 | |||
1029 | struct drm_i915_gem_context_create { |
||
1030 | /* output: id of new context*/ |
||
1031 | __u32 ctx_id; |
||
1032 | __u32 pad; |
||
1033 | }; |
||
1034 | |||
1035 | struct drm_i915_gem_context_destroy { |
||
1036 | __u32 ctx_id; |
||
1037 | __u32 pad; |
||
1038 | }; |
||
1039 | |||
1040 | struct drm_i915_reg_read { |
||
1041 | __u64 offset; |
||
1042 | __u64 val; /* Return value */ |
||
1043 | }; |
||
1044 | |||
1045 | struct drm_i915_reset_stats { |
||
1046 | __u32 ctx_id; |
||
1047 | __u32 flags; |
||
1048 | |||
1049 | /* All resets since boot/module reload, for all contexts */ |
||
1050 | __u32 reset_count; |
||
1051 | |||
1052 | /* Number of batches lost when active in GPU, for this context */ |
||
1053 | __u32 batch_active; |
||
1054 | |||
1055 | /* Number of batches lost pending for execution, for this context */ |
||
1056 | __u32 batch_pending; |
||
1057 | |||
1058 | __u32 pad; |
||
1059 | }; |
||
1060 | |||
5068 | serge | 1061 | struct drm_i915_gem_userptr { |
1062 | __u64 user_ptr; |
||
1063 | __u64 user_size; |
||
1064 | __u32 flags; |
||
1065 | #define I915_USERPTR_READ_ONLY 0x1 |
||
1066 | #define I915_USERPTR_UNSYNCHRONIZED 0x80000000 |
||
1067 | /** |
||
1068 | * Returned handle for the object. |
||
1069 | * |
||
1070 | * Object handles are nonzero. |
||
1071 | */ |
||
1072 | __u32 handle; |
||
1073 | }; |
||
1074 | |||
5022 | Serge | 1075 | struct drm_i915_mask { |
1076 | __u32 handle; |
||
1077 | __u32 width; |
||
1078 | __u32 height; |
||
1079 | __u32 bo_size; |
||
1080 | __u32 bo_pitch; |
||
1081 | __u32 bo_map; |
||
1082 | }; |
||
1083 | |||
4363 | Serge | 1084 | struct drm_i915_fb_info { |
1085 | __u32 name; |
||
1086 | __u32 width; |
||
1087 | __u32 height; |
||
1088 | __u32 pitch; |
||
1089 | __u32 tiling; |
||
4382 | Serge | 1090 | __u32 crtc; |
1091 | __u32 pipe; |
||
4363 | Serge | 1092 | }; |
1093 | |||
4768 | Serge | 1094 | struct drm_i915_mask_update { |
1095 | __u32 handle; |
||
1096 | __u32 dx; |
||
1097 | __u32 dy; |
||
1098 | __u32 width; |
||
1099 | __u32 height; |
||
1100 | __u32 bo_pitch; |
||
1101 | __u32 bo_map; |
||
5374 | serge | 1102 | __u32 forced; |
4768 | Serge | 1103 | }; |
1104 | |||
4363 | Serge | 1105 | #endif /* _I915_DRM_H_ */2) |