WebSVN – Kolibri OS – Blame – /contrib/sdk/sources/libdrm/include/drm/drm.h

Rev	Author	Line No.	Line
4363	Serge	1	/**
		2	* \file drm.h
		3	* Header for the Direct Rendering Manager
		4	*
		5	* \author Rickard E. (Rik) Faith
		6	*
		7	* \par Acknowledgments:
		8	* Dec 1999, Richard Henderson , move to generic \c cmpxchg.
		9	*/
		10
		11	/*
		12	* Copyright 1999 Precision Insight, Inc., Cedar Park, Texas.
		13	* Copyright 2000 VA Linux Systems, Inc., Sunnyvale, California.
		14	* All rights reserved.
		15	*
		16	* Permission is hereby granted, free of charge, to any person obtaining a
		17	* copy of this software and associated documentation files (the "Software"),
		18	* to deal in the Software without restriction, including without limitation
		19	* the rights to use, copy, modify, merge, publish, distribute, sublicense,
		20	* and/or sell copies of the Software, and to permit persons to whom the
		21	* Software is furnished to do so, subject to the following conditions:
		22	*
		23	* The above copyright notice and this permission notice (including the next
		24	* paragraph) shall be included in all copies or substantial portions of the
		25	* Software.
		26	*
		27	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
		28	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
		29	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
		30	* VA LINUX SYSTEMS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
		31	* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
		32	* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
		33	* OTHER DEALINGS IN THE SOFTWARE.
		34	*/
		35
		36	#ifndef _DRM_H_
		37	#define _DRM_H_
		38
		39	#include
		40
6110	serge	41	#include
4363	Serge	42	typedef int8_t __s8;
		43	typedef uint8_t __u8;
		44	typedef int16_t __s16;
		45	typedef uint16_t __u16;
		46	typedef int32_t __s32;
		47	typedef uint32_t __u32;
		48	typedef int64_t __s64;
		49	typedef uint64_t __u64;
		50	typedef unsigned long drm_handle_t;
		51
		52
		53
		54	#define DRM_NAME "drm" /*< Name in kernel, /dev, and /proc /
		55	#define DRM_MIN_ORDER 5 /*< At least 2^5 bytes = 32 bytes /
		56	#define DRM_MAX_ORDER 22 /*< Up to 2^22 bytes = 4MB /
		57	#define DRM_RAM_PERCENT 10 /*< How much system ram can we lock? /
		58
		59	#define _DRM_LOCK_HELD 0x80000000U /*< Hardware lock is held /
		60	#define _DRM_LOCK_CONT 0x40000000U /*< Hardware lock is contended /
		61	#define _DRM_LOCK_IS_HELD(lock) ((lock) & _DRM_LOCK_HELD)
		62	#define _DRM_LOCK_IS_CONT(lock) ((lock) & _DRM_LOCK_CONT)
		63	#define _DRM_LOCKING_CONTEXT(lock) ((lock) & ~(_DRM_LOCK_HELD\|_DRM_LOCK_CONT))
		64
		65	typedef unsigned int drm_context_t;
		66	typedef unsigned int drm_drawable_t;
		67	typedef unsigned int drm_magic_t;
		68
		69	/**
		70	* Cliprect.
		71	*
		72	* \warning: If you change this structure, make sure you change
		73	* XF86DRIClipRectRec in the server as well
		74	*
		75	* \note KW: Actually it's illegal to change either for
		76	* backwards-compatibility reasons.
		77	*/
		78	struct drm_clip_rect {
		79	unsigned short x1;
		80	unsigned short y1;
		81	unsigned short x2;
		82	unsigned short y2;
		83	};
		84
		85	/**
		86	* Drawable information.
		87	*/
		88	struct drm_drawable_info {
		89	unsigned int num_rects;
		90	struct drm_clip_rect *rects;
		91	};
		92
		93	/**
		94	* Texture region,
		95	*/
		96	struct drm_tex_region {
		97	unsigned char next;
		98	unsigned char prev;
		99	unsigned char in_use;
		100	unsigned char padding;
		101	unsigned int age;
		102	};
		103
		104	/**
		105	* Hardware lock.
		106	*
		107	* The lock structure is a simple cache-line aligned integer. To avoid
		108	* processor bus contention on a multiprocessor system, there should not be any
		109	* other data stored in the same cache line.
		110	*/
		111	struct drm_hw_lock {
		112	__volatile__ unsigned int lock; /*< lock variable /
		113	char padding[60]; /*< Pad to cache line /
		114	};
		115
		116	/**
		117	* DRM_IOCTL_VERSION ioctl argument type.
		118	*
		119	* \sa drmGetVersion().
		120	*/
		121	struct drm_version {
		122	int version_major; /*< Major version /
		123	int version_minor; /*< Minor version /
		124	int version_patchlevel; /*< Patch level /
		125	size_t name_len; /*< Length of name buffer /
		126	char name; /< Name of driver /
		127	size_t date_len; /*< Length of date buffer /
		128	char date; /< User-space buffer to hold date /
		129	size_t desc_len; /*< Length of desc buffer /
		130	char desc; /< User-space buffer to hold desc /
		131	};
		132
		133	/**
		134	* DRM_IOCTL_GET_UNIQUE ioctl argument type.
		135	*
		136	* \sa drmGetBusid() and drmSetBusId().
		137	*/
		138	struct drm_unique {
		139	size_t unique_len; /*< Length of unique /
		140	char unique; /< Unique name for driver instantiation /
		141	};
		142
		143	struct drm_list {
		144	int count; /*< Length of user-space structures /
		145	struct drm_version *version;
		146	};
		147
		148	struct drm_block {
		149	int unused;
		150	};
		151
		152	/**
		153	* DRM_IOCTL_CONTROL ioctl argument type.
		154	*
		155	* \sa drmCtlInstHandler() and drmCtlUninstHandler().
		156	*/
		157	struct drm_control {
		158	enum {
		159	DRM_ADD_COMMAND,
		160	DRM_RM_COMMAND,
		161	DRM_INST_HANDLER,
		162	DRM_UNINST_HANDLER
		163	} func;
		164	int irq;
		165	};
		166
		167	/**
		168	* Type of memory to map.
		169	*/
		170	enum drm_map_type {
		171	_DRM_FRAME_BUFFER = 0, /*< WC (no caching), no core dump /
		172	_DRM_REGISTERS = 1, /*< no caching, no core dump /
		173	_DRM_SHM = 2, /*< shared, cached /
		174	_DRM_AGP = 3, /*< AGP/GART /
		175	_DRM_SCATTER_GATHER = 4, /*< Scatter/gather memory for PCI DMA /
		176	_DRM_CONSISTENT = 5, /*< Consistent memory for PCI DMA /
		177	_DRM_GEM = 6 /*< GEM object /
		178	};
		179
		180	/**
		181	* Memory mapping flags.
		182	*/
		183	enum drm_map_flags {
		184	_DRM_RESTRICTED = 0x01, /*< Cannot be mapped to user-virtual /
		185	_DRM_READ_ONLY = 0x02,
		186	_DRM_LOCKED = 0x04, /*< shared, cached, locked /
		187	_DRM_KERNEL = 0x08, /*< kernel requires access /
		188	_DRM_WRITE_COMBINING = 0x10, /*< use write-combining if available /
		189	_DRM_CONTAINS_LOCK = 0x20, /*< SHM page that contains lock /
		190	_DRM_REMOVABLE = 0x40, /*< Removable mapping /
		191	_DRM_DRIVER = 0x80 /*< Managed by driver /
		192	};
		193
		194	struct drm_ctx_priv_map {
		195	unsigned int ctx_id; /*< Context requesting private mapping /
		196	void handle; /< Handle of map /
		197	};
		198
		199	/**
		200	* DRM_IOCTL_GET_MAP, DRM_IOCTL_ADD_MAP and DRM_IOCTL_RM_MAP ioctls
		201	* argument type.
		202	*
		203	* \sa drmAddMap().
		204	*/
		205	struct drm_map {
		206	unsigned long offset; /*< Requested physical address (0 for SAREA)/
		207	unsigned long size; /*< Requested physical size (bytes) /
		208	enum drm_map_type type; /*< Type of memory to map /
		209	enum drm_map_flags flags; /*< Flags /
		210	void handle; /< User-space: "Handle" to pass to mmap() /
		211	/*< Kernel-space: kernel-virtual address /
		212	int mtrr; /*< MTRR slot used /
		213	/* Private data */
		214	};
		215
		216	/**
		217	* DRM_IOCTL_GET_CLIENT ioctl argument type.
		218	*/
		219	struct drm_client {
		220	int idx; /*< Which client desired? /
		221	int auth; /*< Is client authenticated? /
		222	unsigned long pid; /*< Process ID /
		223	unsigned long uid; /*< User ID /
		224	unsigned long magic; /*< Magic /
		225	unsigned long iocs; /*< Ioctl count /
		226	};
		227
		228	enum drm_stat_type {
		229	_DRM_STAT_LOCK,
		230	_DRM_STAT_OPENS,
		231	_DRM_STAT_CLOSES,
		232	_DRM_STAT_IOCTLS,
		233	_DRM_STAT_LOCKS,
		234	_DRM_STAT_UNLOCKS,
		235	_DRM_STAT_VALUE, /*< Generic value /
		236	_DRM_STAT_BYTE, /*< Generic byte counter (1024bytes/K) /
		237	_DRM_STAT_COUNT, /*< Generic non-byte counter (1000/k) /
		238
		239	_DRM_STAT_IRQ, /*< IRQ /
		240	_DRM_STAT_PRIMARY, /*< Primary DMA bytes /
		241	_DRM_STAT_SECONDARY, /*< Secondary DMA bytes /
		242	_DRM_STAT_DMA, /*< DMA /
		243	_DRM_STAT_SPECIAL, /*< Special DMA (e.g., priority or polled) /
		244	_DRM_STAT_MISSED /*< Missed DMA opportunity /
		245	/* Add to the END of the list */
		246	};
		247
		248	/**
		249	* DRM_IOCTL_GET_STATS ioctl argument type.
		250	*/
		251	struct drm_stats {
		252	unsigned long count;
		253	struct {
		254	unsigned long value;
		255	enum drm_stat_type type;
		256	} data[15];
		257	};
		258
		259	/**
		260	* Hardware locking flags.
		261	*/
		262	enum drm_lock_flags {
		263	_DRM_LOCK_READY = 0x01, /*< Wait until hardware is ready for DMA /
		264	_DRM_LOCK_QUIESCENT = 0x02, /*< Wait until hardware quiescent /
		265	_DRM_LOCK_FLUSH = 0x04, /*< Flush this context's DMA queue first /
		266	_DRM_LOCK_FLUSH_ALL = 0x08, /*< Flush all DMA queues first /
		267	/* These HALT flags aren't supported yet
		268	-- they will be used to support the
		269	full-screen DGA-like mode. */
		270	_DRM_HALT_ALL_QUEUES = 0x10, /*< Halt all current and future queues /
		271	_DRM_HALT_CUR_QUEUES = 0x20 /*< Halt all current queues /
		272	};
		273
		274	/**
		275	* DRM_IOCTL_LOCK, DRM_IOCTL_UNLOCK and DRM_IOCTL_FINISH ioctl argument type.
		276	*
		277	* \sa drmGetLock() and drmUnlock().
		278	*/
		279	struct drm_lock {
		280	int context;
		281	enum drm_lock_flags flags;
		282	};
		283
		284	/**
		285	* DMA flags
		286	*
		287	* \warning
		288	* These values \e must match xf86drm.h.
		289	*
		290	* \sa drm_dma.
		291	*/
		292	enum drm_dma_flags {
		293	/* Flags for DMA buffer dispatch */
		294	_DRM_DMA_BLOCK = 0x01, /**<
		295	* Block until buffer dispatched.
		296	*
		297	* \note The buffer may not yet have
		298	* been processed by the hardware --
		299	* getting a hardware lock with the
		300	* hardware quiescent will ensure
		301	* that the buffer has been
		302	* processed.
		303	*/
		304	_DRM_DMA_WHILE_LOCKED = 0x02, /*< Dispatch while lock held /
		305	_DRM_DMA_PRIORITY = 0x04, /*< High priority dispatch /
		306
		307	/* Flags for DMA buffer request */
		308	_DRM_DMA_WAIT = 0x10, /*< Wait for free buffers /
		309	_DRM_DMA_SMALLER_OK = 0x20, /*< Smaller-than-requested buffers OK /
		310	_DRM_DMA_LARGER_OK = 0x40 /*< Larger-than-requested buffers OK /
		311	};
		312
		313	/**
		314	* DRM_IOCTL_ADD_BUFS and DRM_IOCTL_MARK_BUFS ioctl argument type.
		315	*
		316	* \sa drmAddBufs().
		317	*/
		318	struct drm_buf_desc {
		319	int count; /*< Number of buffers of this size /
		320	int size; /*< Size in bytes /
		321	int low_mark; /*< Low water mark /
		322	int high_mark; /*< High water mark /
		323	enum {
		324	_DRM_PAGE_ALIGN = 0x01, /*< Align on page boundaries for DMA /
		325	_DRM_AGP_BUFFER = 0x02, /*< Buffer is in AGP space /
		326	_DRM_SG_BUFFER = 0x04, /*< Scatter/gather memory buffer /
		327	_DRM_FB_BUFFER = 0x08, /*< Buffer is in frame buffer /
		328	_DRM_PCI_BUFFER_RO = 0x10 /*< Map PCI DMA buffer read-only /
		329	} flags;
		330	unsigned long agp_start; /**<
		331	* Start address of where the AGP buffers are
		332	* in the AGP aperture
		333	*/
		334	};
		335
		336	/**
		337	* DRM_IOCTL_INFO_BUFS ioctl argument type.
		338	*/
		339	struct drm_buf_info {
		340	int count; /*< Entries in list /
		341	struct drm_buf_desc *list;
		342	};
		343
		344	/**
		345	* DRM_IOCTL_FREE_BUFS ioctl argument type.
		346	*/
		347	struct drm_buf_free {
		348	int count;
		349	int *list;
		350	};
		351
		352	/**
		353	* Buffer information
		354	*
		355	* \sa drm_buf_map.
		356	*/
		357	struct drm_buf_pub {
		358	int idx; /*< Index into the master buffer list /
		359	int total; /*< Buffer size /
		360	int used; /*< Amount of buffer in use (for DMA) /
		361	void address; /< Address of buffer /
		362	};
		363
		364	/**
		365	* DRM_IOCTL_MAP_BUFS ioctl argument type.
		366	*/
		367	struct drm_buf_map {
		368	int count; /*< Length of the buffer list /
		369	#ifdef __cplusplus
		370	void *virt;
		371	#else
		372	void virtual; /< Mmap'd area in user-virtual /
		373	#endif
		374	struct drm_buf_pub list; /< Buffer information /
		375	};
		376
		377	/**
		378	* DRM_IOCTL_DMA ioctl argument type.
		379	*
		380	* Indices here refer to the offset into the buffer list in drm_buf_get.
		381	*
		382	* \sa drmDMA().
		383	*/
		384	struct drm_dma {
		385	int context; /*< Context handle /
		386	int send_count; /*< Number of buffers to send /
		387	int send_indices; /< List of handles to buffers /
		388	int send_sizes; /< Lengths of data to send /
		389	enum drm_dma_flags flags; /*< Flags /
		390	int request_count; /*< Number of buffers requested /
		391	int request_size; /*< Desired size for buffers /
		392	int request_indices; /< Buffer information /
		393	int *request_sizes;
		394	int granted_count; /*< Number of buffers granted /
		395	};
		396
		397	enum drm_ctx_flags {
		398	_DRM_CONTEXT_PRESERVED = 0x01,
		399	_DRM_CONTEXT_2DONLY = 0x02
		400	};
		401
		402	/**
		403	* DRM_IOCTL_ADD_CTX ioctl argument type.
		404	*
		405	* \sa drmCreateContext() and drmDestroyContext().
		406	*/
		407	struct drm_ctx {
		408	drm_context_t handle;
		409	enum drm_ctx_flags flags;
		410	};
		411
		412	/**
		413	* DRM_IOCTL_RES_CTX ioctl argument type.
		414	*/
		415	struct drm_ctx_res {
		416	int count;
		417	struct drm_ctx *contexts;
		418	};
		419
		420	/**
		421	* DRM_IOCTL_ADD_DRAW and DRM_IOCTL_RM_DRAW ioctl argument type.
		422	*/
		423	struct drm_draw {
		424	drm_drawable_t handle;
		425	};
		426
		427	/**
		428	* DRM_IOCTL_UPDATE_DRAW ioctl argument type.
		429	*/
		430	typedef enum {
5068	serge	431	DRM_DRAWABLE_CLIPRECTS
4363	Serge	432	} drm_drawable_info_type_t;
		433
		434	struct drm_update_draw {
		435	drm_drawable_t handle;
		436	unsigned int type;
		437	unsigned int num;
		438	unsigned long long data;
		439	};
		440
		441	/**
		442	* DRM_IOCTL_GET_MAGIC and DRM_IOCTL_AUTH_MAGIC ioctl argument type.
		443	*/
		444	struct drm_auth {
		445	drm_magic_t magic;
		446	};
		447
		448	/**
		449	* DRM_IOCTL_IRQ_BUSID ioctl argument type.
		450	*
		451	* \sa drmGetInterruptFromBusID().
		452	*/
		453	struct drm_irq_busid {
		454	int irq; /*< IRQ number /
		455	int busnum; /*< bus number /
		456	int devnum; /*< device number /
		457	int funcnum; /*< function number /
		458	};
		459
		460	enum drm_vblank_seq_type {
		461	_DRM_VBLANK_ABSOLUTE = 0x0, /*< Wait for specific vblank sequence number /
		462	_DRM_VBLANK_RELATIVE = 0x1, /*< Wait for given number of vblanks /
		463	_DRM_VBLANK_EVENT = 0x4000000, /*< Send event instead of blocking /
		464	_DRM_VBLANK_FLIP = 0x8000000, /*< Scheduled buffer swap should flip /
		465	_DRM_VBLANK_NEXTONMISS = 0x10000000, /*< If missed, wait for next vblank /
		466	_DRM_VBLANK_SECONDARY = 0x20000000, /*< Secondary display controller /
		467	_DRM_VBLANK_SIGNAL = 0x40000000 /*< Send signal instead of blocking, unsupported /
		468	};
		469
		470	#define _DRM_VBLANK_TYPES_MASK (_DRM_VBLANK_ABSOLUTE \| _DRM_VBLANK_RELATIVE)
		471	#define _DRM_VBLANK_FLAGS_MASK (_DRM_VBLANK_EVENT \| _DRM_VBLANK_SIGNAL \| \
		472	_DRM_VBLANK_SECONDARY \| _DRM_VBLANK_NEXTONMISS)
		473
		474	struct drm_wait_vblank_request {
		475	enum drm_vblank_seq_type type;
		476	unsigned int sequence;
		477	unsigned long signal;
		478	};
		479
		480	struct drm_wait_vblank_reply {
		481	enum drm_vblank_seq_type type;
		482	unsigned int sequence;
		483	long tval_sec;
		484	long tval_usec;
		485	};
		486
		487	/**
		488	* DRM_IOCTL_WAIT_VBLANK ioctl argument type.
		489	*
		490	* \sa drmWaitVBlank().
		491	*/
		492	union drm_wait_vblank {
		493	struct drm_wait_vblank_request request;
		494	struct drm_wait_vblank_reply reply;
		495	};
		496
		497	#define _DRM_PRE_MODESET 1
		498	#define _DRM_POST_MODESET 2
		499
		500	/**
		501	* DRM_IOCTL_MODESET_CTL ioctl argument type
		502	*
		503	* \sa drmModesetCtl().
		504	*/
		505	struct drm_modeset_ctl {
		506	__u32 crtc;
		507	__u32 cmd;
		508	};
		509
		510	/**
		511	* DRM_IOCTL_AGP_ENABLE ioctl argument type.
		512	*
		513	* \sa drmAgpEnable().
		514	*/
		515	struct drm_agp_mode {
		516	unsigned long mode; /*< AGP mode /
		517	};
		518
		519	/**
		520	* DRM_IOCTL_AGP_ALLOC and DRM_IOCTL_AGP_FREE ioctls argument type.
		521	*
		522	* \sa drmAgpAlloc() and drmAgpFree().
		523	*/
		524	struct drm_agp_buffer {
		525	unsigned long size; /*< In bytes -- will round to page boundary /
		526	unsigned long handle; /*< Used for binding / unbinding /
		527	unsigned long type; /*< Type of memory to allocate /
		528	unsigned long physical; /*< Physical used by i810 /
		529	};
		530
		531	/**
		532	* DRM_IOCTL_AGP_BIND and DRM_IOCTL_AGP_UNBIND ioctls argument type.
		533	*
		534	* \sa drmAgpBind() and drmAgpUnbind().
		535	*/
		536	struct drm_agp_binding {
		537	unsigned long handle; /*< From drm_agp_buffer /
		538	unsigned long offset; /*< In bytes -- will round to page boundary /
		539	};
		540
		541	/**
		542	* DRM_IOCTL_AGP_INFO ioctl argument type.
		543	*
		544	* \sa drmAgpVersionMajor(), drmAgpVersionMinor(), drmAgpGetMode(),
		545	* drmAgpBase(), drmAgpSize(), drmAgpMemoryUsed(), drmAgpMemoryAvail(),
		546	* drmAgpVendorId() and drmAgpDeviceId().
		547	*/
		548	struct drm_agp_info {
		549	int agp_version_major;
		550	int agp_version_minor;
		551	unsigned long mode;
		552	unsigned long aperture_base; /* physical address */
		553	unsigned long aperture_size; /* bytes */
		554	unsigned long memory_allowed; /* bytes */
		555	unsigned long memory_used;
		556
		557	/* PCI information */
		558	unsigned short id_vendor;
		559	unsigned short id_device;
		560	};
		561
		562	/**
		563	* DRM_IOCTL_SG_ALLOC ioctl argument type.
		564	*/
		565	struct drm_scatter_gather {
		566	unsigned long size; /*< In bytes -- will round to page boundary /
		567	unsigned long handle; /*< Used for mapping / unmapping /
		568	};
		569
		570	/**
		571	* DRM_IOCTL_SET_VERSION ioctl argument type.
		572	*/
		573	struct drm_set_version {
		574	int drm_di_major;
		575	int drm_di_minor;
		576	int drm_dd_major;
		577	int drm_dd_minor;
		578	};
		579
		580	/** DRM_IOCTL_GEM_CLOSE ioctl argument type */
		581	struct drm_gem_close {
		582	/** Handle of the object to be closed. */
		583	__u32 handle;
		584	__u32 pad;
		585	};
		586
		587	/** DRM_IOCTL_GEM_FLINK ioctl argument type */
		588	struct drm_gem_flink {
		589	/** Handle for the object being named */
		590	__u32 handle;
		591
		592	/** Returned global name */
		593	__u32 name;
		594	};
		595
		596	/** DRM_IOCTL_GEM_OPEN ioctl argument type */
		597	struct drm_gem_open {
		598	/** Name of object being opened */
		599	__u32 name;
		600
		601	/** Returned handle for the object */
		602	__u32 handle;
		603
		604	/** Returned size of the object */
		605	__u64 size;
		606	};
		607
		608	/** DRM_IOCTL_GET_CAP ioctl argument type */
		609	struct drm_get_cap {
		610	__u64 capability;
		611	__u64 value;
		612	};
		613
		614	/**
		615	* DRM_CLIENT_CAP_STEREO_3D
		616	*
		617	* if set to 1, the DRM core will expose the stereo 3D capabilities of the
		618	* monitor by advertising the supported 3D layouts in the flags of struct
		619	* drm_mode_modeinfo.
		620	*/
		621	#define DRM_CLIENT_CAP_STEREO_3D 1
		622
5068	serge	623	/**
		624	* DRM_CLIENT_CAP_UNIVERSAL_PLANES
		625	*
		626	* if set to 1, the DRM core will expose the full universal plane list
		627	* (including primary and cursor planes).
		628	*/
		629	#define DRM_CLIENT_CAP_UNIVERSAL_PLANES 2
		630
6110	serge	631	/**
		632	* DRM_CLIENT_CAP_ATOMIC
		633	*
		634	* If set to 1, the DRM core will allow atomic modesetting requests.
		635	*/
		636	#define DRM_CLIENT_CAP_ATOMIC 3
		637
4363	Serge	638	/** DRM_IOCTL_SET_CLIENT_CAP ioctl argument type */
		639	struct drm_set_client_cap {
		640	__u64 capability;
		641	__u64 value;
		642	};
		643
		644	#define DRM_CLOEXEC O_CLOEXEC
		645	struct drm_prime_handle {
		646	__u32 handle;
		647
		648	/** Flags.. only applicable for handle->fd */
		649	__u32 flags;
		650
		651	/** Returned dmabuf file descriptor */
		652	__s32 fd;
		653	};
		654
		655	#define SRV_GET_PCI_INFO 20
		656	#define SRV_I915_GET_PARAM 21
		657	#define SRV_I915_GEM_CREATE 22
		658	#define SRV_DRM_GEM_CLOSE 23
		659	#define SRV_DRM_GEM_FLINK 24
		660	#define SRV_DRM_GEM_OPEN 25
		661	#define SRV_I915_GEM_PIN 26
		662	#define SRV_I915_GEM_UNPIN 27
5368	serge	663	#define SRV_I915_GEM_GET_CACHING 28
		664	#define SRV_I915_GEM_SET_CACHING 29
		665	#define SRV_I915_GEM_PWRITE 30
		666	#define SRV_I915_GEM_BUSY 31
		667	#define SRV_I915_GEM_SET_DOMAIN 32
		668	#define SRV_I915_GEM_MMAP 33
		669	#define SRV_I915_GEM_SET_TILING 34
		670	#define SRV_I915_GEM_GET_TILING 35
		671	#define SRV_I915_GEM_GET_APERTURE 36
		672	#define SRV_I915_GEM_MMAP_GTT 37
		673	#define SRV_I915_GEM_THROTTLE 38
		674	#define SRV_I915_GEM_EXECBUFFER2 39
		675	#define SRV_I915_GEM_WAIT 40
		676	#define SRV_I915_GEM_CONTEXT_CREATE 41
		677	#define SRV_I915_GEM_CONTEXT_DESTROY 42
		678	#define SRV_I915_REG_READ 43
4363	Serge	679
5368	serge	680	#define SRV_FBINFO 44
		681	#define SRV_MASK_UPDATE 45
		682	#define SRV_MASK_UPDATE_EX 46
4363	Serge	683
6110	serge	684	#define SRV_I915_GEM_PREAD 47
		685	#define SRV_I915_GEM_EXECBUFFER 48
4363	Serge	686
		687	#include "drm_mode.h"
		688
		689	#define DRM_IOCTL_BASE 'd'
6110	serge	690	#define DRM_IO(nr) _IO(DRM_IOCTL_BASE,nr)
4363	Serge	691	#define DRM_IOR(nr,type) _IOR(DRM_IOCTL_BASE,nr,type)
		692	#define DRM_IOW(nr,type) _IOW(DRM_IOCTL_BASE,nr,type)
		693	#define DRM_IOWR(nr,type) _IOWR(DRM_IOCTL_BASE,nr,type)
		694
		695	#define DRM_IOCTL_VERSION
		696	#define DRM_IOCTL_GET_UNIQUE
		697	#define DRM_IOCTL_GET_MAGIC
		698	#define DRM_IOCTL_IRQ_BUSID
		699	#define DRM_IOCTL_GET_MAP
		700	#define DRM_IOCTL_GET_CLIENT
		701	#define DRM_IOCTL_GET_STATS
		702	#define DRM_IOCTL_SET_VERSION
		703	#define DRM_IOCTL_MODESET_CTL
		704	#define DRM_IOCTL_GEM_CLOSE SRV_DRM_GEM_CLOSE
		705	#define DRM_IOCTL_GEM_FLINK SRV_DRM_GEM_FLINK
		706	#define DRM_IOCTL_GEM_OPEN SRV_DRM_GEM_OPEN
		707	#define DRM_IOCTL_GET_CAP
		708	#define DRM_IOCTL_SET_CLIENT_CAP
		709
		710	#define DRM_IOCTL_SET_UNIQUE
		711	#define DRM_IOCTL_AUTH_MAGIC
		712	#define DRM_IOCTL_BLOCK
		713	#define DRM_IOCTL_UNBLOCK
		714	#define DRM_IOCTL_CONTROL
		715	#define DRM_IOCTL_ADD_MAP
		716	#define DRM_IOCTL_ADD_BUFS
		717	#define DRM_IOCTL_MARK_BUFS
		718	#define DRM_IOCTL_INFO_BUFS
		719	#define DRM_IOCTL_MAP_BUFS
		720	#define DRM_IOCTL_FREE_BUFS
		721
		722	#define DRM_IOCTL_RM_MAP
		723
		724	#define DRM_IOCTL_SET_SAREA_CTX
		725	#define DRM_IOCTL_GET_SAREA_CTX
		726
		727	#define DRM_IOCTL_SET_MASTER
		728	#define DRM_IOCTL_DROP_MASTER
		729
		730	#define DRM_IOCTL_ADD_CTX
		731	#define DRM_IOCTL_RM_CTX
		732	#define DRM_IOCTL_MOD_CTX
		733	#define DRM_IOCTL_GET_CTX
		734	#define DRM_IOCTL_SWITCH_CTX
		735	#define DRM_IOCTL_NEW_CTX
		736	#define DRM_IOCTL_RES_CTX
		737	#define DRM_IOCTL_ADD_DRAW
		738	#define DRM_IOCTL_RM_DRAW
		739	#define DRM_IOCTL_DMA
		740	#define DRM_IOCTL_LOCK
		741	#define DRM_IOCTL_UNLOCK
		742	#define DRM_IOCTL_FINISH
		743
		744	#define DRM_IOCTL_PRIME_HANDLE_TO_FD
		745	#define DRM_IOCTL_PRIME_FD_TO_HANDLE
		746
		747	#define DRM_IOCTL_AGP_ACQUIRE
		748	#define DRM_IOCTL_AGP_RELEASE
		749	#define DRM_IOCTL_AGP_ENABLE
		750	#define DRM_IOCTL_AGP_INFO
		751	#define DRM_IOCTL_AGP_ALLOC
		752	#define DRM_IOCTL_AGP_FREE
		753	#define DRM_IOCTL_AGP_BIND
		754	#define DRM_IOCTL_AGP_UNBIND
		755
		756	#define DRM_IOCTL_SG_ALLOC
		757	#define DRM_IOCTL_SG_FREE
		758
		759	#define DRM_IOCTL_WAIT_VBLANK
		760
		761	#define DRM_IOCTL_UPDATE_DRAW
		762
		763	#define DRM_IOCTL_MODE_GETRESOURCES
		764	#define DRM_IOCTL_MODE_GETCRTC
		765	#define DRM_IOCTL_MODE_SETCRTC
		766	#define DRM_IOCTL_MODE_CURSOR
		767	#define DRM_IOCTL_MODE_GETGAMMA
		768	#define DRM_IOCTL_MODE_SETGAMMA
		769	#define DRM_IOCTL_MODE_GETENCODER
		770	#define DRM_IOCTL_MODE_GETCONNECTOR
		771	#define DRM_IOCTL_MODE_ATTACHMODE
		772	#define DRM_IOCTL_MODE_DETACHMODE
		773
		774	#define DRM_IOCTL_MODE_GETPROPERTY
		775	#define DRM_IOCTL_MODE_SETPROPERTY
		776	#define DRM_IOCTL_MODE_GETPROPBLOB
		777	#define DRM_IOCTL_MODE_GETFB
		778	#define DRM_IOCTL_MODE_ADDFB
		779	#define DRM_IOCTL_MODE_RMFB
		780	#define DRM_IOCTL_MODE_PAGE_FLIP
		781	#define DRM_IOCTL_MODE_DIRTYFB
		782
		783	#define DRM_IOCTL_MODE_CREATE_DUMB
		784	#define DRM_IOCTL_MODE_MAP_DUMB
		785	#define DRM_IOCTL_MODE_DESTROY_DUMB
		786	#define DRM_IOCTL_MODE_GETPLANERESOURCES
		787	#define DRM_IOCTL_MODE_GETPLANE
		788	#define DRM_IOCTL_MODE_SETPLANE
		789	#define DRM_IOCTL_MODE_ADDFB2
		790	#define DRM_IOCTL_MODE_OBJ_GETPROPERTIES
		791	#define DRM_IOCTL_MODE_OBJ_SETPROPERTY
		792	#define DRM_IOCTL_MODE_CURSOR2
		793
		794	/**
		795	* Device specific ioctls should only be in their respective headers
		796	* The device specific ioctl range is from 0x40 to 0x99.
		797	* Generic IOCTLS restart at 0xA0.
		798	*
		799	* \sa drmCommandNone(), drmCommandRead(), drmCommandWrite(), and
		800	* drmCommandReadWrite().
		801	*/
		802	#define DRM_COMMAND_BASE 0x40
		803	#define DRM_COMMAND_END 0xA0
		804
		805	/**
		806	* Header for events written back to userspace on the drm fd. The
		807	* type defines the type of event, the length specifies the total
		808	* length of the event (including the header), and user_data is
		809	* typically a 64 bit value passed with the ioctl that triggered the
		810	* event. A read on the drm fd will always only return complete
		811	* events, that is, if for example the read buffer is 100 bytes, and
		812	* there are two 64 byte events pending, only one will be returned.
		813	*
		814	* Event types 0 - 0x7fffffff are generic drm events, 0x80000000 and
		815	* up are chipset specific.
		816	*/
		817	struct drm_event {
		818	__u32 type;
		819	__u32 length;
		820	};
		821
		822	#define DRM_EVENT_VBLANK 0x01
		823	#define DRM_EVENT_FLIP_COMPLETE 0x02
		824
		825	struct drm_event_vblank {
		826	struct drm_event base;
		827	__u64 user_data;
		828	__u32 tv_sec;
		829	__u32 tv_usec;
		830	__u32 sequence;
		831	__u32 reserved;
		832	};
		833
		834	#define DRM_CAP_DUMB_BUFFER 0x1
		835	#define DRM_CAP_VBLANK_HIGH_CRTC 0x2
		836	#define DRM_CAP_DUMB_PREFERRED_DEPTH 0x3
		837	#define DRM_CAP_DUMB_PREFER_SHADOW 0x4
		838	#define DRM_CAP_PRIME 0x5
		839	#define DRM_CAP_TIMESTAMP_MONOTONIC 0x6
		840	#define DRM_CAP_ASYNC_PAGE_FLIP 0x7
6110	serge	841	#define DRM_CAP_ADDFB2_MODIFIERS 0x10
4363	Serge	842
		843	#define DRM_PRIME_CAP_IMPORT 0x1
		844	#define DRM_PRIME_CAP_EXPORT 0x2
		845
		846	/* typedef area */
		847	typedef struct drm_clip_rect drm_clip_rect_t;
		848	typedef struct drm_drawable_info drm_drawable_info_t;
		849	typedef struct drm_tex_region drm_tex_region_t;
		850	typedef struct drm_hw_lock drm_hw_lock_t;
		851	typedef struct drm_version drm_version_t;
		852	typedef struct drm_unique drm_unique_t;
		853	typedef struct drm_list drm_list_t;
		854	typedef struct drm_block drm_block_t;
		855	typedef struct drm_control drm_control_t;
		856	typedef enum drm_map_type drm_map_type_t;
		857	typedef enum drm_map_flags drm_map_flags_t;
		858	typedef struct drm_ctx_priv_map drm_ctx_priv_map_t;
		859	typedef struct drm_map drm_map_t;
		860	typedef struct drm_client drm_client_t;
		861	typedef enum drm_stat_type drm_stat_type_t;
		862	typedef struct drm_stats drm_stats_t;
		863	typedef enum drm_lock_flags drm_lock_flags_t;
		864	typedef struct drm_lock drm_lock_t;
		865	typedef enum drm_dma_flags drm_dma_flags_t;
		866	typedef struct drm_buf_desc drm_buf_desc_t;
		867	typedef struct drm_buf_info drm_buf_info_t;
		868	typedef struct drm_buf_free drm_buf_free_t;
		869	typedef struct drm_buf_pub drm_buf_pub_t;
		870	typedef struct drm_buf_map drm_buf_map_t;
		871	typedef struct drm_dma drm_dma_t;
		872	typedef union drm_wait_vblank drm_wait_vblank_t;
		873	typedef struct drm_agp_mode drm_agp_mode_t;
		874	typedef enum drm_ctx_flags drm_ctx_flags_t;
		875	typedef struct drm_ctx drm_ctx_t;
		876	typedef struct drm_ctx_res drm_ctx_res_t;
		877	typedef struct drm_draw drm_draw_t;
		878	typedef struct drm_update_draw drm_update_draw_t;
		879	typedef struct drm_auth drm_auth_t;
		880	typedef struct drm_irq_busid drm_irq_busid_t;
		881	typedef enum drm_vblank_seq_type drm_vblank_seq_type_t;
		882
		883	typedef struct drm_agp_buffer drm_agp_buffer_t;
		884	typedef struct drm_agp_binding drm_agp_binding_t;
		885	typedef struct drm_agp_info drm_agp_info_t;
		886	typedef struct drm_scatter_gather drm_scatter_gather_t;
		887	typedef struct drm_set_version drm_set_version_t;
		888
		889	int drmIoctl(int fd, unsigned long request, void *arg);
		890
		891	#endif

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(root)/contrib/sdk/sources/libdrm/include/drm/drm.h @ 5068 – Rev 6110