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4349 | Serge | 1 | /* |
2 | * CPU detection code, extracted from mmx.h |
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3 | * (c)1997-99 by H. Dietz and R. Fisher |
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4 | * Converted to C and improved by Fabrice Bellard. |
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5 | * |
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6 | * This file is part of FFmpeg. |
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7 | * |
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8 | * FFmpeg is free software; you can redistribute it and/or |
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9 | * modify it under the terms of the GNU Lesser General Public |
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10 | * License as published by the Free Software Foundation; either |
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11 | * version 2.1 of the License, or (at your option) any later version. |
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12 | * |
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13 | * FFmpeg is distributed in the hope that it will be useful, |
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14 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
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15 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU |
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16 | * Lesser General Public License for more details. |
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17 | * |
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18 | * You should have received a copy of the GNU Lesser General Public |
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19 | * License along with FFmpeg; if not, write to the Free Software |
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20 | * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA |
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21 | */ |
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22 | |||
23 | #include |
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24 | #include |
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25 | |||
26 | #include "libavutil/x86/asm.h" |
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27 | #include "libavutil/x86/cpu.h" |
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28 | #include "libavutil/cpu.h" |
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29 | #include "libavutil/cpu_internal.h" |
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30 | |||
31 | #if HAVE_YASM |
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32 | |||
33 | #define cpuid(index, eax, ebx, ecx, edx) \ |
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34 | ff_cpu_cpuid(index, &eax, &ebx, &ecx, &edx) |
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35 | |||
36 | #define xgetbv(index, eax, edx) \ |
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37 | ff_cpu_xgetbv(index, &eax, &edx) |
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38 | |||
39 | #elif HAVE_INLINE_ASM |
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40 | |||
41 | /* ebx saving is necessary for PIC. gcc seems unable to see it alone */ |
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42 | #define cpuid(index, eax, ebx, ecx, edx) \ |
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43 | __asm__ volatile ( \ |
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44 | "mov %%"REG_b", %%"REG_S" \n\t" \ |
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45 | "cpuid \n\t" \ |
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46 | "xchg %%"REG_b", %%"REG_S \ |
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47 | : "=a" (eax), "=S" (ebx), "=c" (ecx), "=d" (edx) \ |
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48 | : "0" (index)) |
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49 | |||
50 | #define xgetbv(index, eax, edx) \ |
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51 | __asm__ (".byte 0x0f, 0x01, 0xd0" : "=a"(eax), "=d"(edx) : "c" (index)) |
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52 | |||
53 | #define get_eflags(x) \ |
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54 | __asm__ volatile ("pushfl \n" \ |
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55 | "pop %0 \n" \ |
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56 | : "=r"(x)) |
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57 | |||
58 | #define set_eflags(x) \ |
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59 | __asm__ volatile ("push %0 \n" \ |
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60 | "popfl \n" \ |
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61 | :: "r"(x)) |
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62 | |||
63 | #endif /* HAVE_INLINE_ASM */ |
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64 | |||
65 | #if ARCH_X86_64 |
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66 | |||
67 | #define cpuid_test() 1 |
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68 | |||
69 | #elif HAVE_YASM |
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70 | |||
71 | #define cpuid_test ff_cpu_cpuid_test |
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72 | |||
73 | #elif HAVE_INLINE_ASM |
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74 | |||
75 | static int cpuid_test(void) |
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76 | { |
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77 | x86_reg a, c; |
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78 | |||
79 | /* Check if CPUID is supported by attempting to toggle the ID bit in |
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80 | * the EFLAGS register. */ |
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81 | get_eflags(a); |
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82 | set_eflags(a ^ 0x200000); |
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83 | get_eflags(c); |
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84 | |||
85 | return a != c; |
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86 | } |
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87 | #endif |
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88 | |||
89 | /* Function to test if multimedia instructions are supported... */ |
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90 | int ff_get_cpu_flags_x86(void) |
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91 | { |
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92 | int rval = 0; |
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93 | |||
94 | #ifdef cpuid |
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95 | |||
96 | int eax, ebx, ecx, edx; |
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97 | int max_std_level, max_ext_level, std_caps = 0, ext_caps = 0; |
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98 | int family = 0, model = 0; |
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99 | union { int i[3]; char c[12]; } vendor; |
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100 | |||
101 | if (!cpuid_test()) |
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102 | return 0; /* CPUID not supported */ |
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103 | |||
104 | cpuid(0, max_std_level, vendor.i[0], vendor.i[2], vendor.i[1]); |
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105 | |||
106 | if (max_std_level >= 1) { |
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107 | cpuid(1, eax, ebx, ecx, std_caps); |
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108 | family = ((eax >> 8) & 0xf) + ((eax >> 20) & 0xff); |
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109 | model = ((eax >> 4) & 0xf) + ((eax >> 12) & 0xf0); |
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110 | if (std_caps & (1 << 15)) |
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111 | rval |= AV_CPU_FLAG_CMOV; |
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112 | if (std_caps & (1 << 23)) |
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113 | rval |= AV_CPU_FLAG_MMX; |
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114 | if (std_caps & (1 << 25)) |
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115 | rval |= AV_CPU_FLAG_MMXEXT; |
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116 | #if HAVE_SSE |
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117 | if (std_caps & (1 << 25)) |
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118 | rval |= AV_CPU_FLAG_SSE; |
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119 | if (std_caps & (1 << 26)) |
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120 | rval |= AV_CPU_FLAG_SSE2; |
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121 | if (ecx & 1) |
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122 | rval |= AV_CPU_FLAG_SSE3; |
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123 | if (ecx & 0x00000200 ) |
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124 | rval |= AV_CPU_FLAG_SSSE3; |
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125 | if (ecx & 0x00080000 ) |
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126 | rval |= AV_CPU_FLAG_SSE4; |
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127 | if (ecx & 0x00100000 ) |
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128 | rval |= AV_CPU_FLAG_SSE42; |
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129 | #if HAVE_AVX |
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130 | /* Check OXSAVE and AVX bits */ |
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131 | if ((ecx & 0x18000000) == 0x18000000) { |
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132 | /* Check for OS support */ |
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133 | xgetbv(0, eax, edx); |
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134 | if ((eax & 0x6) == 0x6) |
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135 | rval |= AV_CPU_FLAG_AVX; |
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136 | } |
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137 | #if HAVE_AVX2 |
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138 | if (max_std_level >= 7) { |
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139 | cpuid(7, eax, ebx, ecx, edx); |
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140 | if (ebx&0x00000020) |
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141 | rval |= AV_CPU_FLAG_AVX2; |
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142 | /* TODO: BMI1/2 */ |
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143 | } |
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144 | #endif /* HAVE_AVX2 */ |
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145 | #endif /* HAVE_AVX */ |
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146 | #endif /* HAVE_SSE */ |
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147 | } |
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148 | |||
149 | cpuid(0x80000000, max_ext_level, ebx, ecx, edx); |
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150 | |||
151 | if (max_ext_level >= 0x80000001) { |
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152 | cpuid(0x80000001, eax, ebx, ecx, ext_caps); |
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153 | if (ext_caps & (1U << 31)) |
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154 | rval |= AV_CPU_FLAG_3DNOW; |
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155 | if (ext_caps & (1 << 30)) |
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156 | rval |= AV_CPU_FLAG_3DNOWEXT; |
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157 | if (ext_caps & (1 << 23)) |
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158 | rval |= AV_CPU_FLAG_MMX; |
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159 | if (ext_caps & (1 << 22)) |
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160 | rval |= AV_CPU_FLAG_MMXEXT; |
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161 | |||
162 | /* Allow for selectively disabling SSE2 functions on AMD processors |
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163 | with SSE2 support but not SSE4a. This includes Athlon64, some |
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164 | Opteron, and some Sempron processors. MMX, SSE, or 3DNow! are faster |
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165 | than SSE2 often enough to utilize this special-case flag. |
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166 | AV_CPU_FLAG_SSE2 and AV_CPU_FLAG_SSE2SLOW are both set in this case |
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167 | so that SSE2 is used unless explicitly disabled by checking |
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168 | AV_CPU_FLAG_SSE2SLOW. */ |
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169 | if (!strncmp(vendor.c, "AuthenticAMD", 12) && |
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170 | rval & AV_CPU_FLAG_SSE2 && !(ecx & 0x00000040)) { |
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171 | rval |= AV_CPU_FLAG_SSE2SLOW; |
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172 | } |
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173 | |||
174 | /* XOP and FMA4 use the AVX instruction coding scheme, so they can't be |
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175 | * used unless the OS has AVX support. */ |
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176 | if (rval & AV_CPU_FLAG_AVX) { |
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177 | if (ecx & 0x00000800) |
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178 | rval |= AV_CPU_FLAG_XOP; |
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179 | if (ecx & 0x00010000) |
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180 | rval |= AV_CPU_FLAG_FMA4; |
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181 | } |
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182 | } |
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183 | |||
184 | if (!strncmp(vendor.c, "GenuineIntel", 12)) { |
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185 | if (family == 6 && (model == 9 || model == 13 || model == 14)) { |
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186 | /* 6/9 (pentium-m "banias"), 6/13 (pentium-m "dothan"), and |
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187 | * 6/14 (core1 "yonah") theoretically support sse2, but it's |
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188 | * usually slower than mmx, so let's just pretend they don't. |
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189 | * AV_CPU_FLAG_SSE2 is disabled and AV_CPU_FLAG_SSE2SLOW is |
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190 | * enabled so that SSE2 is not used unless explicitly enabled |
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191 | * by checking AV_CPU_FLAG_SSE2SLOW. The same situation |
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192 | * applies for AV_CPU_FLAG_SSE3 and AV_CPU_FLAG_SSE3SLOW. */ |
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193 | if (rval & AV_CPU_FLAG_SSE2) |
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194 | rval ^= AV_CPU_FLAG_SSE2SLOW | AV_CPU_FLAG_SSE2; |
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195 | if (rval & AV_CPU_FLAG_SSE3) |
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196 | rval ^= AV_CPU_FLAG_SSE3SLOW | AV_CPU_FLAG_SSE3; |
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197 | } |
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198 | /* The Atom processor has SSSE3 support, which is useful in many cases, |
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199 | * but sometimes the SSSE3 version is slower than the SSE2 equivalent |
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200 | * on the Atom, but is generally faster on other processors supporting |
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201 | * SSSE3. This flag allows for selectively disabling certain SSSE3 |
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202 | * functions on the Atom. */ |
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203 | if (family == 6 && model == 28) |
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204 | rval |= AV_CPU_FLAG_ATOM; |
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205 | } |
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206 | |||
207 | #endif /* cpuid */ |
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208 | |||
209 | return rval; |
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210 | }><>><>><>><>><>><>><>><>><> |