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4358 | Serge | 1 | /************************************************************************** |
2 | |||
3 | Copyright 2000, 2001 ATI Technologies Inc., Ontario, Canada, and |
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4 | VA Linux Systems Inc., Fremont, California. |
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5 | |||
6 | All Rights Reserved. |
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7 | |||
8 | Permission is hereby granted, free of charge, to any person obtaining |
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9 | a copy of this software and associated documentation files (the |
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10 | "Software"), to deal in the Software without restriction, including |
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11 | without limitation the rights to use, copy, modify, merge, publish, |
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12 | distribute, sublicense, and/or sell copies of the Software, and to |
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13 | permit persons to whom the Software is furnished to do so, subject to |
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14 | the following conditions: |
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15 | |||
16 | The above copyright notice and this permission notice (including the |
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17 | next paragraph) shall be included in all copies or substantial |
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18 | portions of the Software. |
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19 | |||
20 | THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, |
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21 | EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF |
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22 | MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. |
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23 | IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE |
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24 | LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION |
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25 | OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION |
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26 | WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. |
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27 | |||
28 | **************************************************************************/ |
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29 | |||
30 | /* |
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31 | * Authors: |
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32 | * Kevin E. Martin |
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33 | * Gareth Hughes |
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34 | */ |
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35 | |||
36 | #ifndef __RADEON_IOCTL_H__ |
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37 | #define __RADEON_IOCTL_H__ |
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38 | |||
39 | #include "main/simple_list.h" |
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40 | #include "radeon_bo_gem.h" |
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41 | #include "radeon_cs_gem.h" |
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42 | |||
43 | extern void radeonEmitVertexAOS( r100ContextPtr rmesa, |
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44 | GLuint vertex_size, |
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45 | struct radeon_bo *bo, |
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46 | GLuint offset ); |
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47 | |||
48 | extern void radeonEmitVbufPrim( r100ContextPtr rmesa, |
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49 | GLuint vertex_format, |
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50 | GLuint primitive, |
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51 | GLuint vertex_nr ); |
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52 | |||
53 | extern void radeonFlushElts( struct gl_context *ctx ); |
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54 | |||
55 | |||
56 | extern GLushort *radeonAllocEltsOpenEnded( r100ContextPtr rmesa, |
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57 | GLuint vertex_format, |
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58 | GLuint primitive, |
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59 | GLuint min_nr ); |
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60 | |||
61 | |||
62 | extern void radeonEmitAOS( r100ContextPtr rmesa, |
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63 | GLuint n, |
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64 | GLuint offset ); |
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65 | |||
66 | extern void radeonEmitBlit( r100ContextPtr rmesa, |
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67 | GLuint color_fmt, |
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68 | GLuint src_pitch, |
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69 | GLuint src_offset, |
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70 | GLuint dst_pitch, |
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71 | GLuint dst_offset, |
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72 | GLint srcx, GLint srcy, |
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73 | GLint dstx, GLint dsty, |
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74 | GLuint w, GLuint h ); |
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75 | |||
76 | extern void radeonEmitWait( r100ContextPtr rmesa, GLuint flags ); |
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77 | |||
78 | extern void radeonFlushCmdBuf( r100ContextPtr rmesa, const char * ); |
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79 | |||
80 | extern void radeonFlush( struct gl_context *ctx ); |
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81 | extern void radeonFinish( struct gl_context *ctx ); |
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82 | extern void radeonInitIoctlFuncs( struct gl_context *ctx ); |
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83 | extern void radeonGetAllParams( r100ContextPtr rmesa ); |
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84 | extern void radeonSetUpAtomList( r100ContextPtr rmesa ); |
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85 | |||
86 | /* ================================================================ |
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87 | * Helper macros: |
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88 | */ |
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89 | |||
90 | /* Close off the last primitive, if it exists. |
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91 | */ |
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92 | #define RADEON_NEWPRIM( rmesa ) \ |
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93 | do { \ |
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94 | if ( rmesa->radeon.dma.flush ) \ |
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95 | rmesa->radeon.dma.flush( &rmesa->radeon.glCtx ); \ |
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96 | } while (0) |
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97 | |||
98 | /* Can accomodate several state changes and primitive changes without |
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99 | * actually firing the buffer. |
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100 | */ |
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101 | |||
102 | #define RADEON_STATECHANGE( rmesa, ATOM ) \ |
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103 | do { \ |
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104 | RADEON_NEWPRIM( rmesa ); \ |
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105 | rmesa->hw.ATOM.dirty = GL_TRUE; \ |
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106 | rmesa->radeon.hw.is_dirty = GL_TRUE; \ |
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107 | } while (0) |
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108 | |||
109 | #define RADEON_DB_STATE( ATOM ) \ |
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110 | memcpy( rmesa->hw.ATOM.lastcmd, rmesa->hw.ATOM.cmd, \ |
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111 | rmesa->hw.ATOM.cmd_size * 4) |
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112 | |||
113 | static INLINE int RADEON_DB_STATECHANGE(r100ContextPtr rmesa, |
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114 | struct radeon_state_atom *atom ) |
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115 | { |
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116 | if (memcmp(atom->cmd, atom->lastcmd, atom->cmd_size*4)) { |
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117 | GLuint *tmp; |
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118 | RADEON_NEWPRIM( rmesa ); |
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119 | atom->dirty = GL_TRUE; |
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120 | rmesa->radeon.hw.is_dirty = GL_TRUE; |
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121 | tmp = atom->cmd; |
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122 | atom->cmd = atom->lastcmd; |
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123 | atom->lastcmd = tmp; |
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124 | return 1; |
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125 | } |
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126 | else |
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127 | return 0; |
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128 | } |
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129 | |||
130 | /* Command lengths. Note that any time you ensure ELTS_BUFSZ or VBUF_BUFSZ |
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131 | * are available, you will also be adding an rmesa->state.max_state_size because |
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132 | * r200EmitState is called from within r200EmitVbufPrim and r200FlushElts. |
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133 | */ |
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134 | #if RADEON_OLD_PACKETS |
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135 | #define AOS_BUFSZ(nr) ((3 + ((nr / 2) * 3) + ((nr & 1) * 2))+nr*2) |
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136 | #define VERT_AOS_BUFSZ (0) |
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137 | #define ELTS_BUFSZ(nr) (24 + nr * 2) |
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138 | #define VBUF_BUFSZ (8) |
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139 | #else |
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140 | #define AOS_BUFSZ(nr) ((3 + ((nr / 2) * 3) + ((nr & 1) * 2) + nr*2)) |
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141 | #define VERT_AOS_BUFSZ (5) |
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142 | #define ELTS_BUFSZ(nr) (16 + nr * 2) |
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143 | #define VBUF_BUFSZ (4) |
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144 | #endif |
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145 | #define SCISSOR_BUFSZ (8) |
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146 | #define INDEX_BUFSZ (7) |
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147 | |||
148 | |||
149 | static inline uint32_t cmdpacket3(int cmd_type) |
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150 | { |
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151 | drm_radeon_cmd_header_t cmd; |
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152 | |||
153 | cmd.i = 0; |
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154 | cmd.header.cmd_type = cmd_type; |
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155 | |||
156 | return (uint32_t)cmd.i; |
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157 | |||
158 | } |
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159 | |||
160 | #define OUT_BATCH_PACKET3(packet, num_extra) do { \ |
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161 | OUT_BATCH(CP_PACKET2); \ |
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162 | OUT_BATCH(CP_PACKET3((packet), (num_extra))); \ |
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163 | } while(0) |
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164 | |||
165 | #define OUT_BATCH_PACKET3_CLIP(packet, num_extra) do { \ |
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166 | OUT_BATCH(CP_PACKET2); \ |
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167 | OUT_BATCH(CP_PACKET3((packet), (num_extra))); \ |
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168 | } while(0) |
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169 | |||
170 | |||
171 | #endif /* __RADEON_IOCTL_H__ */ |