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| Rev | Author | Line No. | Line |
|---|---|---|---|
| 4358 | Serge | 1 | /************************************************************************** |
| 2 | * |
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| 3 | * Copyright 2004 David Airlie |
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| 4 | * All Rights Reserved. |
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| 5 | * |
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| 6 | * Permission is hereby granted, free of charge, to any person obtaining a |
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| 7 | * copy of this software and associated documentation files (the |
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| 8 | * "Software"), to deal in the Software without restriction, including |
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| 9 | * without limitation the rights to use, copy, modify, merge, publish, |
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| 10 | * distribute, sub license, and/or sell copies of the Software, and to |
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| 11 | * permit persons to whom the Software is furnished to do so, subject to |
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| 12 | * the following conditions: |
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| 13 | * |
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| 14 | * The above copyright notice and this permission notice (including the |
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| 15 | * next paragraph) shall be included in all copies or substantial portions |
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| 16 | * of the Software. |
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| 17 | * |
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| 18 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS |
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| 19 | * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF |
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| 20 | * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. |
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| 21 | * IN NO EVENT SHALL DAVID AIRLIE AND/OR ITS SUPPLIERS BE LIABLE FOR |
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| 22 | * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, |
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| 23 | * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE |
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| 24 | * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. |
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| 25 | * |
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| 26 | **************************************************************************/ |
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| 27 | |||
| 28 | #include "main/glheader.h" |
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| 29 | #include "main/atifragshader.h" |
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| 30 | #include "main/macros.h" |
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| 31 | #include "main/enums.h" |
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| 32 | #include "tnl/t_context.h" |
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| 33 | #include "program/program.h" |
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| 34 | #include "r200_context.h" |
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| 35 | #include "r200_ioctl.h" |
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| 36 | #include "r200_tex.h" |
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| 37 | |||
| 38 | #define SET_INST(inst, type) afs_cmd[((inst<<2) + (type<<1) + 1)] |
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| 39 | #define SET_INST_2(inst, type) afs_cmd[((inst<<2) + (type<<1) + 2)] |
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| 40 | |||
| 41 | static void r200SetFragShaderArg( GLuint *afs_cmd, GLuint opnum, GLuint optype, |
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| 42 | const struct atifragshader_src_register srcReg, |
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| 43 | GLuint argPos, GLuint *tfactor ) |
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| 44 | { |
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| 45 | const GLuint index = srcReg.Index; |
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| 46 | const GLuint srcmod = srcReg.argMod; |
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| 47 | const GLuint srcrep = srcReg.argRep; |
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| 48 | GLuint reg0 = 0; |
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| 49 | GLuint reg2 = 0; |
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| 50 | GLuint useOddSrc = 0; |
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| 51 | |||
| 52 | switch(srcrep) { |
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| 53 | case GL_RED: |
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| 54 | reg2 |= R200_TXC_REPL_RED << (R200_TXC_REPL_ARG_A_SHIFT + (2*argPos)); |
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| 55 | if (optype) |
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| 56 | useOddSrc = 1; |
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| 57 | break; |
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| 58 | case GL_GREEN: |
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| 59 | reg2 |= R200_TXC_REPL_GREEN << (R200_TXC_REPL_ARG_A_SHIFT + (2*argPos)); |
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| 60 | if (optype) |
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| 61 | useOddSrc = 1; |
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| 62 | break; |
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| 63 | case GL_BLUE: |
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| 64 | if (!optype) |
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| 65 | reg2 |= R200_TXC_REPL_BLUE << (R200_TXC_REPL_ARG_A_SHIFT + (2*argPos)); |
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| 66 | else |
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| 67 | useOddSrc = 1; |
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| 68 | break; |
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| 69 | case GL_ALPHA: |
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| 70 | if (!optype) |
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| 71 | useOddSrc = 1; |
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| 72 | break; |
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| 73 | } |
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| 74 | |||
| 75 | if (index >= GL_REG_0_ATI && index <= GL_REG_5_ATI) |
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| 76 | reg0 |= (((index - GL_REG_0_ATI)*2) + 10 + useOddSrc) << (5*argPos); |
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| 77 | else if (index >= GL_CON_0_ATI && index <= GL_CON_7_ATI) { |
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| 78 | if ((*tfactor == 0) || (index == *tfactor)) { |
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| 79 | reg0 |= (R200_TXC_ARG_A_TFACTOR_COLOR + useOddSrc) << (5*argPos); |
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| 80 | reg2 |= (index - GL_CON_0_ATI) << R200_TXC_TFACTOR_SEL_SHIFT; |
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| 81 | *tfactor = index; |
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| 82 | } |
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| 83 | else { |
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| 84 | reg0 |= (R200_TXC_ARG_A_TFACTOR1_COLOR + useOddSrc) << (5*argPos); |
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| 85 | reg2 |= (index - GL_CON_0_ATI) << R200_TXC_TFACTOR1_SEL_SHIFT; |
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| 86 | } |
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| 87 | } |
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| 88 | else if (index == GL_PRIMARY_COLOR_EXT) { |
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| 89 | reg0 |= (R200_TXC_ARG_A_DIFFUSE_COLOR + useOddSrc) << (5*argPos); |
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| 90 | } |
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| 91 | else if (index == GL_SECONDARY_INTERPOLATOR_ATI) { |
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| 92 | reg0 |= (R200_TXC_ARG_A_SPECULAR_COLOR + useOddSrc) << (5*argPos); |
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| 93 | } |
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| 94 | /* GL_ZERO is a noop, for GL_ONE we set the complement */ |
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| 95 | else if (index == GL_ONE) { |
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| 96 | reg0 |= R200_TXC_COMP_ARG_A << (4*argPos); |
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| 97 | } |
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| 98 | |||
| 99 | if (srcmod & GL_COMP_BIT_ATI) |
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| 100 | reg0 ^= R200_TXC_COMP_ARG_A << (4*argPos); |
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| 101 | if (srcmod & GL_BIAS_BIT_ATI) |
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| 102 | reg0 |= R200_TXC_BIAS_ARG_A << (4*argPos); |
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| 103 | if (srcmod & GL_2X_BIT_ATI) |
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| 104 | reg0 |= R200_TXC_SCALE_ARG_A << (4*argPos); |
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| 105 | if (srcmod & GL_NEGATE_BIT_ATI) |
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| 106 | reg0 ^= R200_TXC_NEG_ARG_A << (4*argPos); |
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| 107 | |||
| 108 | SET_INST(opnum, optype) |= reg0; |
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| 109 | SET_INST_2(opnum, optype) |= reg2; |
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| 110 | } |
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| 111 | |||
| 112 | static GLuint dstmask_table[8] = |
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| 113 | { |
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| 114 | R200_TXC_OUTPUT_MASK_RGB, |
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| 115 | R200_TXC_OUTPUT_MASK_R, |
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| 116 | R200_TXC_OUTPUT_MASK_G, |
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| 117 | R200_TXC_OUTPUT_MASK_RG, |
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| 118 | R200_TXC_OUTPUT_MASK_B, |
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| 119 | R200_TXC_OUTPUT_MASK_RB, |
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| 120 | R200_TXC_OUTPUT_MASK_GB, |
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| 121 | R200_TXC_OUTPUT_MASK_RGB |
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| 122 | }; |
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| 123 | |||
| 124 | static void r200UpdateFSArith( struct gl_context *ctx ) |
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| 125 | { |
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| 126 | r200ContextPtr rmesa = R200_CONTEXT(ctx); |
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| 127 | GLuint *afs_cmd; |
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| 128 | const struct ati_fragment_shader *shader = ctx->ATIFragmentShader.Current; |
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| 129 | GLuint pass; |
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| 130 | |||
| 131 | R200_STATECHANGE( rmesa, afs[0] ); |
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| 132 | R200_STATECHANGE( rmesa, afs[1] ); |
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| 133 | |||
| 134 | if (shader->NumPasses < 2) { |
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| 135 | afs_cmd = (GLuint *) rmesa->hw.afs[1].cmd; |
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| 136 | } |
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| 137 | else { |
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| 138 | afs_cmd = (GLuint *) rmesa->hw.afs[0].cmd; |
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| 139 | } |
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| 140 | for (pass = 0; pass < shader->NumPasses; pass++) { |
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| 141 | GLuint opnum = 0; |
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| 142 | GLuint pc; |
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| 143 | for (pc = 0; pc < shader->numArithInstr[pass]; pc++) { |
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| 144 | GLuint optype; |
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| 145 | struct atifs_instruction *inst = &shader->Instructions[pass][pc]; |
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| 146 | |||
| 147 | SET_INST(opnum, 0) = 0; |
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| 148 | SET_INST_2(opnum, 0) = 0; |
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| 149 | SET_INST(opnum, 1) = 0; |
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| 150 | SET_INST_2(opnum, 1) = 0; |
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| 151 | |||
| 152 | for (optype = 0; optype < 2; optype++) { |
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| 153 | GLuint tfactor = 0; |
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| 154 | |||
| 155 | if (inst->Opcode[optype]) { |
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| 156 | switch (inst->Opcode[optype]) { |
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| 157 | /* these are all MADD in disguise |
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| 158 | MADD is A * B + C |
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| 159 | so for GL_ADD use arg B/C and make A complement 0 |
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| 160 | for GL_SUB use arg B/C, negate C and make A complement 0 |
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| 161 | for GL_MOV use arg C |
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| 162 | for GL_MUL use arg A |
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| 163 | for GL_MAD all good */ |
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| 164 | case GL_SUB_ATI: |
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| 165 | /* negate C */ |
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| 166 | SET_INST(opnum, optype) |= R200_TXC_NEG_ARG_C; |
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| 167 | /* fallthrough */ |
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| 168 | case GL_ADD_ATI: |
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| 169 | r200SetFragShaderArg(afs_cmd, opnum, optype, |
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| 170 | inst->SrcReg[optype][0], 1, &tfactor); |
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| 171 | r200SetFragShaderArg(afs_cmd, opnum, optype, |
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| 172 | inst->SrcReg[optype][1], 2, &tfactor); |
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| 173 | /* A = complement 0 */ |
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| 174 | SET_INST(opnum, optype) |= R200_TXC_COMP_ARG_A; |
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| 175 | SET_INST(opnum, optype) |= R200_TXC_OP_MADD; |
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| 176 | break; |
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| 177 | case GL_MOV_ATI: |
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| 178 | /* put arg0 in C */ |
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| 179 | r200SetFragShaderArg(afs_cmd, opnum, optype, |
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| 180 | inst->SrcReg[optype][0], 2, &tfactor); |
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| 181 | SET_INST(opnum, optype) |= R200_TXC_OP_MADD; |
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| 182 | break; |
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| 183 | case GL_MAD_ATI: |
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| 184 | r200SetFragShaderArg(afs_cmd, opnum, optype, |
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| 185 | inst->SrcReg[optype][2], 2, &tfactor); |
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| 186 | /* fallthrough */ |
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| 187 | case GL_MUL_ATI: |
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| 188 | r200SetFragShaderArg(afs_cmd, opnum, optype, |
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| 189 | inst->SrcReg[optype][0], 0, &tfactor); |
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| 190 | r200SetFragShaderArg(afs_cmd, opnum, optype, |
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| 191 | inst->SrcReg[optype][1], 1, &tfactor); |
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| 192 | SET_INST(opnum, optype) |= R200_TXC_OP_MADD; |
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| 193 | break; |
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| 194 | case GL_LERP_ATI: |
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| 195 | /* arg order is not native chip order, swap A and C */ |
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| 196 | r200SetFragShaderArg(afs_cmd, opnum, optype, |
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| 197 | inst->SrcReg[optype][0], 2, &tfactor); |
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| 198 | r200SetFragShaderArg(afs_cmd, opnum, optype, |
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| 199 | inst->SrcReg[optype][1], 1, &tfactor); |
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| 200 | r200SetFragShaderArg(afs_cmd, opnum, optype, |
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| 201 | inst->SrcReg[optype][2], 0, &tfactor); |
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| 202 | SET_INST(opnum, optype) |= R200_TXC_OP_LERP; |
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| 203 | break; |
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| 204 | case GL_CND_ATI: |
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| 205 | r200SetFragShaderArg(afs_cmd, opnum, optype, |
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| 206 | inst->SrcReg[optype][0], 0, &tfactor); |
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| 207 | r200SetFragShaderArg(afs_cmd, opnum, optype, |
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| 208 | inst->SrcReg[optype][1], 1, &tfactor); |
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| 209 | r200SetFragShaderArg(afs_cmd, opnum, optype, |
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| 210 | inst->SrcReg[optype][2], 2, &tfactor); |
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| 211 | SET_INST(opnum, optype) |= R200_TXC_OP_CONDITIONAL; |
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| 212 | break; |
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| 213 | case GL_CND0_ATI: |
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| 214 | r200SetFragShaderArg(afs_cmd, opnum, optype, |
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| 215 | inst->SrcReg[optype][0], 0, &tfactor); |
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| 216 | r200SetFragShaderArg(afs_cmd, opnum, optype, |
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| 217 | inst->SrcReg[optype][1], 1, &tfactor); |
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| 218 | r200SetFragShaderArg(afs_cmd, opnum, optype, |
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| 219 | inst->SrcReg[optype][2], 2, &tfactor); |
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| 220 | SET_INST(opnum, optype) |= R200_TXC_OP_CND0; |
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| 221 | break; |
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| 222 | /* cannot specify dot ops as alpha ops directly */ |
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| 223 | case GL_DOT2_ADD_ATI: |
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| 224 | if (optype) |
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| 225 | SET_INST_2(opnum, 1) |= R200_TXA_DOT_ALPHA; |
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| 226 | else { |
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| 227 | r200SetFragShaderArg(afs_cmd, opnum, 0, |
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| 228 | inst->SrcReg[0][0], 0, &tfactor); |
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| 229 | r200SetFragShaderArg(afs_cmd, opnum, 0, |
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| 230 | inst->SrcReg[0][1], 1, &tfactor); |
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| 231 | r200SetFragShaderArg(afs_cmd, opnum, 0, |
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| 232 | inst->SrcReg[0][2], 2, &tfactor); |
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| 233 | SET_INST(opnum, 0) |= R200_TXC_OP_DOT2_ADD; |
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| 234 | } |
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| 235 | break; |
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| 236 | case GL_DOT3_ATI: |
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| 237 | if (optype) |
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| 238 | SET_INST_2(opnum, 1) |= R200_TXA_DOT_ALPHA; |
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| 239 | else { |
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| 240 | r200SetFragShaderArg(afs_cmd, opnum, 0, |
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| 241 | inst->SrcReg[0][0], 0, &tfactor); |
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| 242 | r200SetFragShaderArg(afs_cmd, opnum, 0, |
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| 243 | inst->SrcReg[0][1], 1, &tfactor); |
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| 244 | SET_INST(opnum, 0) |= R200_TXC_OP_DOT3; |
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| 245 | } |
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| 246 | break; |
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| 247 | case GL_DOT4_ATI: |
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| 248 | /* experimental verification: for dot4 setup of alpha args is needed |
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| 249 | (dstmod is ignored, though, so dot2/dot3 should be safe) |
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| 250 | the hardware apparently does R1*R2 + G1*G2 + B1*B2 + A3*A4 |
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| 251 | but the API doesn't allow it */ |
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| 252 | if (optype) |
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| 253 | SET_INST_2(opnum, 1) |= R200_TXA_DOT_ALPHA; |
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| 254 | else { |
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| 255 | r200SetFragShaderArg(afs_cmd, opnum, 0, |
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| 256 | inst->SrcReg[0][0], 0, &tfactor); |
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| 257 | r200SetFragShaderArg(afs_cmd, opnum, 0, |
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| 258 | inst->SrcReg[0][1], 1, &tfactor); |
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| 259 | r200SetFragShaderArg(afs_cmd, opnum, 1, |
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| 260 | inst->SrcReg[0][0], 0, &tfactor); |
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| 261 | r200SetFragShaderArg(afs_cmd, opnum, 1, |
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| 262 | inst->SrcReg[0][1], 1, &tfactor); |
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| 263 | SET_INST(opnum, optype) |= R200_TXC_OP_DOT4; |
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| 264 | } |
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| 265 | break; |
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| 266 | } |
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| 267 | } |
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| 268 | |||
| 269 | /* destination */ |
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| 270 | if (inst->DstReg[optype].Index) { |
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| 271 | GLuint dstreg = inst->DstReg[optype].Index - GL_REG_0_ATI; |
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| 272 | GLuint dstmask = inst->DstReg[optype].dstMask; |
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| 273 | GLuint sat = inst->DstReg[optype].dstMod & GL_SATURATE_BIT_ATI; |
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| 274 | GLuint dstmod = inst->DstReg[optype].dstMod; |
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| 275 | |||
| 276 | dstmod &= ~GL_SATURATE_BIT_ATI; |
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| 277 | |||
| 278 | SET_INST_2(opnum, optype) |= (dstreg + 1) << R200_TXC_OUTPUT_REG_SHIFT; |
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| 279 | SET_INST_2(opnum, optype) |= dstmask_table[dstmask]; |
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| 280 | |||
| 281 | /* fglrx does clamp the last instructions to 0_1 it seems */ |
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| 282 | /* this won't necessarily catch the last instruction |
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| 283 | which writes to reg0 */ |
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| 284 | if (sat || (pc == (shader->numArithInstr[pass] - 1) && |
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| 285 | ((pass == 1) || (shader->NumPasses == 1)))) |
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| 286 | SET_INST_2(opnum, optype) |= R200_TXC_CLAMP_0_1; |
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| 287 | else |
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| 288 | /*should we clamp or not? spec is vague, I would suppose yes but fglrx doesn't */ |
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| 289 | SET_INST_2(opnum, optype) |= R200_TXC_CLAMP_8_8; |
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| 290 | /* SET_INST_2(opnum, optype) |= R200_TXC_CLAMP_WRAP;*/ |
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| 291 | switch(dstmod) { |
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| 292 | case GL_2X_BIT_ATI: |
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| 293 | SET_INST_2(opnum, optype) |= R200_TXC_SCALE_2X; |
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| 294 | break; |
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| 295 | case GL_4X_BIT_ATI: |
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| 296 | SET_INST_2(opnum, optype) |= R200_TXC_SCALE_4X; |
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| 297 | break; |
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| 298 | case GL_8X_BIT_ATI: |
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| 299 | SET_INST_2(opnum, optype) |= R200_TXC_SCALE_8X; |
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| 300 | break; |
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| 301 | case GL_HALF_BIT_ATI: |
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| 302 | SET_INST_2(opnum, optype) |= R200_TXC_SCALE_INV2; |
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| 303 | break; |
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| 304 | case GL_QUARTER_BIT_ATI: |
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| 305 | SET_INST_2(opnum, optype) |= R200_TXC_SCALE_INV4; |
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| 306 | break; |
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| 307 | case GL_EIGHTH_BIT_ATI: |
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| 308 | SET_INST_2(opnum, optype) |= R200_TXC_SCALE_INV8; |
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| 309 | break; |
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| 310 | default: |
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| 311 | break; |
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| 312 | } |
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| 313 | } |
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| 314 | } |
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| 315 | /* fprintf(stderr, "pass %d nr %d inst 0x%.8x 0x%.8x 0x%.8x 0x%.8x\n", |
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| 316 | pass, opnum, SET_INST(opnum, 0), SET_INST_2(opnum, 0), |
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| 317 | SET_INST(opnum, 1), SET_INST_2(opnum, 1));*/ |
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| 318 | opnum++; |
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| 319 | } |
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| 320 | afs_cmd = (GLuint *) rmesa->hw.afs[1].cmd; |
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| 321 | } |
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| 322 | rmesa->afs_loaded = ctx->ATIFragmentShader.Current; |
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| 323 | } |
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| 324 | |||
| 325 | static void r200UpdateFSRouting( struct gl_context *ctx ) { |
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| 326 | r200ContextPtr rmesa = R200_CONTEXT(ctx); |
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| 327 | const struct ati_fragment_shader *shader = ctx->ATIFragmentShader.Current; |
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| 328 | GLuint reg; |
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| 329 | |||
| 330 | R200_STATECHANGE( rmesa, ctx ); |
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| 331 | R200_STATECHANGE( rmesa, cst ); |
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| 332 | |||
| 333 | for (reg = 0; reg < R200_MAX_TEXTURE_UNITS; reg++) { |
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| 334 | if (shader->swizzlerq & (1 << (2 * reg))) |
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| 335 | /* r coord */ |
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| 336 | set_re_cntl_d3d( ctx, reg, 1); |
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| 337 | /* q coord */ |
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| 338 | else set_re_cntl_d3d( ctx, reg, 0); |
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| 339 | } |
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| 340 | |||
| 341 | rmesa->hw.ctx.cmd[CTX_PP_CNTL] &= ~(R200_MULTI_PASS_ENABLE | |
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| 342 | R200_TEX_BLEND_ENABLE_MASK | |
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| 343 | R200_TEX_ENABLE_MASK); |
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| 344 | rmesa->hw.cst.cmd[CST_PP_CNTL_X] &= ~(R200_PPX_PFS_INST_ENABLE_MASK | |
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| 345 | R200_PPX_TEX_ENABLE_MASK | |
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| 346 | R200_PPX_OUTPUT_REG_MASK); |
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| 347 | |||
| 348 | /* first pass registers use slots 8 - 15 |
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| 349 | but single pass shaders use slots 0 - 7 */ |
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| 350 | if (shader->NumPasses < 2) { |
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| 351 | rmesa->hw.ctx.cmd[CTX_PP_CNTL] |= shader->numArithInstr[0] == 8 ? |
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| 352 | 0xff << (R200_TEX_BLEND_0_ENABLE_SHIFT - 1) : |
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| 353 | (0xff >> (8 - shader->numArithInstr[0])) << R200_TEX_BLEND_0_ENABLE_SHIFT; |
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| 354 | } else { |
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| 355 | rmesa->hw.ctx.cmd[CTX_PP_CNTL] |= R200_MULTI_PASS_ENABLE; |
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| 356 | rmesa->hw.ctx.cmd[CTX_PP_CNTL] |= shader->numArithInstr[1] == 8 ? |
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| 357 | 0xff << (R200_TEX_BLEND_0_ENABLE_SHIFT - 1) : |
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| 358 | (0xff >> (8 - shader->numArithInstr[1])) << R200_TEX_BLEND_0_ENABLE_SHIFT; |
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| 359 | rmesa->hw.cst.cmd[CST_PP_CNTL_X] |= |
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| 360 | (0xff >> (8 - shader->numArithInstr[0])) << R200_PPX_FPS_INST0_ENABLE_SHIFT; |
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| 361 | } |
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| 362 | |||
| 363 | if (shader->NumPasses < 2) { |
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| 364 | for (reg = 0; reg < R200_MAX_TEXTURE_UNITS; reg++) { |
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| 365 | GLbitfield targetbit = ctx->Texture.Unit[reg]._ReallyEnabled; |
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| 366 | R200_STATECHANGE( rmesa, tex[reg] ); |
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| 367 | rmesa->hw.tex[reg].cmd[TEX_PP_TXMULTI_CTL] = 0; |
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| 368 | if (shader->SetupInst[0][reg].Opcode) { |
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| 369 | GLuint txformat = rmesa->hw.tex[reg].cmd[TEX_PP_TXFORMAT] |
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| 370 | & ~(R200_TXFORMAT_ST_ROUTE_MASK | R200_TXFORMAT_LOOKUP_DISABLE); |
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| 371 | GLuint txformat_x = rmesa->hw.tex[reg].cmd[TEX_PP_TXFORMAT_X] & ~R200_TEXCOORD_MASK; |
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| 372 | txformat |= (shader->SetupInst[0][reg].src - GL_TEXTURE0_ARB) |
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| 373 | << R200_TXFORMAT_ST_ROUTE_SHIFT; |
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| 374 | /* fix up texcoords for proj/non-proj 2d (3d and cube are not defined when |
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| 375 | using projection so don't have to worry there). |
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| 376 | When passing coords, need R200_TEXCOORD_VOLUME, otherwise loose a coord */ |
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| 377 | /* FIXME: someone might rely on default tex coords r/q, which we unfortunately |
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| 378 | don't provide (we have the same problem without shaders) */ |
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| 379 | if (shader->SetupInst[0][reg].Opcode == ATI_FRAGMENT_SHADER_PASS_OP) { |
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| 380 | txformat |= R200_TXFORMAT_LOOKUP_DISABLE; |
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| 381 | if (shader->SetupInst[0][reg].swizzle == GL_SWIZZLE_STR_ATI || |
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| 382 | shader->SetupInst[0][reg].swizzle == GL_SWIZZLE_STQ_ATI) { |
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| 383 | txformat_x |= R200_TEXCOORD_VOLUME; |
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| 384 | } |
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| 385 | else { |
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| 386 | txformat_x |= R200_TEXCOORD_PROJ; |
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| 387 | } |
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| 388 | rmesa->hw.ctx.cmd[CTX_PP_CNTL] |= R200_TEX_0_ENABLE << reg; |
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| 389 | } |
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| 390 | else if (targetbit == TEXTURE_3D_BIT) { |
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| 391 | txformat_x |= R200_TEXCOORD_VOLUME; |
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| 392 | } |
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| 393 | else if (targetbit == TEXTURE_CUBE_BIT) { |
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| 394 | txformat_x |= R200_TEXCOORD_CUBIC_ENV; |
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| 395 | } |
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| 396 | else if (shader->SetupInst[0][reg].swizzle == GL_SWIZZLE_STR_ATI || |
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| 397 | shader->SetupInst[0][reg].swizzle == GL_SWIZZLE_STQ_ATI) { |
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| 398 | txformat_x |= R200_TEXCOORD_NONPROJ; |
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| 399 | } |
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| 400 | else { |
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| 401 | txformat_x |= R200_TEXCOORD_PROJ; |
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| 402 | } |
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| 403 | rmesa->hw.tex[reg].cmd[TEX_PP_TXFORMAT] = txformat; |
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| 404 | rmesa->hw.tex[reg].cmd[TEX_PP_TXFORMAT_X] = txformat_x; |
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| 405 | /* enabling texturing when unit isn't correctly configured may not be safe */ |
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| 406 | if (targetbit) |
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| 407 | rmesa->hw.ctx.cmd[CTX_PP_CNTL] |= R200_TEX_0_ENABLE << reg; |
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| 408 | } |
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| 409 | } |
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| 410 | |||
| 411 | } else { |
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| 412 | /* setup 1st pass */ |
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| 413 | for (reg = 0; reg < R200_MAX_TEXTURE_UNITS; reg++) { |
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| 414 | GLbitfield targetbit = ctx->Texture.Unit[reg]._ReallyEnabled; |
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| 415 | R200_STATECHANGE( rmesa, tex[reg] ); |
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| 416 | GLuint txformat_multi = 0; |
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| 417 | if (shader->SetupInst[0][reg].Opcode) { |
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| 418 | txformat_multi |= (shader->SetupInst[0][reg].src - GL_TEXTURE0_ARB) |
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| 419 | << R200_PASS1_ST_ROUTE_SHIFT; |
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| 420 | if (shader->SetupInst[0][reg].Opcode == ATI_FRAGMENT_SHADER_PASS_OP) { |
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| 421 | txformat_multi |= R200_PASS1_TXFORMAT_LOOKUP_DISABLE; |
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| 422 | if (shader->SetupInst[0][reg].swizzle == GL_SWIZZLE_STR_ATI || |
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| 423 | shader->SetupInst[0][reg].swizzle == GL_SWIZZLE_STQ_ATI) { |
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| 424 | txformat_multi |= R200_PASS1_TEXCOORD_VOLUME; |
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| 425 | } |
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| 426 | else { |
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| 427 | txformat_multi |= R200_PASS1_TEXCOORD_PROJ; |
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| 428 | } |
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| 429 | rmesa->hw.cst.cmd[CST_PP_CNTL_X] |= R200_PPX_TEX_0_ENABLE << reg; |
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| 430 | } |
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| 431 | else if (targetbit == TEXTURE_3D_BIT) { |
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| 432 | txformat_multi |= R200_PASS1_TEXCOORD_VOLUME; |
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| 433 | } |
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| 434 | else if (targetbit == TEXTURE_CUBE_BIT) { |
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| 435 | txformat_multi |= R200_PASS1_TEXCOORD_CUBIC_ENV; |
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| 436 | } |
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| 437 | else if (shader->SetupInst[0][reg].swizzle == GL_SWIZZLE_STR_ATI || |
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| 438 | shader->SetupInst[0][reg].swizzle == GL_SWIZZLE_STQ_ATI) { |
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| 439 | txformat_multi |= R200_PASS1_TEXCOORD_NONPROJ; |
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| 440 | } |
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| 441 | else { |
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| 442 | txformat_multi |= R200_PASS1_TEXCOORD_PROJ; |
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| 443 | } |
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| 444 | if (targetbit) |
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| 445 | rmesa->hw.cst.cmd[CST_PP_CNTL_X] |= R200_PPX_TEX_0_ENABLE << reg; |
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| 446 | } |
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| 447 | rmesa->hw.tex[reg].cmd[TEX_PP_TXMULTI_CTL] = txformat_multi; |
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| 448 | } |
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| 449 | |||
| 450 | /* setup 2nd pass */ |
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| 451 | for (reg=0; reg < R200_MAX_TEXTURE_UNITS; reg++) { |
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| 452 | GLbitfield targetbit = ctx->Texture.Unit[reg]._ReallyEnabled; |
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| 453 | if (shader->SetupInst[1][reg].Opcode) { |
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| 454 | GLuint coord = shader->SetupInst[1][reg].src; |
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| 455 | GLuint txformat = rmesa->hw.tex[reg].cmd[TEX_PP_TXFORMAT] |
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| 456 | & ~(R200_TXFORMAT_ST_ROUTE_MASK | R200_TXFORMAT_LOOKUP_DISABLE); |
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| 457 | GLuint txformat_x = rmesa->hw.tex[reg].cmd[TEX_PP_TXFORMAT_X] & ~R200_TEXCOORD_MASK; |
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| 458 | R200_STATECHANGE( rmesa, tex[reg] ); |
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| 459 | if (shader->SetupInst[1][reg].Opcode == ATI_FRAGMENT_SHADER_PASS_OP) { |
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| 460 | txformat |= R200_TXFORMAT_LOOKUP_DISABLE; |
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| 461 | txformat_x |= R200_TEXCOORD_VOLUME; |
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| 462 | if (shader->SetupInst[1][reg].swizzle == GL_SWIZZLE_STR_ATI || |
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| 463 | shader->SetupInst[1][reg].swizzle == GL_SWIZZLE_STQ_ATI) { |
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| 464 | txformat_x |= R200_TEXCOORD_VOLUME; |
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| 465 | } |
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| 466 | else { |
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| 467 | txformat_x |= R200_TEXCOORD_PROJ; |
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| 468 | } |
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| 469 | rmesa->hw.ctx.cmd[CTX_PP_CNTL] |= R200_TEX_0_ENABLE << reg; |
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| 470 | } |
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| 471 | else if (targetbit == TEXTURE_3D_BIT) { |
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| 472 | txformat_x |= R200_TEXCOORD_VOLUME; |
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| 473 | } |
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| 474 | else if (targetbit == TEXTURE_CUBE_BIT) { |
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| 475 | txformat_x |= R200_TEXCOORD_CUBIC_ENV; |
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| 476 | } |
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| 477 | else if (shader->SetupInst[1][reg].swizzle == GL_SWIZZLE_STR_ATI || |
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| 478 | shader->SetupInst[1][reg].swizzle == GL_SWIZZLE_STQ_ATI) { |
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| 479 | txformat_x |= R200_TEXCOORD_NONPROJ; |
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| 480 | } |
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| 481 | else { |
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| 482 | txformat_x |= R200_TEXCOORD_PROJ; |
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| 483 | } |
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| 484 | if (coord >= GL_REG_0_ATI) { |
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| 485 | GLuint txformat_multi = rmesa->hw.tex[reg].cmd[TEX_PP_TXMULTI_CTL]; |
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| 486 | txformat_multi |= (coord - GL_REG_0_ATI + 2) << R200_PASS2_COORDS_REG_SHIFT; |
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| 487 | rmesa->hw.tex[reg].cmd[TEX_PP_TXMULTI_CTL] = txformat_multi; |
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| 488 | rmesa->hw.cst.cmd[CST_PP_CNTL_X] |= 1 << |
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| 489 | (R200_PPX_OUTPUT_REG_0_SHIFT + coord - GL_REG_0_ATI); |
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| 490 | } else { |
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| 491 | txformat |= (coord - GL_TEXTURE0_ARB) << R200_TXFORMAT_ST_ROUTE_SHIFT; |
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| 492 | } |
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| 493 | rmesa->hw.tex[reg].cmd[TEX_PP_TXFORMAT_X] = txformat_x; |
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| 494 | rmesa->hw.tex[reg].cmd[TEX_PP_TXFORMAT] = txformat; |
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| 495 | if (targetbit) |
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| 496 | rmesa->hw.ctx.cmd[CTX_PP_CNTL] |= R200_TEX_0_ENABLE << reg; |
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| 497 | } |
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| 498 | } |
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| 499 | } |
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| 500 | } |
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| 501 | |||
| 502 | static void r200UpdateFSConstants( struct gl_context *ctx ) |
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| 503 | { |
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| 504 | r200ContextPtr rmesa = R200_CONTEXT(ctx); |
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| 505 | const struct ati_fragment_shader *shader = ctx->ATIFragmentShader.Current; |
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| 506 | GLuint i; |
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| 507 | |||
| 508 | /* update constants */ |
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| 509 | R200_STATECHANGE(rmesa, atf); |
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| 510 | for (i = 0; i < 8; i++) |
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| 511 | { |
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| 512 | GLubyte con_byte[4]; |
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| 513 | if ((shader->LocalConstDef >> i) & 1) { |
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| 514 | CLAMPED_FLOAT_TO_UBYTE(con_byte[0], shader->Constants[i][0]); |
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| 515 | CLAMPED_FLOAT_TO_UBYTE(con_byte[1], shader->Constants[i][1]); |
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| 516 | CLAMPED_FLOAT_TO_UBYTE(con_byte[2], shader->Constants[i][2]); |
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| 517 | CLAMPED_FLOAT_TO_UBYTE(con_byte[3], shader->Constants[i][3]); |
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| 518 | } |
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| 519 | else { |
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| 520 | CLAMPED_FLOAT_TO_UBYTE(con_byte[0], ctx->ATIFragmentShader.GlobalConstants[i][0]); |
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| 521 | CLAMPED_FLOAT_TO_UBYTE(con_byte[1], ctx->ATIFragmentShader.GlobalConstants[i][1]); |
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| 522 | CLAMPED_FLOAT_TO_UBYTE(con_byte[2], ctx->ATIFragmentShader.GlobalConstants[i][2]); |
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| 523 | CLAMPED_FLOAT_TO_UBYTE(con_byte[3], ctx->ATIFragmentShader.GlobalConstants[i][3]); |
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| 524 | } |
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| 525 | rmesa->hw.atf.cmd[ATF_TFACTOR_0 + i] = radeonPackColor ( |
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| 526 | 4, con_byte[0], con_byte[1], con_byte[2], con_byte[3] ); |
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| 527 | } |
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| 528 | } |
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| 529 | |||
| 530 | /* update routing, constants and arithmetic |
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| 531 | * constants need to be updated always (globals can change, no separate notification) |
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| 532 | * routing needs to be updated always too (non-shader code will overwrite state, plus |
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| 533 | * some of the routing depends on what sort of texture is bound) |
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| 534 | * for both of them, we need to update anyway because of disabling/enabling ati_fs which |
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| 535 | * we'd need to track otherwise |
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| 536 | * arithmetic is only updated if current shader changes (and probably the data should be |
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| 537 | * stored in some DriverData object attached to the mesa atifs object, i.e. binding a |
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| 538 | * shader wouldn't force us to "recompile" the shader). |
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| 539 | */ |
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| 540 | void r200UpdateFragmentShader( struct gl_context *ctx ) |
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| 541 | { |
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| 542 | r200ContextPtr rmesa = R200_CONTEXT(ctx); |
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| 543 | |||
| 544 | r200UpdateFSConstants( ctx ); |
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| 545 | r200UpdateFSRouting( ctx ); |
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| 546 | if (rmesa->afs_loaded != ctx->ATIFragmentShader.Current) |
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| 547 | r200UpdateFSArith( ctx ); |
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| 548 | } |