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Rev | Author | Line No. | Line |
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4358 | Serge | 1 | /* |
2 | Copyright (C) The Weather Channel, Inc. 2002. All Rights Reserved. |
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3 | |||
4 | The Weather Channel (TM) funded Tungsten Graphics to develop the |
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5 | initial release of the Radeon 8500 driver under the XFree86 license. |
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6 | This notice must be preserved. |
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7 | |||
8 | Permission is hereby granted, free of charge, to any person obtaining |
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9 | a copy of this software and associated documentation files (the |
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10 | "Software"), to deal in the Software without restriction, including |
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11 | without limitation the rights to use, copy, modify, merge, publish, |
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12 | distribute, sublicense, and/or sell copies of the Software, and to |
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13 | permit persons to whom the Software is furnished to do so, subject to |
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14 | the following conditions: |
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15 | |||
16 | The above copyright notice and this permission notice (including the |
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17 | next paragraph) shall be included in all copies or substantial |
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18 | portions of the Software. |
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19 | |||
20 | THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, |
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21 | EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF |
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22 | MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. |
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23 | IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE |
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24 | LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION |
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25 | OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION |
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26 | WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. |
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27 | |||
28 | **************************************************************************/ |
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29 | |||
30 | /* |
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31 | * Authors: |
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32 | * Keith Whitwell |
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33 | */ |
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34 | |||
35 | #ifndef __R200_CONTEXT_H__ |
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36 | #define __R200_CONTEXT_H__ |
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37 | |||
38 | #include "tnl/t_vertex.h" |
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39 | #include "drm.h" |
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40 | #include "radeon_drm.h" |
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41 | #include "dri_util.h" |
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42 | |||
43 | #include "main/macros.h" |
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44 | #include "main/mtypes.h" |
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45 | #include "main/colormac.h" |
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46 | #include "r200_reg.h" |
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47 | #include "r200_vertprog.h" |
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48 | |||
49 | #ifndef R200_EMIT_VAP_PVS_CNTL |
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50 | #error This driver requires a newer libdrm to compile |
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51 | #endif |
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52 | |||
53 | #include "radeon_screen.h" |
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54 | #include "radeon_common.h" |
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55 | |||
56 | struct r200_context; |
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57 | typedef struct r200_context r200ContextRec; |
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58 | typedef struct r200_context *r200ContextPtr; |
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59 | |||
60 | #include "main/mm.h" |
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61 | |||
62 | struct r200_vertex_program { |
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63 | struct gl_vertex_program mesa_program; /* Must be first */ |
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64 | int translated; |
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65 | /* need excess instr: 1 for late loop checking, 2 for |
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66 | additional instr due to instr/attr, 3 for fog */ |
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67 | VERTEX_SHADER_INSTRUCTION instr[R200_VSF_MAX_INST + 6]; |
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68 | int pos_end; |
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69 | int inputs[VERT_ATTRIB_MAX]; |
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70 | GLubyte inputmap_rev[16]; |
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71 | int native; |
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72 | int fogpidx; |
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73 | int fogmode; |
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74 | }; |
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75 | |||
76 | #define R200_TEX_ALL 0x3f |
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77 | |||
78 | |||
79 | struct r200_texture_env_state { |
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80 | radeonTexObjPtr texobj; |
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81 | GLuint outputreg; |
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82 | GLuint unitneeded; |
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83 | }; |
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84 | |||
85 | #define R200_MAX_TEXTURE_UNITS 6 |
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86 | |||
87 | struct r200_texture_state { |
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88 | struct r200_texture_env_state unit[R200_MAX_TEXTURE_UNITS]; |
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89 | }; |
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90 | |||
91 | |||
92 | /* Trying to keep these relatively short as the variables are becoming |
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93 | * extravagently long. Drop the driver name prefix off the front of |
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94 | * everything - I think we know which driver we're in by now, and keep the |
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95 | * prefix to 3 letters unless absolutely impossible. |
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96 | */ |
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97 | |||
98 | #define CTX_CMD_0 0 |
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99 | #define CTX_PP_MISC 1 |
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100 | #define CTX_PP_FOG_COLOR 2 |
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101 | #define CTX_RE_SOLID_COLOR 3 |
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102 | #define CTX_RB3D_BLENDCNTL 4 |
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103 | #define CTX_RB3D_DEPTHOFFSET 5 |
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104 | #define CTX_RB3D_DEPTHPITCH 6 |
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105 | #define CTX_RB3D_ZSTENCILCNTL 7 |
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106 | #define CTX_CMD_1 8 |
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107 | #define CTX_PP_CNTL 9 |
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108 | #define CTX_RB3D_CNTL 10 |
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109 | #define CTX_RB3D_COLOROFFSET 11 |
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110 | #define CTX_CMD_2 12 /* why */ |
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111 | #define CTX_RB3D_COLORPITCH 13 /* why */ |
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112 | #define CTX_STATE_SIZE_OLDDRM 14 |
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113 | #define CTX_CMD_3 14 |
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114 | #define CTX_RB3D_BLENDCOLOR 15 |
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115 | #define CTX_RB3D_ABLENDCNTL 16 |
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116 | #define CTX_RB3D_CBLENDCNTL 17 |
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117 | #define CTX_STATE_SIZE_NEWDRM 18 |
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118 | |||
119 | #define SET_CMD_0 0 |
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120 | #define SET_SE_CNTL 1 |
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121 | #define SET_RE_CNTL 2 /* replace se_coord_fmt */ |
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122 | #define SET_STATE_SIZE 3 |
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123 | |||
124 | #define VTE_CMD_0 0 |
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125 | #define VTE_SE_VTE_CNTL 1 |
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126 | #define VTE_STATE_SIZE 2 |
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127 | |||
128 | #define LIN_CMD_0 0 |
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129 | #define LIN_RE_LINE_PATTERN 1 |
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130 | #define LIN_RE_LINE_STATE 2 |
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131 | #define LIN_CMD_1 3 |
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132 | #define LIN_SE_LINE_WIDTH 4 |
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133 | #define LIN_STATE_SIZE 5 |
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134 | |||
135 | #define MSK_CMD_0 0 |
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136 | #define MSK_RB3D_STENCILREFMASK 1 |
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137 | #define MSK_RB3D_ROPCNTL 2 |
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138 | #define MSK_RB3D_PLANEMASK 3 |
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139 | #define MSK_STATE_SIZE 4 |
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140 | |||
141 | #define VPT_CMD_0 0 |
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142 | #define VPT_SE_VPORT_XSCALE 1 |
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143 | #define VPT_SE_VPORT_XOFFSET 2 |
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144 | #define VPT_SE_VPORT_YSCALE 3 |
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145 | #define VPT_SE_VPORT_YOFFSET 4 |
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146 | #define VPT_SE_VPORT_ZSCALE 5 |
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147 | #define VPT_SE_VPORT_ZOFFSET 6 |
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148 | #define VPT_STATE_SIZE 7 |
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149 | |||
150 | #define ZBS_CMD_0 0 |
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151 | #define ZBS_SE_ZBIAS_FACTOR 1 |
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152 | #define ZBS_SE_ZBIAS_CONSTANT 2 |
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153 | #define ZBS_STATE_SIZE 3 |
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154 | |||
155 | #define MSC_CMD_0 0 |
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156 | #define MSC_RE_MISC 1 |
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157 | #define MSC_STATE_SIZE 2 |
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158 | |||
159 | #define TAM_CMD_0 0 |
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160 | #define TAM_DEBUG3 1 |
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161 | #define TAM_STATE_SIZE 2 |
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162 | |||
163 | #define TEX_CMD_0 0 |
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164 | #define TEX_PP_TXFILTER 1 /*2c00*/ |
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165 | #define TEX_PP_TXFORMAT 2 /*2c04*/ |
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166 | #define TEX_PP_TXFORMAT_X 3 /*2c08*/ |
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167 | #define TEX_PP_TXSIZE 4 /*2c0c*/ |
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168 | #define TEX_PP_TXPITCH 5 /*2c10*/ |
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169 | #define TEX_PP_BORDER_COLOR 6 /*2c14*/ |
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170 | #define TEX_CMD_1_OLDDRM 7 |
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171 | #define TEX_PP_TXOFFSET_OLDDRM 8 /*2d00 */ |
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172 | #define TEX_STATE_SIZE_OLDDRM 9 |
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173 | #define TEX_PP_CUBIC_FACES 7 |
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174 | #define TEX_PP_TXMULTI_CTL 8 |
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175 | #define TEX_CMD_1_NEWDRM 9 |
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176 | #define TEX_PP_TXOFFSET_NEWDRM 10 |
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177 | #define TEX_STATE_SIZE_NEWDRM 11 |
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178 | |||
179 | #define CUBE_CMD_0 0 /* 1 register follows */ /* this command unnecessary */ |
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180 | #define CUBE_PP_CUBIC_FACES 1 /* 0x2c18 */ /* with new enough drm */ |
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181 | #define CUBE_CMD_1 2 /* 5 registers follow */ |
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182 | #define CUBE_PP_CUBIC_OFFSET_F1 3 /* 0x2d04 */ |
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183 | #define CUBE_PP_CUBIC_OFFSET_F2 4 /* 0x2d08 */ |
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184 | #define CUBE_PP_CUBIC_OFFSET_F3 5 /* 0x2d0c */ |
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185 | #define CUBE_PP_CUBIC_OFFSET_F4 6 /* 0x2d10 */ |
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186 | #define CUBE_PP_CUBIC_OFFSET_F5 7 /* 0x2d14 */ |
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187 | #define CUBE_STATE_SIZE 8 |
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188 | |||
189 | #define PIX_CMD_0 0 |
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190 | #define PIX_PP_TXCBLEND 1 |
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191 | #define PIX_PP_TXCBLEND2 2 |
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192 | #define PIX_PP_TXABLEND 3 |
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193 | #define PIX_PP_TXABLEND2 4 |
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194 | #define PIX_STATE_SIZE 5 |
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195 | |||
196 | #define TF_CMD_0 0 |
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197 | #define TF_TFACTOR_0 1 |
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198 | #define TF_TFACTOR_1 2 |
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199 | #define TF_TFACTOR_2 3 |
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200 | #define TF_TFACTOR_3 4 |
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201 | #define TF_TFACTOR_4 5 |
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202 | #define TF_TFACTOR_5 6 |
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203 | #define TF_STATE_SIZE 7 |
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204 | |||
205 | #define ATF_CMD_0 0 |
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206 | #define ATF_TFACTOR_0 1 |
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207 | #define ATF_TFACTOR_1 2 |
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208 | #define ATF_TFACTOR_2 3 |
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209 | #define ATF_TFACTOR_3 4 |
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210 | #define ATF_TFACTOR_4 5 |
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211 | #define ATF_TFACTOR_5 6 |
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212 | #define ATF_TFACTOR_6 7 |
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213 | #define ATF_TFACTOR_7 8 |
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214 | #define ATF_STATE_SIZE 9 |
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215 | |||
216 | /* ATI_FRAGMENT_SHADER */ |
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217 | #define AFS_CMD_0 0 |
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218 | #define AFS_IC0 1 /* 2f00 */ |
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219 | #define AFS_IC1 2 /* 2f04 */ |
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220 | #define AFS_IA0 3 /* 2f08 */ |
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221 | #define AFS_IA1 4 /* 2f0c */ |
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222 | #define AFS_STATE_SIZE 33 |
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223 | |||
224 | #define PVS_CMD_0 0 |
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225 | #define PVS_CNTL_1 1 |
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226 | #define PVS_CNTL_2 2 |
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227 | #define PVS_STATE_SIZE 3 |
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228 | |||
229 | /* those are quite big... */ |
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230 | #define VPI_CMD_0 0 |
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231 | #define VPI_OPDST_0 1 |
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232 | #define VPI_SRC0_0 2 |
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233 | #define VPI_SRC1_0 3 |
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234 | #define VPI_SRC2_0 4 |
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235 | #define VPI_OPDST_63 253 |
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236 | #define VPI_SRC0_63 254 |
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237 | #define VPI_SRC1_63 255 |
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238 | #define VPI_SRC2_63 256 |
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239 | #define VPI_STATE_SIZE 257 |
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240 | |||
241 | #define VPP_CMD_0 0 |
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242 | #define VPP_PARAM0_0 1 |
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243 | #define VPP_PARAM1_0 2 |
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244 | #define VPP_PARAM2_0 3 |
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245 | #define VPP_PARAM3_0 4 |
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246 | #define VPP_PARAM0_95 381 |
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247 | #define VPP_PARAM1_95 382 |
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248 | #define VPP_PARAM2_95 383 |
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249 | #define VPP_PARAM3_95 384 |
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250 | #define VPP_STATE_SIZE 385 |
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251 | |||
252 | #define TCL_CMD_0 0 |
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253 | #define TCL_LIGHT_MODEL_CTL_0 1 |
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254 | #define TCL_LIGHT_MODEL_CTL_1 2 |
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255 | #define TCL_PER_LIGHT_CTL_0 3 |
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256 | #define TCL_PER_LIGHT_CTL_1 4 |
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257 | #define TCL_PER_LIGHT_CTL_2 5 |
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258 | #define TCL_PER_LIGHT_CTL_3 6 |
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259 | #define TCL_CMD_1 7 |
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260 | #define TCL_UCP_VERT_BLEND_CTL 8 |
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261 | #define TCL_STATE_SIZE 9 |
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262 | |||
263 | #define MSL_CMD_0 0 |
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264 | #define MSL_MATRIX_SELECT_0 1 |
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265 | #define MSL_MATRIX_SELECT_1 2 |
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266 | #define MSL_MATRIX_SELECT_2 3 |
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267 | #define MSL_MATRIX_SELECT_3 4 |
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268 | #define MSL_MATRIX_SELECT_4 5 |
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269 | #define MSL_STATE_SIZE 6 |
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270 | |||
271 | #define TCG_CMD_0 0 |
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272 | #define TCG_TEX_PROC_CTL_2 1 |
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273 | #define TCG_TEX_PROC_CTL_3 2 |
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274 | #define TCG_TEX_PROC_CTL_0 3 |
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275 | #define TCG_TEX_PROC_CTL_1 4 |
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276 | #define TCG_TEX_CYL_WRAP_CTL 5 |
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277 | #define TCG_STATE_SIZE 6 |
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278 | |||
279 | #define MTL_CMD_0 0 |
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280 | #define MTL_EMMISSIVE_RED 1 |
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281 | #define MTL_EMMISSIVE_GREEN 2 |
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282 | #define MTL_EMMISSIVE_BLUE 3 |
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283 | #define MTL_EMMISSIVE_ALPHA 4 |
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284 | #define MTL_AMBIENT_RED 5 |
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285 | #define MTL_AMBIENT_GREEN 6 |
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286 | #define MTL_AMBIENT_BLUE 7 |
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287 | #define MTL_AMBIENT_ALPHA 8 |
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288 | #define MTL_DIFFUSE_RED 9 |
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289 | #define MTL_DIFFUSE_GREEN 10 |
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290 | #define MTL_DIFFUSE_BLUE 11 |
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291 | #define MTL_DIFFUSE_ALPHA 12 |
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292 | #define MTL_SPECULAR_RED 13 |
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293 | #define MTL_SPECULAR_GREEN 14 |
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294 | #define MTL_SPECULAR_BLUE 15 |
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295 | #define MTL_SPECULAR_ALPHA 16 |
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296 | #define MTL_CMD_1 17 |
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297 | #define MTL_SHININESS 18 |
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298 | #define MTL_STATE_SIZE 19 |
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299 | |||
300 | #define VAP_CMD_0 0 |
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301 | #define VAP_SE_VAP_CNTL 1 |
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302 | #define VAP_STATE_SIZE 2 |
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303 | |||
304 | /* Replaces a lot of packet info from radeon |
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305 | */ |
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306 | #define VTX_CMD_0 0 |
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307 | #define VTX_VTXFMT_0 1 |
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308 | #define VTX_VTXFMT_1 2 |
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309 | #define VTX_TCL_OUTPUT_VTXFMT_0 3 |
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310 | #define VTX_TCL_OUTPUT_VTXFMT_1 4 |
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311 | #define VTX_CMD_1 5 |
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312 | #define VTX_TCL_OUTPUT_COMPSEL 6 |
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313 | #define VTX_CMD_2 7 |
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314 | #define VTX_STATE_CNTL 8 |
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315 | #define VTX_STATE_SIZE 9 |
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316 | |||
317 | /* SPR - point sprite state |
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318 | */ |
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319 | #define SPR_CMD_0 0 |
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320 | #define SPR_POINT_SPRITE_CNTL 1 |
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321 | #define SPR_STATE_SIZE 2 |
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322 | |||
323 | #define PTP_CMD_0 0 |
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324 | #define PTP_VPORT_SCALE_0 1 |
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325 | #define PTP_VPORT_SCALE_1 2 |
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326 | #define PTP_VPORT_SCALE_PTSIZE 3 |
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327 | #define PTP_VPORT_SCALE_3 4 |
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328 | #define PTP_CMD_1 5 |
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329 | #define PTP_ATT_CONST_QUAD 6 |
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330 | #define PTP_ATT_CONST_LIN 7 |
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331 | #define PTP_ATT_CONST_CON 8 |
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332 | #define PTP_ATT_CONST_3 9 |
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333 | #define PTP_EYE_X 10 |
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334 | #define PTP_EYE_Y 11 |
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335 | #define PTP_EYE_Z 12 |
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336 | #define PTP_EYE_3 13 |
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337 | #define PTP_CLAMP_MIN 14 |
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338 | #define PTP_CLAMP_MAX 15 |
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339 | #define PTP_CLAMP_2 16 |
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340 | #define PTP_CLAMP_3 17 |
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341 | #define PTP_STATE_SIZE 18 |
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342 | |||
343 | #define VTX_COLOR(v,n) (((v)>>(R200_VTX_COLOR_0_SHIFT+(n)*2))&\ |
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344 | R200_VTX_COLOR_MASK) |
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345 | |||
346 | /** |
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347 | * Given the \c R200_SE_VTX_FMT_1 for the current vertex state, determine |
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348 | * how many components are in texture coordinate \c n. |
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349 | */ |
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350 | #define VTX_TEXn_COUNT(v,n) (((v) >> (3 * n)) & 0x07) |
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351 | |||
352 | #define MAT_CMD_0 0 |
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353 | #define MAT_ELT_0 1 |
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354 | #define MAT_STATE_SIZE 17 |
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355 | |||
356 | #define GRD_CMD_0 0 |
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357 | #define GRD_VERT_GUARD_CLIP_ADJ 1 |
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358 | #define GRD_VERT_GUARD_DISCARD_ADJ 2 |
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359 | #define GRD_HORZ_GUARD_CLIP_ADJ 3 |
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360 | #define GRD_HORZ_GUARD_DISCARD_ADJ 4 |
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361 | #define GRD_STATE_SIZE 5 |
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362 | |||
363 | /* position changes frequently when lighting in modelpos - separate |
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364 | * out to new state item? |
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365 | */ |
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366 | #define LIT_CMD_0 0 |
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367 | #define LIT_AMBIENT_RED 1 |
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368 | #define LIT_AMBIENT_GREEN 2 |
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369 | #define LIT_AMBIENT_BLUE 3 |
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370 | #define LIT_AMBIENT_ALPHA 4 |
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371 | #define LIT_DIFFUSE_RED 5 |
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372 | #define LIT_DIFFUSE_GREEN 6 |
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373 | #define LIT_DIFFUSE_BLUE 7 |
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374 | #define LIT_DIFFUSE_ALPHA 8 |
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375 | #define LIT_SPECULAR_RED 9 |
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376 | #define LIT_SPECULAR_GREEN 10 |
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377 | #define LIT_SPECULAR_BLUE 11 |
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378 | #define LIT_SPECULAR_ALPHA 12 |
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379 | #define LIT_POSITION_X 13 |
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380 | #define LIT_POSITION_Y 14 |
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381 | #define LIT_POSITION_Z 15 |
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382 | #define LIT_POSITION_W 16 |
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383 | #define LIT_DIRECTION_X 17 |
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384 | #define LIT_DIRECTION_Y 18 |
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385 | #define LIT_DIRECTION_Z 19 |
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386 | #define LIT_DIRECTION_W 20 |
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387 | #define LIT_ATTEN_QUADRATIC 21 |
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388 | #define LIT_ATTEN_LINEAR 22 |
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389 | #define LIT_ATTEN_CONST 23 |
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390 | #define LIT_ATTEN_XXX 24 |
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391 | #define LIT_CMD_1 25 |
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392 | #define LIT_SPOT_DCD 26 |
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393 | #define LIT_SPOT_DCM 27 |
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394 | #define LIT_SPOT_EXPONENT 28 |
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395 | #define LIT_SPOT_CUTOFF 29 |
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396 | #define LIT_SPECULAR_THRESH 30 |
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397 | #define LIT_RANGE_CUTOFF 31 /* ? */ |
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398 | #define LIT_ATTEN_CONST_INV 32 |
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399 | #define LIT_STATE_SIZE 33 |
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400 | |||
401 | /* Fog |
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402 | */ |
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403 | #define FOG_CMD_0 0 |
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404 | #define FOG_R 1 |
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405 | #define FOG_C 2 |
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406 | #define FOG_D 3 |
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407 | #define FOG_PAD 4 |
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408 | #define FOG_STATE_SIZE 5 |
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409 | |||
410 | /* UCP |
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411 | */ |
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412 | #define UCP_CMD_0 0 |
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413 | #define UCP_X 1 |
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414 | #define UCP_Y 2 |
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415 | #define UCP_Z 3 |
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416 | #define UCP_W 4 |
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417 | #define UCP_STATE_SIZE 5 |
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418 | |||
419 | /* GLT - Global ambient |
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420 | */ |
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421 | #define GLT_CMD_0 0 |
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422 | #define GLT_RED 1 |
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423 | #define GLT_GREEN 2 |
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424 | #define GLT_BLUE 3 |
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425 | #define GLT_ALPHA 4 |
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426 | #define GLT_STATE_SIZE 5 |
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427 | |||
428 | /* EYE |
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429 | */ |
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430 | #define EYE_CMD_0 0 |
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431 | #define EYE_X 1 |
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432 | #define EYE_Y 2 |
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433 | #define EYE_Z 3 |
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434 | #define EYE_RESCALE_FACTOR 4 |
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435 | #define EYE_STATE_SIZE 5 |
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436 | |||
437 | /* CST - constant state |
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438 | */ |
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439 | #define CST_CMD_0 0 |
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440 | #define CST_PP_CNTL_X 1 |
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441 | #define CST_CMD_1 2 |
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442 | #define CST_RB3D_DEPTHXY_OFFSET 3 |
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443 | #define CST_CMD_2 4 |
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444 | #define CST_RE_AUX_SCISSOR_CNTL 5 |
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445 | #define CST_CMD_4 6 |
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446 | #define CST_SE_VAP_CNTL_STATUS 7 |
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447 | #define CST_CMD_5 8 |
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448 | #define CST_RE_POINTSIZE 9 |
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449 | #define CST_CMD_6 10 |
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450 | #define CST_SE_TCL_INPUT_VTX_0 11 |
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451 | #define CST_SE_TCL_INPUT_VTX_1 12 |
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452 | #define CST_SE_TCL_INPUT_VTX_2 13 |
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453 | #define CST_SE_TCL_INPUT_VTX_3 14 |
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454 | #define CST_STATE_SIZE 15 |
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455 | |||
456 | #define PRF_CMD_0 0 |
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457 | #define PRF_PP_TRI_PERF 1 |
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458 | #define PRF_PP_PERF_CNTL 2 |
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459 | #define PRF_STATE_SIZE 3 |
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460 | |||
461 | |||
462 | #define SCI_CMD_1 0 |
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463 | #define SCI_XY_1 1 |
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464 | #define SCI_CMD_2 2 |
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465 | #define SCI_XY_2 3 |
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466 | #define SCI_STATE_SIZE 4 |
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467 | |||
468 | #define R200_QUERYOBJ_CMD_0 0 |
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469 | #define R200_QUERYOBJ_DATA_0 1 |
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470 | #define R200_QUERYOBJ_CMDSIZE 2 |
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471 | |||
472 | #define STP_CMD_0 0 |
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473 | #define STP_DATA_0 1 |
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474 | #define STP_CMD_1 2 |
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475 | #define STP_STATE_SIZE 35 |
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476 | |||
477 | struct r200_hw_state { |
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478 | /* Hardware state, stored as cmdbuf commands: |
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479 | * -- Need to doublebuffer for |
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480 | * - reviving state after loss of context |
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481 | * - eliding noop statechange loops? (except line stipple count) |
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482 | */ |
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483 | struct radeon_state_atom ctx; |
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484 | struct radeon_state_atom set; |
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485 | struct radeon_state_atom sci; |
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486 | struct radeon_state_atom vte; |
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487 | struct radeon_state_atom lin; |
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488 | struct radeon_state_atom msk; |
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489 | struct radeon_state_atom vpt; |
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490 | struct radeon_state_atom vap; |
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491 | struct radeon_state_atom vtx; |
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492 | struct radeon_state_atom tcl; |
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493 | struct radeon_state_atom msl; |
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494 | struct radeon_state_atom tcg; |
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495 | struct radeon_state_atom msc; |
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496 | struct radeon_state_atom cst; |
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497 | struct radeon_state_atom tam; |
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498 | struct radeon_state_atom tf; |
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499 | struct radeon_state_atom tex[6]; |
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500 | struct radeon_state_atom cube[6]; |
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501 | struct radeon_state_atom zbs; |
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502 | struct radeon_state_atom mtl[2]; |
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503 | struct radeon_state_atom mat[9]; |
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504 | struct radeon_state_atom lit[8]; /* includes vec, scl commands */ |
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505 | struct radeon_state_atom ucp[6]; |
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506 | struct radeon_state_atom pix[6]; /* pixshader stages */ |
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507 | struct radeon_state_atom eye; /* eye pos */ |
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508 | struct radeon_state_atom grd; /* guard band clipping */ |
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509 | struct radeon_state_atom fog; |
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510 | struct radeon_state_atom glt; |
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511 | struct radeon_state_atom prf; |
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512 | struct radeon_state_atom afs[2]; |
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513 | struct radeon_state_atom pvs; |
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514 | struct radeon_state_atom vpi[2]; |
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515 | struct radeon_state_atom vpp[2]; |
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516 | struct radeon_state_atom atf; |
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517 | struct radeon_state_atom spr; |
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518 | struct radeon_state_atom ptp; |
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519 | struct radeon_state_atom stp; |
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520 | }; |
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521 | |||
522 | struct r200_state { |
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523 | /* Derived state for internal purposes: |
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524 | */ |
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525 | struct r200_texture_state texture; |
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526 | GLuint envneeded; |
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527 | }; |
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528 | |||
529 | #define R200_CMD_BUF_SZ (16*1024) |
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530 | |||
531 | #define R200_ELT_BUF_SZ (16*1024) |
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532 | /* r200_tcl.c |
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533 | */ |
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534 | struct r200_tcl_info { |
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535 | GLuint hw_primitive; |
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536 | |||
537 | int elt_used; |
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538 | |||
539 | }; |
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540 | |||
541 | |||
542 | /* r200_swtcl.c |
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543 | */ |
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544 | struct r200_swtcl_info { |
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545 | |||
546 | |||
547 | radeon_point_func draw_point; |
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548 | radeon_line_func draw_line; |
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549 | radeon_tri_func draw_tri; |
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550 | |||
551 | /** |
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552 | * Offset of the 4UB color data within a hardware (swtcl) vertex. |
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553 | */ |
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554 | GLuint coloroffset; |
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555 | |||
556 | /** |
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557 | * Offset of the 3UB specular color data within a hardware (swtcl) vertex. |
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558 | */ |
||
559 | GLuint specoffset; |
||
560 | |||
561 | /** |
||
562 | * Should Mesa project vertex data or will the hardware do it? |
||
563 | */ |
||
564 | GLboolean needproj; |
||
565 | }; |
||
566 | |||
567 | |||
568 | |||
569 | |||
570 | /* A maximum total of 29 elements per vertex: 3 floats for position, 3 |
||
571 | * floats for normal, 4 floats for color, 4 bytes for secondary color, |
||
572 | * 3 floats for each texture unit (18 floats total). |
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573 | * |
||
574 | * we maybe need add. 4 to prevent segfault if someone specifies |
||
575 | * GL_TEXTURE6/GL_TEXTURE7 (esp. for the codegen-path) (FIXME: ) |
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576 | * |
||
577 | * The position data is never actually stored here, so 3 elements could be |
||
578 | * trimmed out of the buffer. |
||
579 | */ |
||
580 | |||
581 | #define R200_MAX_VERTEX_SIZE ((3*6)+11) |
||
582 | |||
583 | struct r200_context { |
||
584 | struct radeon_context radeon; |
||
585 | |||
586 | /* Driver and hardware state management |
||
587 | */ |
||
588 | struct r200_hw_state hw; |
||
589 | struct r200_state state; |
||
590 | struct r200_vertex_program *curr_vp_hw; |
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591 | |||
592 | /* Vertex buffers |
||
593 | */ |
||
594 | struct radeon_ioctl ioctl; |
||
595 | struct radeon_store store; |
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596 | |||
597 | /* Clientdata textures; |
||
598 | */ |
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599 | GLuint prefer_gart_client_texturing; |
||
600 | |||
601 | /* TCL stuff |
||
602 | */ |
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603 | GLmatrix TexGenMatrix[R200_MAX_TEXTURE_UNITS]; |
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604 | GLboolean recheck_texgen[R200_MAX_TEXTURE_UNITS]; |
||
605 | GLboolean TexGenNeedNormals[R200_MAX_TEXTURE_UNITS]; |
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606 | GLuint TexMatEnabled; |
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607 | GLuint TexMatCompSel; |
||
608 | GLuint TexGenEnabled; |
||
609 | GLuint TexGenCompSel; |
||
610 | GLmatrix tmpmat; |
||
611 | |||
612 | /* r200_tcl.c |
||
613 | */ |
||
614 | struct r200_tcl_info tcl; |
||
615 | |||
616 | /* r200_swtcl.c |
||
617 | */ |
||
618 | struct r200_swtcl_info swtcl; |
||
619 | |||
620 | GLboolean using_hyperz; |
||
621 | GLboolean texmicrotile; |
||
622 | |||
623 | struct ati_fragment_shader *afs_loaded; |
||
624 | }; |
||
625 | |||
626 | |||
627 | static inline r200ContextPtr |
||
628 | R200_CONTEXT(struct gl_context *ctx) |
||
629 | { |
||
630 | return (r200ContextPtr) ctx; |
||
631 | } |
||
632 | |||
633 | |||
634 | extern void r200DestroyContext( __DRIcontext *driContextPriv ); |
||
635 | extern GLboolean r200CreateContext( gl_api api, |
||
636 | const struct gl_config *glVisual, |
||
637 | __DRIcontext *driContextPriv, |
||
638 | unsigned major_version, |
||
639 | unsigned minor_version, |
||
640 | uint32_t flags, |
||
641 | unsigned *error, |
||
642 | void *sharedContextPrivate); |
||
643 | extern GLboolean r200MakeCurrent( __DRIcontext *driContextPriv, |
||
644 | __DRIdrawable *driDrawPriv, |
||
645 | __DRIdrawable *driReadPriv ); |
||
646 | extern GLboolean r200UnbindContext( __DRIcontext *driContextPriv ); |
||
647 | |||
648 | extern void r200_init_texcopy_functions(struct dd_function_table *table); |
||
649 | |||
650 | /* ================================================================ |
||
651 | * Debugging: |
||
652 | */ |
||
653 | |||
654 | #define R200_DEBUG RADEON_DEBUG |
||
655 | |||
656 | |||
657 | |||
658 | #endif /* __R200_CONTEXT_H__ */ |