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/*
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 * Copyright © 2007 Intel Corporation
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 *
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 * Permission is hereby granted, free of charge, to any person obtaining a
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 * copy of this software and associated documentation files (the "Software"),
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 * to deal in the Software without restriction, including without limitation
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 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
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 * and/or sell copies of the Software, and to permit persons to whom the
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 * Software is furnished to do so, subject to the following conditions:
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 *
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 * The above copyright notice and this permission notice (including the next
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 * paragraph) shall be included in all copies or substantial portions of the
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 * Software.
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 *
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 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
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 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
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 * IN THE SOFTWARE.
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 *
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 * Authors:
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 *    Eric Anholt
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 *
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 */
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#define PCI_CHIP_IGD_GM			0xA011
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#define PCI_CHIP_IGD_G			0xA001
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#define IS_IGDGM(devid)	(devid == PCI_CHIP_IGD_GM)
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#define IS_IGDG(devid)	(devid == PCI_CHIP_IGD_G)
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#define IS_IGD(devid) (IS_IGDG(devid) || IS_IGDGM(devid))
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#define PCI_CHIP_I965_G			0x29A2
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#define PCI_CHIP_I965_Q			0x2992
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#define PCI_CHIP_I965_G_1		0x2982
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#define PCI_CHIP_I946_GZ		0x2972
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#define PCI_CHIP_I965_GM                0x2A02
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#define PCI_CHIP_I965_GME               0x2A12
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#define PCI_CHIP_GM45_GM                0x2A42
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#define PCI_CHIP_IGD_E_G                0x2E02
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#define PCI_CHIP_Q45_G                  0x2E12
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#define PCI_CHIP_G45_G                  0x2E22
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#define PCI_CHIP_G41_G                  0x2E32
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#define PCI_CHIP_B43_G                  0x2E42
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#define PCI_CHIP_B43_G1                 0x2E92
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#define PCI_CHIP_ILD_G                  0x0042
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#define PCI_CHIP_ILM_G                  0x0046
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#define PCI_CHIP_SANDYBRIDGE_GT1	0x0102	/* Desktop */
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#define PCI_CHIP_SANDYBRIDGE_GT2	0x0112
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#define PCI_CHIP_SANDYBRIDGE_GT2_PLUS	0x0122
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#define PCI_CHIP_SANDYBRIDGE_M_GT1	0x0106	/* Mobile */
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#define PCI_CHIP_SANDYBRIDGE_M_GT2	0x0116
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#define PCI_CHIP_SANDYBRIDGE_M_GT2_PLUS	0x0126
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#define PCI_CHIP_SANDYBRIDGE_S		0x010A	/* Server */
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#define PCI_CHIP_IVYBRIDGE_GT1          0x0152  /* Desktop */
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#define PCI_CHIP_IVYBRIDGE_GT2          0x0162
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#define PCI_CHIP_IVYBRIDGE_M_GT1        0x0156  /* Mobile */
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#define PCI_CHIP_IVYBRIDGE_M_GT2        0x0166
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#define PCI_CHIP_IVYBRIDGE_S_GT1        0x015a  /* Server */
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#define PCI_CHIP_IVYBRIDGE_S_GT2        0x016a
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#define PCI_CHIP_BAYTRAIL_M_1           0x0F31
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#define PCI_CHIP_BAYTRAIL_M_2           0x0F32
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#define PCI_CHIP_BAYTRAIL_M_3           0x0F33
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#define PCI_CHIP_BAYTRAIL_M_4           0x0157
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#define PCI_CHIP_BAYTRAIL_D             0x0155
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#define PCI_CHIP_HASWELL_GT1            0x0402 /* Desktop */
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#define PCI_CHIP_HASWELL_GT2            0x0412
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#define PCI_CHIP_HASWELL_GT3            0x0422
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#define PCI_CHIP_HASWELL_M_GT1          0x0406 /* Mobile */
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#define PCI_CHIP_HASWELL_M_GT2          0x0416
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#define PCI_CHIP_HASWELL_M_GT3          0x0426
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#define PCI_CHIP_HASWELL_S_GT1          0x040A /* Server */
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#define PCI_CHIP_HASWELL_S_GT2          0x041A
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#define PCI_CHIP_HASWELL_S_GT3          0x042A
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#define PCI_CHIP_HASWELL_B_GT1          0x040B /* Reserved */
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#define PCI_CHIP_HASWELL_B_GT2          0x041B
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#define PCI_CHIP_HASWELL_B_GT3          0x042B
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#define PCI_CHIP_HASWELL_E_GT1          0x040E /* Reserved */
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#define PCI_CHIP_HASWELL_E_GT2          0x041E
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#define PCI_CHIP_HASWELL_E_GT3          0x042E
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#define PCI_CHIP_HASWELL_SDV_GT1        0x0C02 /* Desktop */
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#define PCI_CHIP_HASWELL_SDV_GT2        0x0C12
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#define PCI_CHIP_HASWELL_SDV_GT3        0x0C22
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#define PCI_CHIP_HASWELL_SDV_M_GT1      0x0C06 /* Mobile */
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#define PCI_CHIP_HASWELL_SDV_M_GT2      0x0C16
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#define PCI_CHIP_HASWELL_SDV_M_GT3      0x0C26
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#define PCI_CHIP_HASWELL_SDV_S_GT1      0x0C0A /* Server */
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#define PCI_CHIP_HASWELL_SDV_S_GT2      0x0C1A
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#define PCI_CHIP_HASWELL_SDV_S_GT3      0x0C2A
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#define PCI_CHIP_HASWELL_SDV_B_GT1      0x0C0B /* Reserved */
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#define PCI_CHIP_HASWELL_SDV_B_GT2      0x0C1B
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#define PCI_CHIP_HASWELL_SDV_B_GT3      0x0C2B
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#define PCI_CHIP_HASWELL_SDV_E_GT1      0x0C0E /* Reserved */
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#define PCI_CHIP_HASWELL_SDV_E_GT2      0x0C1E
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#define PCI_CHIP_HASWELL_SDV_E_GT3      0x0C2E
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#define PCI_CHIP_HASWELL_ULT_GT1        0x0A02 /* Desktop */
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#define PCI_CHIP_HASWELL_ULT_GT2        0x0A12
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#define PCI_CHIP_HASWELL_ULT_GT3        0x0A22
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#define PCI_CHIP_HASWELL_ULT_M_GT1      0x0A06 /* Mobile */
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#define PCI_CHIP_HASWELL_ULT_M_GT2      0x0A16
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#define PCI_CHIP_HASWELL_ULT_M_GT3      0x0A26
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#define PCI_CHIP_HASWELL_ULT_S_GT1      0x0A0A /* Server */
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#define PCI_CHIP_HASWELL_ULT_S_GT2      0x0A1A
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#define PCI_CHIP_HASWELL_ULT_S_GT3      0x0A2A
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#define PCI_CHIP_HASWELL_ULT_B_GT1      0x0A0B /* Reserved */
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#define PCI_CHIP_HASWELL_ULT_B_GT2      0x0A1B
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#define PCI_CHIP_HASWELL_ULT_B_GT3      0x0A2B
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#define PCI_CHIP_HASWELL_ULT_E_GT1      0x0A0E /* Reserved */
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#define PCI_CHIP_HASWELL_ULT_E_GT2      0x0A1E
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#define PCI_CHIP_HASWELL_ULT_E_GT3      0x0A2E
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#define PCI_CHIP_HASWELL_CRW_GT1        0x0D02 /* Desktop */
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#define PCI_CHIP_HASWELL_CRW_GT2        0x0D12
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#define PCI_CHIP_HASWELL_CRW_GT3        0x0D22
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#define PCI_CHIP_HASWELL_CRW_M_GT1      0x0D06 /* Mobile */
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#define PCI_CHIP_HASWELL_CRW_M_GT2      0x0D16
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#define PCI_CHIP_HASWELL_CRW_M_GT3      0x0D26
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#define PCI_CHIP_HASWELL_CRW_S_GT1      0x0D0A /* Server */
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#define PCI_CHIP_HASWELL_CRW_S_GT2      0x0D1A
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#define PCI_CHIP_HASWELL_CRW_S_GT3      0x0D2A
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#define PCI_CHIP_HASWELL_CRW_B_GT1      0x0D0B /* Reserved */
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#define PCI_CHIP_HASWELL_CRW_B_GT2      0x0D1B
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#define PCI_CHIP_HASWELL_CRW_B_GT3      0x0D2B
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#define PCI_CHIP_HASWELL_CRW_E_GT1      0x0D0E /* Reserved */
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#define PCI_CHIP_HASWELL_CRW_E_GT2      0x0D1E
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#define PCI_CHIP_HASWELL_CRW_E_GT3      0x0D2E
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#define IS_G45(devid)           (devid == PCI_CHIP_IGD_E_G || \
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                                 devid == PCI_CHIP_Q45_G || \
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                                 devid == PCI_CHIP_G45_G || \
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                                 devid == PCI_CHIP_G41_G || \
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                                 devid == PCI_CHIP_B43_G || \
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                                 devid == PCI_CHIP_B43_G1)
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#define IS_GM45(devid)          (devid == PCI_CHIP_GM45_GM)
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#define IS_G4X(devid)		(IS_G45(devid) || IS_GM45(devid))
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#define IS_ILD(devid)           (devid == PCI_CHIP_ILD_G)
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#define IS_ILM(devid)           (devid == PCI_CHIP_ILM_G)
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#define IS_GEN5(devid)          (IS_ILD(devid) || IS_ILM(devid))
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#define IS_SNB_GT1(devid)	(devid == PCI_CHIP_SANDYBRIDGE_GT1 || \
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				 devid == PCI_CHIP_SANDYBRIDGE_M_GT1 || \
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				 devid == PCI_CHIP_SANDYBRIDGE_S)
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#define IS_SNB_GT2(devid)	(devid == PCI_CHIP_SANDYBRIDGE_GT2 || \
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				 devid == PCI_CHIP_SANDYBRIDGE_GT2_PLUS	|| \
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				 devid == PCI_CHIP_SANDYBRIDGE_M_GT2 || \
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				 devid == PCI_CHIP_SANDYBRIDGE_M_GT2_PLUS)
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#define IS_GEN6(devid)		(IS_SNB_GT1(devid) || IS_SNB_GT2(devid))
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#define IS_IVB_GT1(devid)       (devid == PCI_CHIP_IVYBRIDGE_GT1 || \
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				 devid == PCI_CHIP_IVYBRIDGE_M_GT1 || \
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				 devid == PCI_CHIP_IVYBRIDGE_S_GT1)
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#define IS_IVB_GT2(devid)       (devid == PCI_CHIP_IVYBRIDGE_GT2 || \
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				 devid == PCI_CHIP_IVYBRIDGE_M_GT2 || \
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				 devid == PCI_CHIP_IVYBRIDGE_S_GT2)
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#define IS_IVYBRIDGE(devid)     (IS_IVB_GT1(devid) || IS_IVB_GT2(devid))
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#define IS_BAYTRAIL(devid)      (devid == PCI_CHIP_BAYTRAIL_M_1 || \
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                                 devid == PCI_CHIP_BAYTRAIL_M_2 || \
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                                 devid == PCI_CHIP_BAYTRAIL_M_3 || \
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                                 devid == PCI_CHIP_BAYTRAIL_M_4 || \
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                                 devid == PCI_CHIP_BAYTRAIL_D)
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#define IS_GEN7(devid)	        (IS_IVYBRIDGE(devid) || \
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				 IS_BAYTRAIL(devid) || \
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				 IS_HASWELL(devid))
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#define IS_HSW_GT1(devid)	(devid == PCI_CHIP_HASWELL_GT1 || \
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				 devid == PCI_CHIP_HASWELL_M_GT1 || \
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				 devid == PCI_CHIP_HASWELL_S_GT1 || \
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				 devid == PCI_CHIP_HASWELL_B_GT1 || \
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				 devid == PCI_CHIP_HASWELL_E_GT1 || \
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				 devid == PCI_CHIP_HASWELL_SDV_GT1 || \
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				 devid == PCI_CHIP_HASWELL_SDV_M_GT1 || \
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				 devid == PCI_CHIP_HASWELL_SDV_S_GT1 || \
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				 devid == PCI_CHIP_HASWELL_SDV_B_GT1 || \
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				 devid == PCI_CHIP_HASWELL_SDV_E_GT1 || \
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				 devid == PCI_CHIP_HASWELL_ULT_GT1 || \
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				 devid == PCI_CHIP_HASWELL_ULT_M_GT1 || \
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				 devid == PCI_CHIP_HASWELL_ULT_S_GT1 || \
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				 devid == PCI_CHIP_HASWELL_ULT_B_GT1 || \
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				 devid == PCI_CHIP_HASWELL_ULT_E_GT1 || \
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				 devid == PCI_CHIP_HASWELL_CRW_GT1 || \
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				 devid == PCI_CHIP_HASWELL_CRW_M_GT1 || \
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				 devid == PCI_CHIP_HASWELL_CRW_S_GT1 || \
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				 devid == PCI_CHIP_HASWELL_CRW_B_GT1 || \
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				 devid == PCI_CHIP_HASWELL_CRW_E_GT1)
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#define IS_HSW_GT2(devid)	(devid == PCI_CHIP_HASWELL_GT2 || \
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				 devid == PCI_CHIP_HASWELL_M_GT2 || \
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				 devid == PCI_CHIP_HASWELL_S_GT2 || \
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				 devid == PCI_CHIP_HASWELL_B_GT2 || \
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				 devid == PCI_CHIP_HASWELL_E_GT2 || \
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				 devid == PCI_CHIP_HASWELL_SDV_GT2 || \
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				 devid == PCI_CHIP_HASWELL_SDV_M_GT2 || \
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				 devid == PCI_CHIP_HASWELL_SDV_S_GT2 || \
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				 devid == PCI_CHIP_HASWELL_SDV_B_GT2 || \
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				 devid == PCI_CHIP_HASWELL_SDV_E_GT2 || \
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				 devid == PCI_CHIP_HASWELL_ULT_GT2 || \
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				 devid == PCI_CHIP_HASWELL_ULT_M_GT2 || \
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				 devid == PCI_CHIP_HASWELL_ULT_S_GT2 || \
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				 devid == PCI_CHIP_HASWELL_ULT_B_GT2 || \
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				 devid == PCI_CHIP_HASWELL_ULT_E_GT2 || \
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				 devid == PCI_CHIP_HASWELL_CRW_GT2 || \
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				 devid == PCI_CHIP_HASWELL_CRW_M_GT2 || \
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				 devid == PCI_CHIP_HASWELL_CRW_S_GT2 || \
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				 devid == PCI_CHIP_HASWELL_CRW_B_GT2 || \
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				 devid == PCI_CHIP_HASWELL_CRW_E_GT2)
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#define IS_HSW_GT3(devid)	(devid == PCI_CHIP_HASWELL_GT3 || \
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				 devid == PCI_CHIP_HASWELL_M_GT3 || \
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				 devid == PCI_CHIP_HASWELL_S_GT3 || \
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				 devid == PCI_CHIP_HASWELL_B_GT3 || \
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				 devid == PCI_CHIP_HASWELL_E_GT3 || \
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				 devid == PCI_CHIP_HASWELL_SDV_GT3 || \
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				 devid == PCI_CHIP_HASWELL_SDV_M_GT3 || \
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				 devid == PCI_CHIP_HASWELL_SDV_S_GT3 || \
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				 devid == PCI_CHIP_HASWELL_SDV_B_GT3 || \
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				 devid == PCI_CHIP_HASWELL_SDV_E_GT3 || \
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				 devid == PCI_CHIP_HASWELL_ULT_GT3 || \
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				 devid == PCI_CHIP_HASWELL_ULT_M_GT3 || \
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				 devid == PCI_CHIP_HASWELL_ULT_S_GT3 || \
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				 devid == PCI_CHIP_HASWELL_ULT_B_GT3 || \
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				 devid == PCI_CHIP_HASWELL_ULT_E_GT3 || \
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				 devid == PCI_CHIP_HASWELL_CRW_GT3 || \
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				 devid == PCI_CHIP_HASWELL_CRW_M_GT3 || \
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				 devid == PCI_CHIP_HASWELL_CRW_S_GT3 || \
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				 devid == PCI_CHIP_HASWELL_CRW_B_GT3 || \
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				 devid == PCI_CHIP_HASWELL_CRW_E_GT3)
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#define IS_HASWELL(devid)       (IS_HSW_GT1(devid) || \
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				 IS_HSW_GT2(devid) || \
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				 IS_HSW_GT3(devid))